CN101977152A - High-performance network-on-chip system suitable for reconfiguration - Google Patents
High-performance network-on-chip system suitable for reconfiguration Download PDFInfo
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- CN101977152A CN101977152A CN2010105412673A CN201010541267A CN101977152A CN 101977152 A CN101977152 A CN 101977152A CN 2010105412673 A CN2010105412673 A CN 2010105412673A CN 201010541267 A CN201010541267 A CN 201010541267A CN 101977152 A CN101977152 A CN 101977152A
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Abstract
The invention belongs to the technical field of network-on-chip system designs, and in particular relates to a high-performance network-on-chip system suitable for reconfiguration. By adding a plurality of reconfigurable circuit IP cores, such as an FPGAIP (Field Programmable Gate Array Internet Protocol) core, and a plurality of configuration bit stream storage unit IP cores in a network-on-chip node, a reconfigurable parallel operating system is realized. The traditional network-on-chip structure is improved, and a sub-network suitable for reconfiguration is added, so that the reconfiguration of the system can be completed at high speed during the reconfiguration, without influencing the normal network communication function. The high-performance network-on-chip system ensures that the network integrates double characteristics of packet switching and circuit switching, and has an important meaning for constructing a high-performance reconfiguration system.
Description
Technical field
The invention belongs to the network-on-a-chip design field, be specifically related to a kind of high-performance network-on-a-chip that is suitable for reconstruct.
Background technology
Along with improving constantly of single-chip integrated level, the continuous increase of IP module in the system, bus-structured organizational form shows increasing constraint.Module constantly increases, and bus performance but can not correspondingly promote.In recent years, the proposition of network-on-chip (NoC) structure efficiently solved this contradiction.
But, when network-on-chip is used for the restructural application, unsatisfactory.Owing to when reshuffling, require configuration to finish as early as possible, reshuffle the bit stream high efficiency of transmission, traditional NoC network can't adapt to.At this situation, the present invention proposes the high-performance network-on-a-chip framework that is suitable for reconstruct, and improved network configuration, carried out the optimal design of network at the reconstruct feature.
Summary of the invention
Goal of the invention of the present invention is to provide a kind of high performance network-on-a-chip that is suitable for reconstruct.
High-performance network-on-a-chip provided by the invention is to add reconfigurable circuit IP kernel and bit stream memory cell IP kernel in network-on-a-chip, and has improved network service foundation structure, has made up the high performance parallel arithmetic system that is suitable for reconstruct.
In network-on-a-chip, add the reconfigurable circuit IP kernel, as the FPGA IP kernel, just make SOC (system on a chip) have the restructural characteristic.This system uses for realizing that restructural is parallel, is significant.
Make up the reconfigurable network system, promptly on the network-on-chip basis, each node is inserted various computing units and reconstructed module respectively, as processor (CPU), memory (SRAM), reconfigurable circuit (FPGA), configuration bit stream memory cell, dedicated processes hardware (ASIC, RFID), Peripheral Interface etc.Each unit all has resource network interface (RNI) to be connected to router.
Because during reshuffling, reshuffle the unit and need great amount of data transmission, traditional packet network communication structure can't satisfy its bandwidth demand.For this reason, the present invention adds in network configuration and reshuffles private access, make itself and conventional communication networks is parallel exists, during reshuffling, be connected to form special use and reshuffle the circuit switching path, make and reshuffle and can finish at a high speed.In addition, because the adding of this configuration network, must add in the routing infrastructure has the module that connects control for reshuffling.This structure combines the flexibility and the Circuit-switched high performance nature of packet network.
In addition, any universal or special IP kernel that needs high speed data transfer can be connected to high-speed data channel (promptly reshuffling private access) and come up, can improve the performance of total system like this, as: processor IP, DSP IP, exclusive data processing ASIC IP kernel etc.
Technique effect:
After having adopted this reconfigurable network-on-chip, system can have both the high-performance of concurrent operation and the advantage of the flexibility that restructural calculates.
Description of drawings
Fig. 1 is a restructural network-on-a-chip example.
Fig. 2 is a restructural network-on-chip routing interface.
Embodiment
At first in network node, add reconfigurable circuit FPGA IP kernel and dispose bit stream storage unit circuit IP kernel accordingly.In conventional network-on-chip, add the configure dedicated express network, and make route add configuration transmission controlled function.Describe with an example below.
Accompanying drawing 1 is a possible restructural network-on-a-chip example.It is made of the mesh network of a 3x3, comprises 9 routing nodes, is designated as R11, R12, R13, R21, R22, R23, R31, R32, R33.Node inserts various possible IP kernels respectively, as processor (CPU), memory (SRAM), reconfigurable circuit (FPGA), and configuration bit stream memory cell, dedicated processes hardware (ASIC, RFID), Peripheral Interface etc.Each unit all has resource network interface (RNI) to be connected to router.Yellow arrows has been represented the general communication network, and red arrow is the specialized configuration passage at the restructural characteristics design.As seen from the figure, the FPGA IP kernel has been connected designated lane to router with configuration bit stream memory cell IP kernel.When reshuffling when carrying out, configuration bit stream is by the high-speed channel high efficiency of transmission, and this has improved allocative efficiency on the one hand, has saved the general communication resource on the other hand again, makes layoutprocedure not influence the operate as normal of other modules.
Accompanying drawing 2 is depicted as the routing interface part in this network.Because the adding of configuration sub-network is different with conventional route, need in this route to add and reshuffle transmission control module, comprise the route control of reshuffling transmission, and conventional transmission and the coordination control of reshuffling transmission.In addition, the resource network interface also has been divided into conventional coffret and reconfiguration data interface, and the reconfiguration data interface often is included in the configuration control circuit of reshuffling IP kernel.When reshuffling transmission when carrying out, Route Selection is determined switched circuit, makes configuration data reshuffle the interface high-speed transfer from the bit stream memory cell to RNI then.In this stage, the conventional route transmission of this route still can be moved, and still can correctly transmit by this route based on the networking data of packet switch.Like this, one in conjunction with packet switch and Circuit-switched routing infrastructure, can effectively improve systematic function.
The example system of Fig. 1 realizes encryption and decryption functions.Owing in the encryption and decryption computing, have a large amount of general-purpose operation, and computing has concurrency, this for the reconstruct concurrent operation provides may.Universal operating unit is designed to special-purpose ASIC IP kernel, and with the difference circuit be set to respectively two kinds the configuration bit streams be stored in two bit stream memory cell.When encrypting, configuration all is configured to encrypted circuit with two FPGA, all is configured to decrypt circuit during deciphering, and this just can allow encryption and decryption parallel running in two FPGA.In addition, RFID can be used for chip identification, makes the chip can be tracked; Peripheral Interface IP is used for peripheral hardware mutual; Other adds CPU, makes that whole system can be by CPU control operation.
Workflow is as follows:
1, after system powered on, CPU started and carries out initial configuration by configure dedicated network control FPGA;
When 2, system carries out cryptographic calculation, can allow FPGA and ASIC work in coordination with and finish, and allow two FPGA carry out parallel computation;
3, when needs are decrypted, CPU control FPGA reshuffles, and at this moment, FPGA reshuffles by the configure dedicated network high-speed once more, notifies CPU by the NoC network after finishing;
4, after this, the CPU control FPGA decrypt operation that walks abreast.
As seen, this system has realized high performance restructural concurrent operation.
Claims (3)
1. high-performance network-on-a-chip that is suitable for reconstruct, it is characterized in that it being in network-on-a-chip, to add reconfigurable circuit IP kernel and bit stream memory cell IP kernel, and improvement network service foundation structure, structure is suitable for the high performance parallel arithmetic system of reconstruct, promptly on the network-on-chip basis, each node is inserted various computing units and reconstructed module respectively, comprise processor, memory, reconfigurable circuit, configuration bit stream memory cell, dedicated processes hardware and Peripheral Interface; Each unit all has the resource network interface to be connected to router; And add in network configuration and reshuffle private access, this reshuffles private access and the parallel existence of conventional communication networks.
2. the high-performance network-on-a-chip that is suitable for reconstruct according to claim 1 is characterized in that adding the module that has for reshuffling connection control in routing infrastructure.
3. the high-performance network-on-a-chip that is suitable for reconstruct according to claim 1 is characterized in that all IP kernels all are connected to reshuffle on the private access.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102413036A (en) * | 2011-08-22 | 2012-04-11 | 复旦大学 | Real-time partially and dynamically reconfigurable system |
| CN102752207A (en) * | 2012-07-06 | 2012-10-24 | 哈尔滨工业大学 | Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof |
| CN103412849A (en) * | 2013-08-02 | 2013-11-27 | 桂林电子科技大学 | NoC (network on chip) resource network interface of ARM processing unit and drive method of NoC resource network interface |
| CN103986672A (en) * | 2014-05-23 | 2014-08-13 | 清华大学 | Method and system for reconstructing on-chip network topological structure |
| WO2016000224A1 (en) * | 2014-07-02 | 2016-01-07 | 华为技术有限公司 | Computer system |
| CN106453258A (en) * | 2016-09-12 | 2017-02-22 | 中国电子科技集团公司第三十二研究所 | High-speed data encryption and decryption system and method |
| US10212497B2 (en) | 2013-10-22 | 2019-02-19 | Hewlett Packard Enterprise Development Lp | Hybrid circuit-packet switch |
| CN110659510A (en) * | 2019-09-12 | 2020-01-07 | 苏州浪潮智能科技有限公司 | Configuration file decryption method, device, equipment and readable storage medium |
| CN111786894A (en) * | 2020-07-01 | 2020-10-16 | 无锡中微亿芯有限公司 | FPGA device for realizing on-chip network transmission bandwidth expansion function |
| CN114205241A (en) * | 2021-11-19 | 2022-03-18 | 芯盟科技有限公司 | Network-on-chip |
| US11750510B2 (en) | 2020-07-01 | 2023-09-05 | Wuxi Esiontech Co., Ltd. | FPGA device for implementing expansion of transmission bandwidth of network-on-chip |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102413036A (en) * | 2011-08-22 | 2012-04-11 | 复旦大学 | Real-time partially and dynamically reconfigurable system |
| CN102752207A (en) * | 2012-07-06 | 2012-10-24 | 哈尔滨工业大学 | Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof |
| CN102752207B (en) * | 2012-07-06 | 2014-12-10 | 哈尔滨工业大学 | Reconfigurable 2D (two-dimensional) mesh on-chip network structure and reconfiguration method thereof |
| CN103412849A (en) * | 2013-08-02 | 2013-11-27 | 桂林电子科技大学 | NoC (network on chip) resource network interface of ARM processing unit and drive method of NoC resource network interface |
| US10212497B2 (en) | 2013-10-22 | 2019-02-19 | Hewlett Packard Enterprise Development Lp | Hybrid circuit-packet switch |
| CN103986672A (en) * | 2014-05-23 | 2014-08-13 | 清华大学 | Method and system for reconstructing on-chip network topological structure |
| CN103986672B (en) * | 2014-05-23 | 2017-12-19 | 清华大学 | The reconstructing method and system of Survey on network-on-chip topology |
| WO2016000224A1 (en) * | 2014-07-02 | 2016-01-07 | 华为技术有限公司 | Computer system |
| CN106453258A (en) * | 2016-09-12 | 2017-02-22 | 中国电子科技集团公司第三十二研究所 | High-speed data encryption and decryption system and method |
| CN106453258B (en) * | 2016-09-12 | 2020-04-03 | 中国电子科技集团公司第三十二研究所 | High-speed data encryption and decryption system |
| CN110659510A (en) * | 2019-09-12 | 2020-01-07 | 苏州浪潮智能科技有限公司 | Configuration file decryption method, device, equipment and readable storage medium |
| CN111786894A (en) * | 2020-07-01 | 2020-10-16 | 无锡中微亿芯有限公司 | FPGA device for realizing on-chip network transmission bandwidth expansion function |
| CN111786894B (en) * | 2020-07-01 | 2021-08-10 | 无锡中微亿芯有限公司 | FPGA device for realizing on-chip network transmission bandwidth expansion function |
| US11750510B2 (en) | 2020-07-01 | 2023-09-05 | Wuxi Esiontech Co., Ltd. | FPGA device for implementing expansion of transmission bandwidth of network-on-chip |
| CN114205241A (en) * | 2021-11-19 | 2022-03-18 | 芯盟科技有限公司 | Network-on-chip |
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Application publication date: 20110216 |