CN101977063B - General LDPC decoder - Google Patents
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- CN101977063B CN101977063B CN 201010532675 CN201010532675A CN101977063B CN 101977063 B CN101977063 B CN 101977063B CN 201010532675 CN201010532675 CN 201010532675 CN 201010532675 A CN201010532675 A CN 201010532675A CN 101977063 B CN101977063 B CN 101977063B
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Abstract
The invention discloses a general LDPC (low-density parity check code) decoder, which comprises a dispatching module, an input module, a decoding module and an output module. The input module, the decoding module and the output module work independently under the control of the dispatching module by adopting a mode of a state machine, wherein the decoding module has general hardware design and can decode LDPC of different lengths.
Description
Technical field
The present invention relates to a kind of ldpc code decoder, particularly have the ldpc decoder of versatility, belong to the decoding technique field.
Background technology
Along with the development of the technology such as deep space communication, mobile satellite communication, low signal-to-noise ratio communication becomes an important directions of development communication technologies.In order to communicate reliably, the chnnel coding of high-gain becomes the indispensable part of low signal-to-noise ratio communication system, in the error correction coding of inventing and using up to now, only has Turbo code and LDPC code to have performance near shannon limit.Compare with Turbo code, the LDPC code all has obvious advantage aspect arithmetic speed, decoding threshold and the error floor, become the study hotspot of current field of channel coding.Europe digital television broadcasting tissue (DVB) has been announced to abandon Turbo code in its satellite digital TV standard of future generation (DVB-S2) and has been adopted the LDPC code as the encoding scheme of forward error correction.And cellular mobile communication of future generation, wideband satellite communication, wireless personal-area network (802.15), wireless mobile broadband access network (802.20) and other communication systems such as data storage medium device access and wire line MODEM (Cable Modem), Digital Subscriber Line (DSL) are also being considered it as the chnnel coding standard.
LDPC (Low-Density Parity Check Code) code is a kind of linear block codes, and its check matrix is a very sparse matrix, the quantity of the nonzero element in the matrix with respect to ranks length seldom.If each row of check matrix (or row) have identical weight to claim that this LDPC code is regular, otherwise are called abnormal LDPC code.Because the position of element 1 does not have rule to follow substantially in the check matrix of irregular LDPC codes, causes encoder complexity high, realize that difficulty is larger.And regular LDPC code, particularly accurate cycline rule LDPC code can adopt simple shift register to finish coding, and hardware complexity reduces greatly.
Existing ldpc code decoder does not possess versatility basically, and the corresponding a kind of decoder of a kind of code length needs to redesign decoder after the variation code length, has greatly increased research and development time and R﹠D costs.For the ldpc decoder that uses on the star, because operational environment is special, must have a kind of universal ldpc decoder to come compatible different communication system protocol, so the versatility of ldpc code decoder environment on star is particularly crucial.
Summary of the invention
Technology of the present invention is dealt with problems and is: overcome the deficiencies in the prior art, a kind of general LDPC decoder is provided.Employing the invention solves the incompatible problem of different code length ldpc code decoder, has realized decoding to different length LDPC code with universal decoding architecture.
Technical solution of the present invention is:
A kind of general LDPC decoder comprises scheduler module, receiver module, decoding module and sending module, and receiver module receives the LDPC coded data and coded data is outputed to decoding module piecemeal; Decoding module is deciphered the coded data of receiver module input, and decoding data is exported to sending module; Form information data output after the decoding data ordering of sending module with decoding module segmentation output, it is characterized in that: described scheduler module adopts state machine to achieve a butt joint with mode with the order of shaking hands and receives the mutual control of module, decoding module and sending module;
Described decoding module can be deciphered the LDPC coded data of general length, and decoding module comprises: code check node processing module CNPM
i, i=0......n-1, n are line number, the variable node processing module VNPM of check matrix protograph
j, j=0......m-1, m are columns, the data memory input Y of check matrix protograph
j, output data storage D
j, iterative computation memory R
IjAnd Q
Ij
VNPM
jHave i+1 from input and i the output from 0 to i-1 numbering of 0 to i numbering, VNPM
jThe input that is numbered i and Y
jOutput link to each other VNPM
jThe input of numbering from 0 to i-1 by number with R
IjOutput corresponding link to each other VNPM
jThe output of numbering from 0 to i-1 by number with Q
IjCorresponding linking to each other of input;
After receiving the data receiver instruction, VNPM
jWith Y
jThe coded data section of buffer memory input copies i time, and after preserving the coded data section, outputs to simultaneously continuous Q from i output again
IjIn;
After receiving the beginning translation instruction, decoding module enters iterative decoding process, VNPM
jData and the modifying factor inputted from i-1 input are multiplied each other at every turn, preserve acquired results again with after the coded data section addition of preserving; Again the result is exported simultaneously from i output, and be written to corresponding Q
IjWherein i-1 input as addend do not comprise and VNPM
jThe data that the identical input of numbering j is inputted;
CNPM
iHave j from the input of 0 to j-1 numbering and the output of j 0 to j-1 numbering; CNPM
iJ input by number with Q
IjOutput corresponding link to each other CNPM
iJ output by number with R
IjCorresponding linking to each other of input;
CNPM
jWith at every turn from the data of j input input the minimum and inferior little data of absolute value select; From the output output absolute value identical with the input numbering of input least absolute value data time little data, from the data of other j-1 output output absolute value minimum; CNPM
iThe data of j output port output are written to corresponding R
Qj
In iterative decoding process, CNPM
iAnd VNPM
jIteration is carried out work successively, and receives from Q respectively
IjAnd R
IjThe data of output, Q
IjAnd R
IjIn output during data, when reading last iteration according to the reading address circulation of predesignating respectively by VNPM
jAnd CNPM
iThe data that write; The Q that subscript is identical
IjAnd R
IjBe one group corresponding to each node element in the every row of check matrix protograph, one group of Q
JqAnd R
JqHave identical reading address and end address, described reading address equals and Q
JqAnd R
JqThe side-play amount of submatrix after the corresponding node element expansion; Described end address equals and Q
JqAnd R
JqThe order of submatrix after the corresponding node element expansion; Described reading address and end address need to be configured according to code length before the decoding again;
After receiving the end translation instruction, VNPM
jNumbering after suing for peace with the coded data section of preservation, the data of 0 to i-1 input input is carried out outputing to D from 1 output behind the hard decision
j, and by D
jOrder is exported decoding data by number.
Described decoding module also can be designed to comprise: code check node processing module CNPM
i, i=0......n-1, n are line number, the variable node processing module VNPM of check matrix protograph
j, j=0......m-1, m are columns, the data memory input Y of check matrix protograph
j, output data storage D
j, iterative computation memory R
QjAnd Q
Qj, q=0......k-1, k are the number of check-node in the every row of check matrix protograph;
VNPM
jHave k+1 from input and k the output from 0 to k-1 numbering of 0 to k numbering, VNPM
jThe input that is numbered k and Y
jOutput link to each other VNPM
jThe input of numbering from 0 to k-1 by number with R
QjOutput corresponding link to each other VNPM
jThe output of numbering from 0 to k-1 by number with Q
QjCorresponding linking to each other of input;
After receiving the data receiver instruction, VNPM
jWith Y
jThe coded data section of buffer memory input copies k time, and after preserving the coded data section, exports simultaneously from k output again;
After receiving the beginning translation instruction, decoding module enters iterative decoding process, VNPM
jData and the modifying factor inputted from k-1 input are multiplied each other at every turn, preserve again with after the coded data section addition of preserving; The result is exported simultaneously from k output, and be written to corresponding Q
QjWherein k-1 input as addend do not comprise and VNPM
jThe data that the identical input of numbering j is inputted;
CNPM
iHave I from the input of 0 to I-1 numbering and the output of I 0 to I-1 numbering, described I is the number of variable node in the every row of check matrix protograph; CNPM
iI input and Q
QjOutput, press check matrix protograph i the position of variable node be corresponding in capable and link to each other CNPM
iI output and R
QjInput, press check matrix protograph i capable in corresponding linking to each other of position of variable node;
CNPM
iWith at every turn from the data of I input input the minimum and inferior little data of absolute value select; From the identical output output absolute value time little data of the input numbering of input least absolute value data, from the data of other I-1 output output absolute value minimum; CNPM
iThe data of I output port output are written to corresponding R
Qj
In iterative decoding process, CNPM
iAnd VNPM
jIteration is carried out work successively, and receives from Q respectively
JqAnd R
JqThe data of output, Q
JqAnd R
JqWhen the output data, read the data that last iteration writes according to the reading address circulation of predesignating; The identical Q of subscript
JqAnd R
JqBe one group and by row corresponding to the check-node in the every row of check matrix protograph, one group of Q
JqAnd R
JqHave identical reading address, described reading address equals and Q
JqAnd R
JqThe side-play amount of submatrix after the corresponding check-node expansion;
After receiving the end translation instruction, VNPM
jNumbering after suing for peace with the coded data section of preservation, the data of 0 to k-1 input input is carried out outputing to D from 1 output behind the hard decision
j, and by D
jOrder is exported decoding data by number.
Described general length is the integral multiple of the every row variable node of check matrix protograph number.
Described modifying factor value is at 0～1.
The present invention compared with prior art has following advantage:
(1), the project organization that adopts of decoding module of the present invention, can realize the decoding to different code length LDPC, only need to reconfigure the LDPC code that reading address in the decoding module just can adapt to different code lengths, have good flexibility and extremely strong compatibility.
(2), adopt between modules of the present invention state machine to realize, each operational module works alone under the handshaking type control of scheduler module, has improved the reliability of decoder.
(2), because the present invention has universal decoding architecture, therefore can adopt fixing FPGA resource and cooperate external RAM to realize, and the FPGA resource occupation is few, logical resource does not increase with the increase of code length, save the software and hardware resources of design and implementation phase, especially be adapted to the spacecraft operational environment of resource-constrained.
Description of drawings
Fig. 1 is system block diagram of the present invention;
Fig. 2 is state machine diagram of the present invention;
Fig. 3 is the decoding module structural design drawing;
Fig. 4 is embodiment check matrix protograph;
Fig. 5 is the decoding performance curve chart.
Embodiment
One, inventive principle
The check matrix H of quasi-cyclic LDPC code
QcShown in (1), each submatrix A
I, jThe ring shift right permutation matrix of b * b or 0 matrix of b * b.
Because cyclic permutation matrices A
I, jForm be decided by the side-play amount of matrix fully, therefore, always can use mother matrix H
b=[p (i, j)]
M * nCharacterize check matrix H
Qc, wherein, p (i, j) is A
I, jSide-play amount.
If p (i, j)＞0 then represents H
QcThe A of correspondence in the matrix
I, jBe that side-play amount is the permutation matrix of p (i, j) to the right, namely by with unit matrix ring shift right p (i, j) position, can obtain A
I, j
If p (i, j)=0 then represents A
I, jBe unit matrix, namely unit matrix do not carried out cyclic shift;
If p (i, j)＜0 then represents A
I, jBe the full 0 matrix.
In design, just can represent check matrix H as long as store mother matrix like this
Qc, principle is so that possessed realizability to the general decoding method of LDPC code whereby.Just be based on the decoder of quasi-cyclic LDPC code in technical solutions according to the invention.
Protograph (J Thorpe, " Low-Density Parity-Check (LDPC) Codes Constructed from Protographs ", with D.Divsalar, " Construction of Protograph LDPC Codes with Linear Minimum Distance ") can think the check matrix of the LDPC code that number of nodes is less, the submatrix A in the corresponding (1)
I, j(matrix of b * b), b is 1 if make in protograph, then A
I, jOnly represent 0 and 1 two kind of value, therefore, protograph has all properties of LDPC code check matrix.LDPC code structure based on protograph is to expand A on the protograph basis
I, j, by changing the value of b, make decoder be common to the LDPC code of various code lengths.
Protograph is after obtaining the check matrix of LDPC code after the expansion, because A
I, jB greater than 1, so the expansion multiple is different, the A of same position
I, jMay corresponding multiple different side-play amount, different side-play amounts corresponds to also different with regard to performance that new LDPC code embodies, and therefore, when selecting the protograph check matrix, need to search for by Computer Simulation, selects the protograph matrix of an excellent performance.
Two, design
General LDPC decoder of the present invention comprises: scheduler module, receiver module, decoding module and sending module.As shown in Figure 1, be each intermodule connection diagram of decoder.
1, state machine design
Scheduler module is the global control module in the decoder, and scheduler module is carried out handshake method to other modules and controlled alternately, and namely scheduler module is sent control command to modules, wait for that module work is finished and commands in return after, send again next command.Whole decoder is to carry out work in the state machine mode of command driven.
As shown in Figure 2, be the state transition graph of decoder state machine.Adopt the triggering mode of operation of state machine to eliminate because code length changes impact on each resume module time, guaranteed simultaneously the concurrent working that is independent of each other between processing module also to have improved the reliability of decoder work.
Whole state machine comprises that 5 operating states are respectively: wait state Idle (free time), accepting state S1, variable node update mode S2, check-node update mode S3 and output state S4.
Idle state: be the initial operating state of decoder.Without transfer of data, be in the state of waiting for the scheduler module dispatching command between this moment modules.
S1 state: be the operating state of the receiver module of decoder.When having decoding data to arrive, scheduler module sends and receives order to receiver module, start receiver module and receive decoding data, receiver module cushions the decoding data of input, then the input sequence according to decoding data carries out fragmented storage, then reply and wait for the transmission order of scheduler module to scheduler module, receive that the decoding data after the rear receiver module of transmission order is with segmentation is exported to respectively and simultaneously decoding module.
S2, S3 state: be the state of the decoding module iterative decoding work of decoder.In decode procedure, S2 state and S3 cycle of states iteration are carried out, and wherein, the S2 state is the operating state of VNPM, upgrade operation corresponding to variable node; The S3 state is the operating state of CNPM, upgrades operation corresponding to check-node.
Decoding module when work, do not consider the code word size of the decoding data inputted, just beginning the decoding order and stopping the decoding order and carry out work according to scheduler module.When decoding module receive scheduler module begin decoding order after, begin to decipher.This moment, decoder was in the S2 state, then, carried out iterative decoding according to the conversion sequential loop of variable node information updating (S2 state), check-node information updating (S3 state) and calculated.Whenever finish a variable node renewal operation and be equivalent to finish iteration one time with check-node renewal operation, in the decode procedure, scheduler module is carried out accumulated counts to iterations.When reaching predetermined iterations, scheduler module sends to decoding module and ceases and desist order, and after decoding module receives and ceases and desist order, stops decoding, the output decoding data.
S4 state: be the state of the output module work of decoder.When decoding data output is arranged, the scheduling mould is determined and to be sent output command to output module, starts output data that output module the receives decoding module row buffering of going forward side by side, because the input data that the decoder receiver module receives are fragmented storage, therefore the data of exporting among the buffer memory D also will be exported successively, i.e. D
0Data all output complete after, export again D
1In data, the like.
2, modular design
Decoding module
The core of decoder is the decoding matrix module, decoding module of the present invention in conjunction with the protograph structure generation possess the LDPC decoding architecture of versatility.
Protograph is the check matrix of the quasi-cyclic LDPC code of a small-scale in essence, and it has stipulated the submatrix A of every delegation and each row
I, jNumber, and the position of full 0 matrix and non-zero matrix.When the design decoder, the structures shape of protograph the decoding architecture of LDPC code, therefore, only otherwise change the structure (being number and the position of non-zero matrix) of protograph, even the code length of LDPC coding changes, the decoding architecture of decoding module just can not change so, thereby makes decoder possess versatility.
Before the design decoding module, first the protograph of a preferred excellent performance is set up decoding architecture take this protograph as source, and the protograph of so-called excellent performance refers under identical error rate condition, if signal to noise ratio is lower, then the performance of protograph is better.When code length changes, do not change the structure of protograph, just adjust submatrix A
I, jSize and side-play amount make it satisfy the code length requirement, the size of submatrix can directly be calculated according to the code length value, side-play amount need to be deciphered simulation model by LDPC and screen.
Decoding module of the present invention is the purpose that reaches versatility, need the antithetical phrase matrix A
I, jThe change of size and side-play amount can self adaptation.When specific design, two kinds of project organizations have been adopted.
Structure one
For the check matrix protograph that a size is n * m, need n code check node processing module CNPM
i, and according to being numbered from 0 to n-1; M variable node processing module VNPM
j, and according to being numbered from 0 to m-1.Simultaneously, be coded data section and the segmentation output decoding data section of storing received module segmentation input, also need with in VNPM
jJ corresponding data memory input Y
jWith j output data storage D
j, Y
jAnd D
jBe numbered to m-1 according to 0 equally, and by number with corresponding VNPM
jLink.Submatrix corresponding to each element in the protograph check matrix obtains after expansion arranges iterative computation memory R simultaneously
IjAnd Q
Ij, a R
QjWith a Q
QjBe decided to be one group.
For variable node processing module VNPM
j, have i+1 from input and i the output from 0 to i-1 numbering of 0 to i numbering, VNPM
jI input and Y
jOutput link to each other VNPM
jThe input of numbering from 0 to i-1 by number with R
IjOutput corresponding link to each other VNPM
jThe output of numbering from 0 to i-1 by number with Q
IjCorresponding linking to each other of input.
For code check node processing module CNPM
i, have j from the input of 0 to j-1 numbering and the output of j 0 to j-1 numbering.CNPM
iJ from input and the Q of 0 to j-1 numbering
IjOutput correspondingly by number link to each other CNPM
iJ from output and the Q of 0 to j-1 numbering
IjInput corresponding linking to each other by number.
As shown in Figure 3, be check matrix protograph H=[A
Ij]
2 * 4The time, the decoding module that adopts structure one to realize.Among Fig. 3, be provided with 2 CNPM corresponding to the line number of check matrix protograph, columns is provided with 4 VNMP, and is provided with 2 * 4 groups of R and Q, is numbered according to ranks respectively.And connect according to above-mentioned connected mode.
Structure two
The check matrix protograph that is n * m to a size equally, structure two is compared with structure one, and its main distinction is that the R that uses and the quantity of Q become R
QjAnd Q
Qj, wherein, if preferentially arrange by row, then q is corresponding to the number k of check-node in the every row of check matrix protograph, according to being numbered from 0 to k-1.Then analyze in conjunction with the check matrix protograph, structure two with respect to structure one omitted corresponding in the check matrix protograph corresponding to R and the Q of 0 element position.
For adapting to the change of R and Q quantity, the input of VNPM and CNPM and output have carried out corresponding variation.For variable node processing module VNPM
j, have k+1 from input and k the output from 0 to k-1 numbering of 0 to k numbering, VNPM
jK input and Y
jOutput link to each other VNPM
jThe input of numbering from 0 to k-1 by number with R
QjOutput corresponding link to each other VNPM
jThe output of numbering from 0 to k-1 by number with Q
QjCorresponding linking to each other of input.
For code check node processing module CNPM
i, having I from the input of 0 to I-1 numbering and the output of I 0 to I-1 numbering, described I is the number of variable node in the every row of check matrix protograph.In the check matrix protograph, have a plurality of different variable nodes (number of variable node can be 0) in the delegation, so, for different CNPM
iWith VNPM
jHas different corresponding annexations.Because protograph is carrying out expanded type, be the submatrix of full 0 after the expansion of 0 element, therefore, when pressing the structure of this principle design decoding module, can further be summarized as, press the CNPM of line number
iWith the capable VNPM that has check-node of i in the check matrix protograph
jHave connection, and CNPM
iAnd VNPM
jTie point just be R
QjAnd Q
Qj
At CNPM
iAnd R
QjAnd Q
QjConnection the time, CNPM
iI from input and the Q of 0 to I-1 numbering
QjOutput, press check matrix protograph i the position of variable node be corresponding in capable and link to each other CNPM
iI from output and the R of 0 to I-1 numbering
QjInput, press check matrix protograph i capable in corresponding linking to each other of position of variable node.
This kind design, so that in the process of carrying out iteration, CNPM
iAnd VNPM
jCorrespondence position according to check-node and variable node carries out work respectively, thereby temporary transient idle CNPM can occur
iAnd VNPM
jBut since adopted with the check matrix protograph in the R of check-node (variable node) sum
QjAnd Q
Qj, therefore, R
QjAnd Q
QjIn each iterative process, all can be used, be in the work all the time.Further saved hardware resource with respect to structure one.
Decoding algorithm
The present invention adopted the property taken advantage of correction minimum and (MSMA) decoding algorithm decipher.
After receiving the beginning translation instruction, decoding module enters iterative decoding process, VNPM
jEach data and modifying factor from k-1 or i-1 input input multiplied each other, preserve again with after the coded data section addition of preserving; The result is exported simultaneously from k or i output, and be written among the corresponding Q; Wherein the input as addend does not comprise and VNPM
jThe data that the identical input of numbering j is inputted;
CNPM
iWith at every turn from the data of I or j input input the minimum and inferior little data of absolute value select; From the identical output output absolute value time little data of the input numbering of input least absolute value data, from the data of other I-1 or j-1 output output absolute value minimum; CNPM
iThe data of I or j output port output are written among the corresponding R.
In iterative decoding process, CNPM
iAnd VNPM
jReceive respectively from the data of coupled Q and R output.Q and R be in output during data, reads one group of Q of data that last iteration writes according to the reading address circulation of predesignating and have identical reading address with R, and reading address equals the side-play amount of gained submatrix after the check-node expansion corresponding with Q and R.
In every group of Q and R, the first address of data writing is 0, and end address is b-1, and b is the order of every group of Q and the corresponding check matrix protograph of R submatrix.The rule that circulation is read is, Q and R read the data that are temporary in wherein with address headed by the reading address ADDx that predesignates, and when reading data end address b-1, are reading until ADDx-1 since 0, read by this circulation, realize the wherein cyclic shift output of temporal data.
According to this design, only need to be in Q and R set in advance the initial address (reading address) of each reading out data according to the side-play amount of the submatrix of correspondence, CNPM
iAnd VNPM
jIndependently carry out respectively, the cumulative statistics of scheduler module iterations, thereby can be when code length changes, only need by reading address and b among each Q of routine change and the R, just can be in the situation that do not affect decoding architecture, LDPC code to different coding length is deciphered, and has realized the versatility design of decoder.
Design for structure two, owing to having omitted Q corresponding with 0 element in the check matrix protograph and R, but, the Q in the structure two and R still with the check matrix protograph in nonzero element have corresponding relation, therefore reading address can be set in the same way.
Receiver module
Be used for to receive the coded data of input decoder, and coded data is carried out segmentation, accepting module is according to Y in the decoding module to the segmentation principle of coded data
jNumber the coded data of input is carried out according to sequencing.Coded data section after segmentation is finished is under the control of scheduler module, and order is input to the Y of decoding module successively piecemeal
jIn, namely according to from Y
0To Y
mOrder receive.
Output module
Output module receives the decoding data section of decoding module output under the control of scheduler module, and the decoding data of segmentation output is reconfigured rear output.According to the sequencing of decoding module received code data segment, will export after the layout of decoding data section, namely according to from D
0To D
mOrder export.
Scheduler module
Scheduler module is controlled modules in the mode of state conversion and is worked alone the control of shaking hands of receiver module, decoding module and output module.
Three, embodiment
Below take 1/2 code check as example, the design process of the general ldpc decoder of configurable code length is described.
Protograph matrix such as Fig. 4 that this programme is selected by simulation model are according to the mother matrix H of QC-LDPC code in the decoding architecture of protograph design
b=[a
Ij]
8 * 16, decoding architecture comprises 8 code check node processing module CNPM, 16 variable node processing module VNPM; 16 data memory input Y; 16 output data storage D; 48 interactive information memory R; 48 interactive information memory Q.
48 groups of R and Q are divided into 16 row, the all corresponding VNPM of 3 groups of R that each lists and Q, in Fig. 4, the number of check-node in the every row of check matrix protograph, each VNPM has 4 inputs and 3 outputs, and wherein the 4th of each VNPM the input links to each other with Y.All the other 3 inputs connect respectively the output of 3 R in these row, and 3 outputs connect respectively the input of 3 Q in these row, and 1 output of concurrent multiplexing is used for exporting decoding data to D when decoding finishes.
CNPM has 6 inputs and 6 outputs equally.48 groups of R and Q will have 3 row after being divided into 16 row.8 code check node processing module CNPM correspond respectively to 8 row, and according to corresponding R and the Q of connecting in the position of every row variable node in Fig. 4 matrix.
The submatrix of protograph is the ring shift right permutation matrix of b * b in this programme, according to Fig. 4 as can be known, utilizes this check matrix protograph to decipher (the code length here is required to be 16 integral multiple) to the LDPC code of code length L=16*b.Before the use, by the simulation model of protograph to the LDPC code check matrix, can obtain the side-play amount of corresponding code length check matrix, and then the reading address of each R and Q can be set.
Use the fpga chip of the Virtex4SX55 of xilinx company in the present embodiment, the logical resource that takies is 25%, is equivalent to 1,500,000 logic.The capacity of memory Q and R is respectively (8*4kbits), like this when the configuration code length, as long as the size of submatrix is no more than the maximum size of memory Q (and R).According to code length formula L=16*b, when b=4k, code length is the longest to be 64k, and the code length in this scope is enough to satisfy the instructions for use of existing LDPC code.
In addition, adopt the decoder of the present invention's design also to have preferably decoding performance, as shown in Figure 5, the code length that the ldpc decoder of configurable code length generates respectively is the code performance curve of 6912 (" " lines) and 2048 (" zero " lines), X-axis is signal to noise ratio (eb/n0) among the figure, and Y-axis is the error rate.Data shows, code check is 1/2 in the CCSDS standard, and code length is that LDPC code eb/n0 under the 10-8 error rate condition of 8192 is 1.5dB; The LDPC code of code length 2048 eb/n0 under the 10-6 error rate condition is 2dB.More as can be known, the LDPC code of the configurable code length in this method on performance with the gap of CCSDS standard less than 0.3dB.
The unspecified part of the present invention belongs to general knowledge as well known to those skilled in the art.
Claims (5)
1. a general LDPC decoder comprises scheduler module, receiver module, decoding module and sending module, and receiver module receives the LDPC coded data and coded data is outputed to decoding module piecemeal; Decoding module is deciphered the coded data of receiver module input, and decoding data is exported to sending module; Form information data output after the decoding data ordering of sending module with decoding module segmentation output, it is characterized in that: described scheduler module adopts state machine to achieve a butt joint in the mode of the order of shaking hands and receives the mutual control of module, decoding module and sending module;
Described decoding module can be deciphered the LDPC coded data of general length, and decoding module comprises: code check node processing module CNPM
i, i=0......n-1, n are line number, the variable node processing module VNPM of check matrix protograph
j, j=0......m-1, m are columns, the data memory input Y of check matrix protograph
j, output data storage D
j, iterative computation memory R
IjAnd Q
Ij
VNPM
jHave i+1 from input and i the output from 0 to i-1 numbering of 0 to i numbering, VNPM
jThe input that is numbered i and Y
jOutput link to each other VNPM
jThe input of numbering from 0 to i-1 by number with R
IjOutput corresponding link to each other VNPM
jThe output of numbering from 0 to i-1 by number with Q
IjCorresponding linking to each other of input;
After receiving the data receiver instruction, VNPM
jWith Y
jThe coded data section of buffer memory input copies i time, and after preserving the coded data section, outputs to simultaneously continuous Q from i output again
IjIn;
After receiving the beginning translation instruction, decoding module enters iterative decoding process, VNPM
jData and the modifying factor inputted from i-1 input are multiplied each other at every turn, preserve acquired results again with after the coded data section addition of preserving; Again the result is exported simultaneously from i output, and be written to corresponding Q
IjWherein i-1 input as addend do not comprise and VNPM
jThe data that the identical input of numbering j is inputted;
CNPM
iHave j from the input of 0 to j-1 numbering and the output of j 0 to j-1 numbering; CNPM
iJ input by number with Q
IjOutput corresponding link to each other CNPM
iJ output by number with R
IjCorresponding linking to each other of input;
CNPM
iWith at every turn from the data of j input input the minimum and inferior little data of absolute value select; From the output output absolute value identical with the input numbering of input least absolute value data time little data, from the data of other j-1 output output absolute value minimum; CNPM
iThe data of j output port output are written to corresponding R
Qj
In iterative decoding process, CNPM
iAnd VNPM
jIteration is carried out work successively, and receives from Q respectively
IjAnd R
IjThe data of output, Q
IjAnd R
IjIn output during data, when reading last iteration according to the reading address circulation of predesignating respectively by VNPM
jThe data that write with CNPMi; The Q that subscript is identical
IjAnd R
IjBe one group corresponding to each node element in the every row of check matrix protograph, one group of Q
JqAnd R
JqHave identical reading address and end address, described reading address equals and Q
JqAnd R
JqThe side-play amount of submatrix after the corresponding node element expansion; Described end address equals and Q
JqAnd R
JqThe order of submatrix after the corresponding node element expansion; Described reading address and end address need to be configured according to code length before decoding;
After receiving the end translation instruction, VNPM
jNumbering after suing for peace with the coded data section of preservation, the data of 0 to i-1 input input is carried out outputing to D from 1 output behind the hard decision
j, and by D
jOrder is exported decoding data by number.
2. a kind of general LDPC decoder according to claim 1, it is characterized in that: described decoding module also can be designed to comprise: code check node processing module CNPM
i, i=0......n-1, n are line number, the variable node processing module VNPM of check matrix protograph
j, j=0......m-1, m are columns, the data memory input Y of check matrix protograph
j, output data storage D
j, iterative computation memory R
QjAnd Q
Qj, q=0......k-1, k are the number of check-node in the every row of check matrix protograph;
VNPM
jHave k+1 from input and k the output from 0 to k-1 numbering of 0 to k numbering, VNPM
jThe input that is numbered k and Y
jOutput link to each other VNPM
jThe input of numbering from 0 to k-1 by number with R
QjOutput corresponding link to each other VNPM
jThe output of numbering from 0 to k-1 by number with Q
QjCorresponding linking to each other of input;
After receiving the data receiver instruction, VNPM
jWith Y
jThe coded data section of buffer memory input copies k time, and after preserving the coded data section, exports simultaneously from k output again;
After receiving the beginning translation instruction, decoding module enters iterative decoding process, VNPM
jData and the modifying factor inputted from k-1 input are multiplied each other at every turn, preserve again with after the coded data section addition of preserving; The result is exported simultaneously from k output, and be written to corresponding Q
QjWherein k-1 input as addend do not comprise and VNPM
jThe data that the identical input of numbering j is inputted;
CNPM
iHave I from the input of 0 to I-1 numbering and the output of I 0 to I-1 numbering, described I is the number of variable node in the every row of check matrix protograph; CNPM
iI input and Q
QjOutput, press check matrix protograph i the position of variable node be corresponding in capable and link to each other CNPM
iI output and R
QjInput, press check matrix protograph i capable in corresponding linking to each other of position of variable node;
CNPM
iWith at every turn from the data of I input input the minimum and inferior little data of absolute value select; From the identical output output absolute value time little data of the input numbering of input least absolute value data, from the data of other I-1 output output absolute value minimum; CNPM
iThe data of I output port output are written to corresponding R
Qj
In iterative decoding process, CNPM
iAnd VNPM
jIteration is carried out work successively, and receives from Q respectively
JqAnd R
JqThe data of output, Q
JqAnd R
JqWhen the output data, read the data that last iteration writes according to the reading address circulation of predesignating; The identical Q of subscript
JqAnd R
JqBe one group and by row corresponding to the check-node in the every row of check matrix protograph, one group of Q
JqAnd R
JqHave identical reading address, described reading address equals and Q
JqAnd R
JqThe side-play amount of submatrix after the corresponding check-node expansion;
After receiving the end translation instruction, VNPM
jNumbering after suing for peace with the coded data section of preservation, the data of 0 to k-1 input input is carried out outputing to D from 1 output behind the hard decision
j, and by D
jOrder is exported decoding data by number.
3. a kind of general LDPC decoder according to claim 1, it is characterized in that: described general length is the integral multiple of the every row variable node of check matrix protograph number.
4. a kind of general LDPC decoder according to claim 1, it is characterized in that: described modifying factor value is at 0～1.
5. it is characterized in that: described modifying factor value 0.8125 according to claim 1 or 4 described a kind of general LDPC decoders.
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