CN101977042A - PWM or PSM dual-mode modulation control circuit used for switch voltage-stabilized supply - Google Patents
PWM or PSM dual-mode modulation control circuit used for switch voltage-stabilized supply Download PDFInfo
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Abstract
The invention discloses a Pulse-Width Modulation (PWM) or Pulse-slope Modulation (PSM) dual-mode modulation control circuit used for a switch voltage-stabilized supply, and belongs to the technical field of electronics. The PWM or PSM dual-mode modulation control circuit comprises a controllable current reference source Iref, a comparator, a switching control circuit Load_SM, wherein the controllable current reference resource Iref generates two reference voltage signals, namely vref0 and vref1, under the control of a pair of control signals D0 and D1, which have opposite phase positions; the comparator realizes the comparison output of the voltage SM of a drain terminal of a main switch tube and the reference voltage; and the switching control circuit Load_SM automatically switches the PWM or PSM modulation mode and updates the control signals D0 and D1. The PWM or PSM dual-mode modulation control circuit selects the PWM or PSM modulation mode according to the condition of load weight so as to ensure high efficiency in a whole load range of a system. In the PWM or PSM dual-mode modulation control circuit, the load condition is judged by directly converting a current into a voltage and comparing the voltage with the reference voltage without sampling the current on a power switch tube by using a current sampling circuit. Most of the PWM or PSM dual-mode modulation control circuit is a logical circuit, has low power consumption, occupies small chip area, and can remarkably improve the efficiency of the system.
Description
Technical field
The invention belongs to electronic technology field, relate to the switching power supply control circuit, specifically refer to a kind of control circuit that is used for switching power supply with PWM or PSM bimodulus modulation system.
Background technology
The normal modulation system that adopts has pulse-width-modulated mode PWM (PulseWidth Modulation) and pulse over-cycle phase modulating mode PSM (Pulse Skip Modulation) in the switching power supply (being power inverter), makes the output voltage of converter keep stable by negative feedback control loop.Pulse-width-modulated mode PWM specific implementation is: change if the variation of input voltage or load causes output voltage, sample circuit is sampled to output voltage, and it and reference voltage compared, and then, make output voltage stabilization according to changing the duty ratio regulate converter switches.Pulse over-cycle phase modulating mode PSM specific implementation is: change if the variation of input voltage or load causes output voltage, sample circuit is sampled to output voltage, and itself and reference voltage compared, and then determined whether that according to variation pulse is striden across, make output voltage stabilization.PSM is based on constant frequency constant-breadth CWCF (Constant Width Constant Frequency) modulating pulse, when converter output voltage during greater than reference voltage, to there be pulse to be striden across, otherwise will be always the on/off operating state under the impulse wave control of constant frequency constant-breadth, make the output voltage stabilization of converter thus.PWM is based on the constant frequency modulating pulse that broadens, and when converter output voltage during greater than reference voltage, the duty ratio of converter switches reduces; When converter output voltage during less than reference voltage, the duty ratio of converter switches increases; Make the output voltage stabilization of converter thus.It is faster that the PSM modulating mode has response speed, the higher advantage of efficient under underload, and under the PWM modulating mode, system effectiveness is higher when heavy duty, but, cause under underload system effectiveness lower because each clock cycle must conducting.In order in whole loading range, to realize greater efficiency, can consider in system, to adopt PSM and two kinds of mode of operations of PWM, when load is light, be operated in by it under higher PSM mode of operation of efficient by control circuit, when load is heavier, be operated under the higher PWM mode of operation of efficient by it, thereby the realization system has higher efficient in whole loading range by control circuit.
Summary of the invention
The invention provides a kind of PWM or PSM bimodulus modulation control circuit that is used for switching power supply, this control circuit can be selected PWM or PSM modulating mode according to loading condition, all has higher efficient with the assurance system in whole loading range; This control circuit does not need current sampling circuit to come electric current on the sampled power switching tube, but directly current conversion is become voltage and reference voltage relatively, thereby judges the weight situation of load; This control circuit major part is a logical circuit, and oneself power consumption is low, and chip occupying area is less, can significantly improve the efficient of system.
Detailed technology scheme of the present invention is:
A kind of PWM or PSM bimodulus modulation control circuit that is used for switching power supply as shown in Figure 1 to Figure 3, comprises controllable current a reference source Iref, comparator comp and control switching circuit Load_SM.
Described controllable current a reference source Iref is managed and bias current sources I by four NMOS pipe, three PMOS as shown in Figure 2
BForm.Three PMOS manage M01, M02 and M03 series connection, i.e. the drain electrode of M01 connects the source electrode of M02, and the drain electrode of M02 connects the source electrode of M03, and the source electrode of M01 connects input voltage vin.The gate interconnection of NMOS pipe MB, M0 and M1, the source electrode interconnection of NMOS pipe MB, M0 and M1 meets bias current sources I behind the drain electrode of NMOS pipe MB and the grid short circuit
BThe drain electrode of NMOS pipe M0 connects the source electrode of NMOS pipe M2, and the drain electrode of NMOS pipe M1 connects the source electrode of NMOS pipe M3; The drain electrode interconnection of NMOS pipe M2 and M3 also connects the drain electrode that PMOS manages M03.
The drain electrode of PMOS pipe M03 connects the positive input terminal of comparator comp, and the drain voltage SW of main switch connects the negative input end of comparator comp in the external switch stabilized voltage power supply.
Described control switching circuit Load_SM as shown in Figure 3, by two d type flip flops, two delayers, two inverters, two sequential detectors, two with door, one or and a selector form.The input of the output termination delayer 1 of comparator comp; The data input pin of the output termination d type flip flop 1 of delayer 1, the clock end of the output termination d type flip flop 1 of inverter 1; The in-phase output end of d type flip flop 1 connects the input of sequential detector 1, and the reversed-phase output of d type flip flop 1 connects the input of sequential detector 2; An input of the output termination of sequential detector 1 and door 1, an input of the output termination of sequential detector 2 and door 2; With door 1 and with the output signal of door 2 respectively as or two input signals of door, or the output signal of door is as the clock signal of d type flip flop 2; The reversed-phase output of d type flip flop 2 and data input pin short circuit, the in-phase output end of d type flip flop 2 meet the input of delayer 2 and the control input end S of selector respectively; The control signal D0 of delayer 2 output connect simultaneously inverter 2 input, with another input of door 1 and controllable current a reference source Iref in the grid of NMOS pipe M2, the control signal D1 of inverter 2 outputs connect simultaneously with another input of door 2 and controllable current a reference source Iref in the grid of NMOS pipe M3; Select input to import PSM or PWM modulation signal respectively for two of selector, when control input end S is high level, select the PWM modulation signal as output signal; When control input end S is low level, select the PSM modulation signal as output signal; The output signal of selector is respectively as the gate control signal of three PMOS pipe M01, M02 among the gate control signal of main switch in the external switch stabilized voltage power supply and the controllable current a reference source Iref and M03, simultaneously, the output signal of selector after inverter 1 is anti-phase as the clock signal of d type flip flop 1.
Figure 1 shows that the application of the present invention in typical buck power inverter.Under typical buck circuit-mode, main switch MPP source electrode meets input signal Vin, and grid meets control signal vg, and drain electrode (SW) connects an end of inductance L, the negative electrode of diode D and the negative terminal of comparator comp simultaneously respectively.The other end of inductance L meets capacitor C and load resistance R respectively, the other end ground connection of capacitor C and load resistance R, the plus earth of diode D, the positive termination controllable current benchmark Iref of comparator comp, comparator output comp_out meets control switching circuit Load_SM, other three inputs of Load_SM are respectively vg, PSM control signal and pwm control signal, and it is output as the grid control signal vg of control signal D0, D1 and main switch MPP.
The invention has the beneficial effects as follows:
PWM or the PSM bimodulus modulation control circuit that is used for switching power supply provided by the invention, this control circuit can select the control signal of PWM or PSM modulating mode to control main switch in the external switch stabilized voltage power supply according to the weight situation of external loading, all has higher efficient with the assurance system in whole loading range.Adopt main switch in the PSM modulating mode control external switch stabilized voltage power supply when externally load is light, and adopt main switch in the PWM modulating mode control external switch stabilized voltage power supply when externally load is heavier.Can realize the automatic switchover of PWM or PSM modulating mode when load variations, circuit is provided with lag function, guarantees that working state of system is stable, and variable oscillation can not knock-on under the different modulating pattern.In addition, this control circuit does not need current sampling circuit to come electric current on the sampled power switching tube, but directly current conversion is become voltage and reference voltage relatively, thereby judges the weight situation of load; This control circuit major part is a logical circuit, and oneself power consumption is low, and chip occupying area is less, can significantly improve the efficient of system.
Description of drawings
Fig. 1 is the PWM of switching power supply or the theory diagram of PSM bimodulus modulation control circuit of being used for provided by the invention.
Fig. 2 is controllable current a reference source and comparator circuit figure among the present invention.
Fig. 3 is the circuit diagram of control switching circuit Load_SM among the present invention.
Embodiment
Below in conjunction with accompanying drawing, be that the power inverter of buck structure is an example with the switching power supply, the operation principle that is used for the PWM or the PSM bimodulus modulation control circuit of switching power supply provided by the invention is described.
Be in the electric current on the main switch of the buck circuit under the interrupter duty pattern, can simulate with a triangular wave.As shown in Figure 2,3 PMOS pipe M01, M02 and M03 equivalences that are in dark linear zone of series connection are a resistance, adopt the gate control signal vg identical with main switch, and establishing the electric current that flows through M01, M02 and M03 is I
DAdopt a pair of anti-phase each other control signal D0 and D1 to control the conducting of NMOS pipe M2 and M3 among the controllable current a reference source Iref or end: when D0 be high level, when D1 is low level, M2 conducting, M3 end, and this moment, the voltage of controllable current a reference source Iref input comparator anode was vref0; When D0 be low level, when D1 is high level, M2 is by, M3 conducting, this moment, the voltage of controllable current a reference source Iref input comparator anode was vref1; By the breadth length ratio of M0 and M2 and M1 and M3 is set, make vref0 be slightly smaller than vref1, to realize hysteresis.The reference voltage vref1 that reference voltage vref0 that comparator produces main switch drain terminal voltage SW and control signal D0 or control signal D1 produce compares, when SW＞vref0, and the comparator output low level; When SW＜vref1, comparator output high level.
The clock of d type flip flop 1 is the gate control signal vg negate of main switch, have the same initial moment and cycle with comparator output signal comp_out, but comparator output signal comp_out is by after the delay of delayer 1, the output of delayer 1 just lags behind the clock of d type flip flop 1, and the input that can guarantee d type flip flop 1 like this can be sampled and obtain.
Sequential detector comprises two same sequential detectors 1 and sequential detector 2 as shown in Figure 3, and the function of each sequential detector is that the signal of input is judged, is respectively applied for PWM to the PSM mode is switched and PSM switches to the PWM mode detection.When sequential detector detects the low imput of a N continuous clock cycle, output high level (the big I of the value of N is made as between 4～8 according to actual conditions), otherwise output remains low level.Sequential detector has reduced the influence of comparator imbalance voltage, and the detection by a N continuous clock cycle input signal, makes the small sample perturbations of electric current be unlikely to cause the frequent switching of main switch modulating mode.
Two sequential detectors are respectively applied for continuous high level and the low level of detection comparator output signal comp_out, wherein sequential detector 1 is used for the continuous low level of detection comparator output, the anti-phase output that is input as d type flip flop 1 of sequential detector 2 is used for the continuous high level that detection comparator is exported.
When PSM when PWM switches, main switch drain terminal voltage SW and vref1 are compared.SW if a N continuous clock cycle is all exported high level, illustrates promptly that the electric current on the main switch is excessive less than vref1 comparator output high level then, illustrates that the PSM modulating mode is no longer suitable, need switch to pwm pattern at this moment.When PWM when PSM switches, main switch drain terminal voltage SW and vref0 are compared.SW is greater than vref0 comparator output low level then, if equal output low level of a N continuous clock cycle illustrates that then load is too small, pwm pattern can not obtain being higher than the efficient of PSM modulating mode again, need switch to the PSM modulating mode.It should be noted that D0, D1 are two internal control signals that phase place is opposite, be used for control and produce two voltage reference vref0 and vref1, and vref0 is less than vref1, to realize hysteresis.
Adopt selector to carry out final pattern control, the output signal of d type flip flop 2 is as the control input end S input signal of selector, when control input end S input signal is high level, select the PWM modulation signal for output and as the gate control signal vg of main switch; When control input end S input signal is low level, select the PSM modulation signal for output and as the gate control signal vg of main switch.The output of d type flip flop 2 produces control signal D0 by delayer 2, and control signal D0 produces control signal D1 by inverter 2.When system works during in the PWM modulating mode, control input end S input signal is a high level, and promptly D0 is high (through what postpones), and D1 is low.For sequential detector 1, when D0 is high, by with the character of door as can be known, D0 pair with its with signal do not exert an influence, with its with signal as directly having passed through; Concerning sequential detector 2, D1 is low, by with the character of door as can be known, no matter sequential detector 2 outputs are high level or low level, its result is always low; Again by or the character of door, low level and other signal carry out or, not to other with its mutually or signal exert an influence.Therefore, can get conclusion, when system works during in the PWM modulating mode, sequential detector 2 conductively-closeds, sequential detector 1 is with D0's and signal, through or door, former state is sent to the input end of clock of d type flip flop 2.In like manner, when system works during in the PSM modulating mode, D0 is low, sequential detector 1 conductively-closed, sequential detector 2 output signals and D1 with signal through or door, be sent to the input end of clock of d type flip flop 2 by former state.
Provided by the inventionly be used for the PWM of switching power supply or the course of work of PSM bimodulus modulation control circuit comprises: (1) PWM is to the handoff procedure of PSM: the zero hour, system works is in the PWM state, and D0 is high, and D1 is low.In the process that load reduces, main switch drain terminal voltage SW increases gradually, compares with vref0, produces the square wave comp_out of one-period, and delayer 1 postpones this square wave, is used for eliminating the risk phenomenon that circuit may exist.Waveform after the delay is by d type flip flop 1, is sampled at the rising edge of clock, and sampled result is d_out.D_out then enters sequential detector, by before narration as can be known, as PWM during to the PSM mode switch, below the output conductively-closed of No. one sequential detector 2, therefore, only need to be concerned about the output of sequential detector 1 this moment.Be output as low level when the output of sequential detector 1 detects d type flip flop 1 N clock cycle continuously, think that promptly load is too small, high level of sequential detector 1 output this moment.This high level be similarly high D0 carry out with, the result still is a high level, be sent to the input end of clock of d type flip flop 2, rising edge at this high level, the input of sampling d type flip flop 2 (promptly going up the anti-phase output of d type flip flop 2 constantly), because system works under the PWM pattern at this moment, S does not still become for high state this moment, the reversed-phase output of promptly going up a moment d type flip flop 2 is low, be that being input as of current time d type flip flop 2 is low, thereby current time d type flip flop 2 is output as lowly, selector control input end S is low, selector is selected the output of PSM modulation signal and as the gate control signal vg of main switch, has finally been realized the switching of PWM to PSM.(2) PSM is when PWM switches, and system starts working in the PSM state, and S, D0 are low, and D1 is high.Along with peripheral load increases gradually, main switch drain terminal voltage SW reduces gradually, compare with vref1, the same to the PSM switching with PWM, the output of comparator is through after postponing, sample by d type flip flop 1, the reversed-phase output signal of d type flip flop 1 is sent into sequential detector 2 detect, low if a N continuous clock cycle is, that is to say if a d_out N continuous clock cycle is height, just think that load is excessive, then produce a high level.By narration before as can be known, when D0 is low, above one tunnel conductively-closed, the output signal of sequential detector 2 is sent to the input end of clock of d type flip flop 2, rising edge at this high level, the input of sampling d type flip flop 2 (promptly going up the anti-phase output of d type flip flop 2 constantly), because S is low state, promptly go up the anti-phase height that is output as of a moment d type flip flop 2, therefore the current time d type flip flop is output as height, selector is selected the output of PWM modulation signal and as the gate control signal vg of main switch, has finally been realized the switching of PSM to PWM.
Claims (3)
1. a PWM or a PSM bimodulus modulation control circuit that is used for switching power supply comprises controllable current a reference source Iref, comparator comp and control switching circuit Load_SM;
Described controllable current a reference source Iref is managed and bias current sources I by four NMOS pipe, three PMOS
BForm; Three PMOS manage M01, M02 and M03 series connection, i.e. the drain electrode of M01 connects the source electrode of M02, and the drain electrode of M02 connects the source electrode of M03, and the source electrode of M01 connects input voltage vin; The gate interconnection of NMOS pipe MB, M0 and M1, the source electrode interconnection of NMOS pipe MB, M0 and M1 meets bias current sources I behind the drain electrode of NMOS pipe MB and the grid short circuit
BThe drain electrode of NMOS pipe M0 connects the source electrode of NMOS pipe M2, and the drain electrode of NMOS pipe M1 connects the source electrode of NMOS pipe M3; The drain electrode interconnection of NMOS pipe M2 and M3 also connects the drain electrode that PMOS manages M03;
The drain electrode of PMOS pipe M03 connects the positive input terminal of comparator comp, and the drain voltage SW of main switch connects the negative input end of comparator comp in the external switch stabilized voltage power supply;
Described control switching circuit Load_SM by two d type flip flops, two delayers, two inverters, two sequential detectors, two with door, one or and a selector form; The input of the output termination delayer 1 of comparator comp; The data input pin of the output termination d type flip flop 1 of delayer 1, the clock end of the output termination d type flip flop 1 of inverter 1; The in-phase output end of d type flip flop 1 connects the input of sequential detector 1, and the reversed-phase output of d type flip flop 1 connects the input of sequential detector 2; An input of the output termination of sequential detector 1 and door 1, an input of the output termination of sequential detector 2 and door 2; With door 1 and with the output signal of door 2 respectively as or two input signals of door, or the output signal of door is as the clock signal of d type flip flop 2; The reversed-phase output of d type flip flop 2 and data input pin short circuit, the in-phase output end of d type flip flop 2 meet the input of delayer 2 and the control input end S of selector respectively; The control signal D0 of delayer 2 output connect simultaneously inverter 2 input, with another input of door 1 and controllable current a reference source Iref in the grid of NMOS pipe M2, the control signal D1 of inverter 2 outputs connect simultaneously with another input of door 2 and controllable current a reference source Iref in the grid of NMOS pipe M3; Select input to import PSM or PWM modulation signal respectively for two of selector, when control input end S is high level, select the PWM modulation signal as output signal; When control input end S is low level, select the PSM modulation signal as output signal; The output signal of selector is respectively as the gate control signal of three PMOS pipe M01, M02 among the gate control signal of main switch in the external switch stabilized voltage power supply and the controllable current a reference source Iref and M03, simultaneously, the output signal of selector after inverter 1 is anti-phase as the clock signal of d type flip flop 1.
2. PWM or the PSM bimodulus modulation control circuit that is used for switching power supply according to claim 1, it is characterized in that, two sequential detectors among the described control switching circuit Load_SM are identical sequential detector, when sequential detector detects the low imput of a N continuous clock cycle, the output high level, otherwise output remains low level.
3. PWM or the PSM bimodulus modulation control circuit that is used for switching power supply according to claim 2 is characterized in that the span of described N is between 4～8.
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| CN106208709A (en) * | 2015-05-29 | 2016-12-07 | Ls产电株式会社 | Electric power conversion apparatus and the method for operation electric power conversion apparatus |
| CN108200707A (en) * | 2018-01-26 | 2018-06-22 | 中国海洋石油集团有限公司 | A kind of light source voltage control module |
| CN108270419A (en) * | 2018-02-28 | 2018-07-10 | 武汉优泰电子技术有限公司 | A kind of shaping circuit |
| CN108736695A (en) * | 2018-06-08 | 2018-11-02 | 山东超越数控电子股份有限公司 | A kind of the realization structure and method of PWM and PSM patterns seamless switching |
| CN110012575A (en) * | 2019-05-09 | 2019-07-12 | 杭州必易微电子有限公司 | Drive control circuit and control method |
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| CN106208709A (en) * | 2015-05-29 | 2016-12-07 | Ls产电株式会社 | Electric power conversion apparatus and the method for operation electric power conversion apparatus |
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| CN108200707A (en) * | 2018-01-26 | 2018-06-22 | 中国海洋石油集团有限公司 | A kind of light source voltage control module |
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| CN108270419A (en) * | 2018-02-28 | 2018-07-10 | 武汉优泰电子技术有限公司 | A kind of shaping circuit |
| CN108736695A (en) * | 2018-06-08 | 2018-11-02 | 山东超越数控电子股份有限公司 | A kind of the realization structure and method of PWM and PSM patterns seamless switching |
| CN110012575A (en) * | 2019-05-09 | 2019-07-12 | 杭州必易微电子有限公司 | Drive control circuit and control method |
| CN110012575B (en) * | 2019-05-09 | 2024-04-19 | 杭州必易微电子有限公司 | Drive control circuit and control method |
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