CN101977019B - H-bridge motor controller supporting unipolar and bipolar pulse width modulation control - Google Patents
H-bridge motor controller supporting unipolar and bipolar pulse width modulation control Download PDFInfo
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Abstract
The invention relates to an H-bridge motor controller supporting unipolar and bipolar pulse width modulation control, which comprises an interface management logic circuit, a channel control logic circuit, a fault detection logic circuit and a pulse width modulation logic circuit, wherein the interface management logic circuit is used for receiving data information, address information and clock signals from the exterior, and the data information comprises positive pulse width P, negative pulse width N, dead zone time D, period T and the like; the channel control logic circuit mainly comprises a channel gate control register, a period control register and a frequency divider; the fault detection logic circuit is used for detecting whether the positive pulse width P, the negative pulse width N, the dead zone time D and the period T meet the relation of P+N+2D=T; and the pulse width modulation logic circuit is used for controlling the conversion of an internal state machine according to the input positive pulse width P and negative pulse width N so as to output a corresponding PWM waveform signal for driving the motor to rotate correspondingly. The H-bridge motor controller realizes the output of unipolar and bipolar pulse width modulation waveform signals so as to meet the dual application requirements for high precision and low power consumption.
Description
Technical field
The present invention relates to the motor-driven controller of a kind of H bridge, relate in particular to a kind of H bridge electric machine controller of realizing single bipolar pulse-width modulation output.
Background technology
The PWM pulse-width modulation is that a kind of switching regulator stabilized voltage power supply is used, and is to utilize the numeral of microcontroller to export the technology that analog circuit is controlled.The largest benefit of utilizing pulse width modulation mode realization electric machine speed regulation is that the energy of power supply can be fully used, and the efficient of circuit is high.In addition, adopt pulse width modulation mode to make and obtain full supply voltage when loading on work, help overcoming the inherent coil resistance of motor like this and make motor produce bigger moment.Therefore, the PWM pulse-width modulation is the best means of direct current machine being carried out Digital Control, has been widely used in dc motor speed regulating.
In numerous application scenarios of motor, both required the motor forward rotation sometimes, also need the motor reverse rotation.This just requires motor driver both can export forward drive current to motor windings, can also export the reverse drive electric current.And the employing at present of this driver is the H bridge driver the most widely.Because the H bridge driver possesses the characteristic that positive and negative driving is arranged, and simple in structure, characteristics such as driving power is big, be widely used in the driving of stepping motor, alternating current machine and direct current machine etc.
To aspect the Electric Machine Control of H bridge driver, owing to there is dual-use demand, need adopt two kinds of modulation control modes, i.e. bipolar modulated control and one pole modulation control to Electric Machine Control to high accuracy and low-power consumption.The electric machine controller that possesses two kinds of modulation control modes at present adopts the electric machine control system of discrete element formation such as MCU, FPGA basically.Formerly application number is 200910251520.9 to the applicant, name is called " a kind of electric machine controller based on the H bridge driver " and proposed the circuit of single-chip integrated solution; But this patent only realizes the bipolar modulated control mode, and can't satisfy the application demand to one pole modulation control; And this scheme does not propose error condition and detects, and can't satisfy the application requirements of highly reliable system.
Summary of the invention
The object of the invention provides a kind of H bridge electric machine controller of supporting single bipolar pulse width modulation controlled and detecting various control error conditions automatically.
In order to achieve the above object, the technical scheme that the present invention adopted is: a kind of H bridge electric machine controller of supporting single bipolar pulse width modulation controlled, and its exportable at least one road PWM waveform signal, it comprises
The interface management logical circuit; It mainly is made up of address decoder and a plurality of register; Described interface management logical circuit is used for receiving from the outside and comprises data message, address information and clock signals such as direct impulse width P, reverse impulse width N, Dead Time D, cycle T, and after decoder for decoding, deposits the data message that receives in relevant register according to address information;
The channel control logic circuit, it mainly is made up of passage gating control register, periodic Control register and frequency divider, and described passage gating control register is used for the output channel gating signal; Said periodic Control register is used for periodic quantity is counted, and cycle count of every completion will be exported a triggering signal; Described frequency divider is used for clock signal is carried out frequency division;
The error detection logic circuit, whether its direct impulse width P, reverse impulse width N, Dead Time D and cycle T that is used to detect input satisfies the relation of P+N+2D=T, if do not satisfy, then output error interrupt signal is forbidden misdata output;
The pulse-width modulation logical circuit; It comprises at least one pulse-width modulation passage; After described error detection logic circuit inerrancy interrupt signal output and channel control logic circuit output channel gating signal and triggering signal, direct impulse width P, reverse impulse width N according to input control the conversion of its internal state machine; To export corresponding PWM waveform signal, be used for drive motors and do corresponding rotation.
Further, in the error detection logic circuit, when detecting direct impulse width P, reverse impulse width N, Dead Time D and cycle T relation be: (1) Dead Time D is less than 16 clock width; (2) forward drive pulse P and reverse drive pulse N sum are more than or equal to the cycle; (3) forward drive pulse P greater than cycle T or reverse drive pulse N greater than cycle T; When (4) forward drive pulse P and reverse drive pulse N sum have in the carry any; Error detection logic circuit output error interrupt signal is to the pulse-width modulation logical circuit; Described pulse-width modulation logical circuit will keep the one-period state normally to export, until input correct P, N, D value.
Described error detection logic circuit also comprises the relation of forward drive pulse P that is exported in each output cycle and reverse drive pulse N complete detection the whether; Promptly in an output cycle; Have only after P and all complete input of N, the controlled quentity controlled variable that just allows newly to import is loaded in the pulse-width modulation logical circuit.
Described pulse-width modulation logical circuit mainly is made up of controlled quentity controlled variable register, controlled quentity controlled variable buffer, counter buffer and pulse width control circuit; The count value of forward drive width P and reverse drive pulse duration N is written in the corresponding controlled quentity controlled variable register in the interface management logical circuit; After the output of error detection logic circuit inerrancy interrupt signal and channel control logic output channel gating and triggering signal; Data in the controlled quentity controlled variable register are loaded into corresponding controlled quentity controlled variable buffer; Data in the controlled quentity controlled variable buffer are written into counter buffer at the rising edge of the triggering signal that each sign output cycle begins; The value of counter buffer writes the corresponding counts device in the pulse width control circuit in next rising edge of clock signal again; Counter is counted respectively P, N, D controlled quentity controlled variable respectively, and every completion is once counted and will be produced a pulse redirect signal controlling state machine and carry out the state redirect, thus output corresponding modulation waveform.
The process of described state machine state redirect is: at electrification reset or when quitting work; State machine gets into idle waiting Idle state; Rising edge when the triggering signal that detects channel control logic output; And the value of current P counter is not equal to 0, and state machine gets into forward drive PD state, and the effective forward drive motor of output low level signal; If the value of current P counter equals 0, state machine gets into dead band Dead state, does not export any drive signal; After state machine got into forward drive state PD state, counter was done and is subtracted counting, after accomplishing the needed time counting of forward drive, produced state redirect signal, and state machine gets into dead band Dead state thereupon; Under the Dead state of dead band, rolling counters forward Dead Time, counting finish back generation state redirect signal; If the value of current N counter is not equal to 0, state machine gets into reverse drive ND state after detecting state redirect signal, output reverse drive motor signal; If the value of current N counter equals 0, state machine gets into idle waiting Idle state after detecting state redirect signal, not output drive signal; After state machine gets into reverse drive N state D; Counter subtracts counting, produces state redirect signal after the needed time up to accomplishing the reverse drive motor, and state machine gets into idle waiting Idle after receiving state redirect signal; So circulation realizes the output of single bipolar pulse modulation signal.
Described interface management logical circuit, channel control logic circuit, error detection logic circuit, pulse-width modulation logical circuit are integrated on the chip piece.
Owing to adopt technique scheme; The present invention has the following advantages: H bridge electric machine controller of the present invention; Through changing output mode to its input direct impulse width P, reverse impulse width N, Dead Time D and cycle T; Realize the output of single bipolar pulse-width modulation waveform signal, to satisfy the dual-use demand of high accuracy and low-power consumption.Simultaneously, it also is provided with the error detection logic circuit, under the situation that input signal makes a mistake, will keep the one-period state normally to export, and reliability is high.
Description of drawings
Accompanying drawing 2 is an one pole pulse-width modulation output waveform figure;
Accompanying drawing 3 is H bridge electric machine controller structure principle chart of the present invention;
Accompanying drawing 4 is channel control logic schematic block circuit diagram of the present invention;
Accompanying drawing 5 is error detection logic schematic block circuit diagram of the present invention;
Accompanying drawing 6 is pulse-width modulation logical circuit theory diagram of the present invention;
Accompanying drawing 7 is realized single bipolar pulsewidth output state transition diagram for pulse-width modulation logical circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the preferred specific embodiment of the present invention is described:
H bridge electric machine controller of the present invention can provide bipolar modulated control mode and one pole modulation control mode simultaneously; So-called bipolar modulated is exactly that existing forward motor-driven pulse P comprises reverse motor driving pulse N again in an output cycle, to the control of the motor difference decision by both.As shown in Figure 1, as forward motor-driven pulse duration P during, will control the motor forward rotation greater than reverse motor driving pulse width N; Forward motor-driven pulse duration P is during less than reverse motor driving pulse width N, with the drive motors counter-rotation; When forward motor-driven pulse duration P equals reverse motor driving pulse width N, drive motors not.Bipolar modulated mode drive motors precision is high, and is quiet, dynamic characteristic good, but that weak point is power consumption is bigger, is not suitable for using the Electric Machine Control that power consumption such as powered battery is had relatively high expectations.And the one pole modulation is in an output cycle, to have only wherein a kind of output pulse, and is as shown in Figure 2, if forward drive motor, just output forward motor-driven pulse P in each output cycle; And during the reverse drive motor, then only need output reverse motor driving pulse width N.This kind modulation system can effectively reduce power consumption, but there is static friction in system, and its dynamic and static characteristic and control precision have reduction.This shows that the pluses and minuses of two kinds of modulating modes exist complementary, thus in the work engineering of motor, can be bipolar through conversion and output mode one pole obtain the optimum efficiency of machine operation.As in the process of steering wheel work, the adjustment of steering wheel position can be selected the unipolar pulse modulation way of output earlier in earlier stage, carries out coarse regulation, can guarantee lower system drive power consumption; When the steering wheel position was adjusted near the target location, the variable bipolar pulse modulation way of output that is changed to was carried out fine control, thereby is effectively improved its control precision.
In order to realize the PWM pulse-width modulation output of two kinds of modulation control modes, H bridge controller of the present invention is made up of channel control logic circuit, error detection logic circuit, interface management logical circuit and pulse-width modulation logical circuit, and is as shown in Figure 3.Wherein, the interface management logical circuit mainly is an input function of accomplishing address decoding and data, guarantees that control data can normally be input to the inside circuit function register and store; The channel control logic circuit is mainly realized functions such as passage gating, output periodic Control and clock division; Error detection logic mainly is responsible for the input and the state of circuit are carried out wrong detection, in case detect wrong input, circuit will keep last correct output, until the correct controlled quentity controlled variable of input; The pulse-width modulation logical circuit is according to the controlled quentity controlled variable of input and the state of function register, exports correct pulse-width modulation waveform, control H bridge driver, and drive motors is done corresponding rotation.In the present embodiment, the pulse-width modulation logical circuit has 5 output channels, so can select the output of respective channel according to the use needs.Be elaborated in the face of each functional circuit down:
Said interface management logical circuit mainly is made up of address decoder and register, and the interface management circuit is used for receiving data information, address information and various control signal.Described data message comprises information such as direct impulse width P, reverse impulse width N, Dead Time D in the one-period, and described address information is mainly used in to above-mentioned data message provides register address distributes.In the present embodiment; Interface management logical circuit inside has 23 registers; Shown in the allocation information table 1 of each function register, address decoding circuitry is exactly that the address information of importing is linked with relevant register, realizes realizing the read-write operation to register through the address.
Table 1
Shown in Figure 4 is the channel control logic circuit theory diagrams, and it mainly realizes functions such as passage gating, output periodic Control and clock division, mainly is made up of passage gating control register, frequency divider and periodic Control register.The passage gate logic is exactly through gating that a channel control register realizes each passage being set and closing; Output periodic Control logic mainly is through one group of period register is set, and through a counter periodic quantity is counted, and triggering signal of 1 counting output of every completion excites the beginning in a new pulsewidth output cycle; Clock division circuits mainly is that clock is carried out frequency division, so that realize different accuracy of timekeepings.
Shown in Figure 5 is the error detection logic circuit theory diagrams, and it comprises that mainly controlled quentity controlled variable Data Detection and data integrity detect two parts functional circuit.The controlled quentity controlled variable Data Detection mainly detects controlled quentity controlled variable P, the N value (count value of controlled quentity controlled variable P value representation forward drive pulsewidth degree of input; The count value of controlled quentity controlled variable N value representation reverse drive pulsewidth degree) and the relation of dead band D (dead band is defined as not overlapping at interval between forward drive pulse P and the reverse drive pulse N), output cycle T, guarantee the minimum output valve in dead band simultaneously.Have following 4 aspects relation when detecting output controlled quentity controlled variable data: (1) Dead Time D is less than 16 clock width; (2) forward drive pulse P and reverse drive pulse N sum are more than or equal to the cycle; (3) forward drive pulse P greater than cycle T or reverse drive pulse N greater than cycle T; (4) forward drive pulse P and reverse drive pulse N sum have carry.As long as testing circuit detects the relation that there are above 4 aspects in input controlled quentity controlled variable data, then be judged as input controlled quentity controlled variable error in data, and the output error interrupt signal, forbid that misdata gets into the pulse-width modulation logical circuit.The circuit constant normal output that also will maintain the original state is until the input right value.
It is for the forward drive pulse P that guarantees to be exported in each output cycle is complete with the relation of reverse drive pulse N that data integrity detects logic, promptly in each output cycle, exports P and N must satisfy relational expression: P+N+2D=T; So in an output cycle, have only after P and N accomplish input, the controlled quentity controlled variable data load that just allows newly to import is in the pulse-width modulation logical circuit.Owing in the input process of controlled quentity controlled variable P, N, successively import, and the controlled quentity controlled variable of new input is loaded into the pulse-width modulation logical circuit when each output cycle begins by serial input mode.Imported before the cycle begins and might occur one of them controlled quentity controlled variable like this; And another controlled quentity controlled variable just is transfused to after the cycle begins; The new controlled quentity controlled variable of input is loaded when the cycle begins before cycle, and another controlled quentity controlled variable has loaded original value because of not having enough time to import.Load the imperfect mistake that occurs with regard to having occurred because of controlled quentity controlled variable like this.Therefore, whether introducing data integrity detection logic detects the input controlled quentity controlled variable exactly complete, just is loaded on the control of pulse-width modulation logical circuit after the input of assurance data is complete and exports.
Shown in Figure 6 is pulse-width modulation logical circuit schematic diagram, and this circuit mainly is made up of 5 parts: controlled quentity controlled variable register, controlled quentity controlled variable buffer, counter buffer and pulse width control circuit.When entire circuit is in running order, write in the controlled quentity controlled variable register through the count value of data management logic with forward drive width P and reverse drive pulse duration N, dead band D register produces D=(T-P-N)/2 by the automatic computing of inside circuit.Whether the real-time detected register input of error detection logic data are correct, whether the input data are complete.If the correct and data integrity of input data, the value that then writes the controlled quentity controlled variable register will be loaded into the controlled quentity controlled variable buffer.Data in the controlled quentity controlled variable buffer are written into counter buffer at the rising edge of the triggering signal that each sign output cycle begins.The value of counter buffer writes the corresponding counts device in the pulse width control logic in next rising edge of clock signal again.The pulse width control logic is the key component of pulse-width modulation output, and its master control logic is accomplished by finite states machine control.Counter is counted respectively P, N, D controlled quentity controlled variable respectively, and every completion is once counted and will be produced a pulse redirect signal StartTurn control state machine and carry out the state redirect.Produce a pulse load signal Load control counter loaded with new data after the state machine redirect simultaneously; Output control logic is according to the state output corresponding modulation waveform of state machine.The state machine transition diagram is as shown in Figure 7, and concrete transfer process is:
At electrification reset or when quitting work, state machine gets into idle waiting Idle state; When the rising edge that detects triggering signal Tstart, if the value of current P counter is not equal to 0, then state machine gets into forward drive PD state, and the effective forward drive motor of output low level signal; If the value of current P counter equals 0, state machine then gets into dead band Dead state, does not export any drive signal; If state machine gets into forward drive PD state, counter is done and is subtracted counting, after accomplishing the needed time counting of forward drive, produces state redirect signal StartTurn, and state machine gets into dead band Dead state thereupon.Under the Dead state of dead band, rolling counters forward Dead Time, counting finish back generation state redirect signal StartTurn.If the value of current N counter is not equal to 0, then state machine gets into reverse drive ND state after detecting state redirect signal StartTurn, output reverse drive motor signal.Otherwise if the value of current N counter equals 0, then state machine gets into idle waiting Idle state after detecting state redirect signal StartTurn, not output drive signal.After state machine got into reverse drive ND state, counter subtracted counting, produced state redirect signal StartTurn after the needed time up to accomplishing the reverse drive motor.State machine gets into idle waiting Idle state after receiving state redirect signal, so circulation.So the mouth in the control input end only need be imported corresponding direct impulse width P as required or/and controlled quentity controlled variables such as reverse impulse width N can realize the automatic output of single bipolar pulse modulation.
Present embodiment H bridge electric machine controller can be realized by digital circuit fully, after accomplishing circuit design and carrying out logic synthesis, can carry out the figure design, carries out flow production at last, thereby forms a single-chip digitial controller.All adopt circuit of single-chip integrated standard design, work flow to realize about the logic synthesis of circuit, automatic layout design, flow manufacturing and packaging and testing, repeat no more at this.
According to the electric machine controller that foregoing is realized, it has following characteristics:
(1) adopt the PWM pulse width modulation mode to realize the control to motor, power-efficient is high, and moment is big;
(2) control signal that the H bridge drives requirement is satisfied in output, can directly control the H bridge and drive running;
(3) the single-chip integrated manipulator is simple in structure, and cost is low, and reliability is high;
(4) have two kinds of modulation of bipolar modulated and one pole modulation control mode, satisfy the dual-use demand of high accuracy and low-power consumption;
(5) have error detection function, further improve reliability;
(6) circuit has the independent controlled output of 5 passages, satisfies multichannel and drives requirement simultaneously.
The foregoing description only is explanation technical conceive of the present invention and characteristics; Its purpose is to let the personage who is familiar with this technology can understand content of the present invention and enforcement according to this; Can not limit protection scope of the present invention with this; All equivalences that spirit is done according to the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (6)
1. support the singly H bridge electric machine controller of bipolar pulse width modulation controlled for one kind, its exportable at least one road PWM waveform signal, it comprises
The interface management logical circuit; It mainly is made up of address decoder and a plurality of register; Described interface management logical circuit is used for receiving from the outside and comprises data message, address information and clock signals such as direct impulse width P, reverse impulse width N, Dead Time D, cycle T, and after decoder for decoding, deposits the data message that receives in relevant register according to address information;
The channel control logic circuit, it mainly is made up of passage gating control register, periodic Control register and frequency divider, and described passage gating control register is used for the output channel gating signal; Said periodic Control register is used for periodic quantity is counted, and cycle count of every completion will be exported a triggering signal; Described frequency divider is used for clock signal is carried out frequency division;
The error detection logic circuit, whether its direct impulse width P, reverse impulse width N, Dead Time D and cycle T that is used to detect input satisfies the relation of P+N+2D=T, if do not satisfy, then output error interrupt signal is forbidden misdata output;
The pulse-width modulation logical circuit; It comprises at least one pulse-width modulation passage; After described error detection logic circuit inerrancy interrupt signal output and channel control logic circuit output channel gating signal and triggering signal, direct impulse width P, reverse impulse width N according to input control the conversion of its internal state machine; To export corresponding PWM waveform signal, be used for drive motors and do corresponding rotation.
2. the H bridge electric machine controller of supporting single bipolar pulse width modulation controlled according to claim 1; It is characterized in that: in the error detection logic circuit, when detecting direct impulse width P, reverse impulse width N, Dead Time D and cycle T relation be: (1) Dead Time D is less than 16 clock width; (2) direct impulse width P and reverse impulse width N sum are more than or equal to the cycle; (3) direct impulse width P greater than cycle T or reverse drive pulse N greater than cycle T; When (4) direct impulse width P and reverse impulse width N sum have in the carry any; Error detection logic circuit output error interrupt signal is to the pulse-width modulation logical circuit; Described pulse-width modulation logical circuit will keep the one-period state normally to export, until input correct P, N, D value.
3. the H bridge electric machine controller of supporting single bipolar pulse width modulation controlled according to claim 2; It is characterized in that: described error detection logic circuit also comprises the relation of direct impulse width P that is exported in each output cycle and reverse impulse width N complete detection the whether; Promptly in an output cycle; Have only after P and all complete input of N, the controlled quentity controlled variable that just allows newly to import is loaded in the pulse-width modulation logical circuit.
4. the H bridge electric machine controller of supporting single bipolar pulse width modulation controlled according to claim 1; It is characterized in that: described pulse-width modulation logical circuit mainly is made up of controlled quentity controlled variable register, controlled quentity controlled variable buffer, counter buffer and pulse width control circuit; The count value of direct impulse width P and reverse impulse width N is written in the corresponding controlled quentity controlled variable register in the interface management logical circuit; After the output of error detection logic circuit inerrancy interrupt signal and channel control logic circuit output channel gating and triggering signal; Data in the controlled quentity controlled variable register are loaded into corresponding controlled quentity controlled variable buffer; Data in the controlled quentity controlled variable buffer are written into counter buffer at the rising edge of the triggering signal that each sign output cycle begins; The value of counter buffer writes the corresponding counts device in the pulse width control circuit in next rising edge of clock signal again; Counter is counted respectively P, N, D controlled quentity controlled variable respectively, and every completion is once counted and will be produced a pulse redirect signal controlling state machine and carry out the state redirect, thus output corresponding modulation waveform.
5. the H bridge electric machine controller of the single bipolar pulse modulation of support according to claim 4 control; It is characterized in that: the process of described state machine state redirect is: at electrification reset or when quitting work; State machine gets into idle waiting Idle state, and when the rising edge of the triggering signal that detects the output of channel control logic circuit, and the value of current counter to the P counting is not equal to 0; State machine gets into forward drive PD state, and the effective forward drive motor of output low level signal; If the value of current counter to P counting equals 0, state machine gets into dead band Dead state, does not export any drive signal; After state machine gets into forward drive state PD state, the counter of P counting done subtract counting, after accomplishing the needed time counting of forward drive, produce state redirect signal, state machine gets into dead band Dead state thereupon; Under the Dead state of dead band, to the rolling counters forward Dead Time of D counting, counting finishes back generation state redirect signal; If the value of current counter to N counting is not equal to 0, state machine gets into reverse drive ND state after detecting state redirect signal, output reverse drive motor signal; If the value of current counter to N counting equals 0, state machine gets into idle waiting Idle state after detecting state redirect signal, not output drive signal; After state machine gets into reverse drive N state D; The counter of N counting done subtract counting; Produce state redirect signal after the needed time up to accomplishing the reverse drive motor; State machine gets into idle waiting Idle after receiving state redirect signal, and so circulation realizes the output of single bipolar pulse modulation signal.
6. support the H bridge electric machine controller of single bipolar pulse modulation control according in the claim 1～5 any, it is characterized in that: described interface management logical circuit, channel control logic circuit, error detection logic circuit, pulse-width modulation logical circuit are integrated on the chip piece.
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| DE102011051548A1 (en) * | 2011-07-04 | 2013-01-10 | Sma Solar Technology Ag | Operating procedure for an inverter and grid-fault-tolerant inverter |
| CN102324891B (en) * | 2011-09-10 | 2013-04-24 | 李嘉文 | Motor speed stabilizing control circuit and digital PWM (Pulse Width Modulation) control circuit |
| CN102510250B (en) * | 2011-10-28 | 2014-04-23 | 中国兵器工业集团第二一四研究所苏州研发中心 | Five-channel PWM (pulse-width modulation) motor control circuit |
| DE102011118044A1 (en) * | 2011-11-09 | 2013-05-16 | Conti Temic Microelectronic Gmbh | Method for controlling a motor by means of pulse width modulation (PWM) |
| CN103501163B (en) * | 2013-10-08 | 2016-08-17 | 洛阳师范学院 | A kind of pwm power amplifier being applied to antenna |
| CN105406844A (en) * | 2015-10-22 | 2016-03-16 | 福州瑞芯微电子股份有限公司 | PWM framework supporting input and output modes |
| CN105634563B (en) * | 2015-12-22 | 2018-03-09 | 武汉瑞纳捷电子技术有限公司 | A kind of LF communication system and method for limiting distance |
| CN107707164B (en) * | 2016-08-08 | 2020-03-17 | 东莞市一能机电技术有限公司 | Stepping driver system and method for controlling PWM time sequence and dead zone |
| CN109769404B (en) * | 2016-08-16 | 2021-02-26 | 东芝三菱电机产业系统株式会社 | System interconnection inverter device and method for operating the same |
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