CN101976652B - Semiconductor packaging structure and manufacture process thereof - Google Patents
Semiconductor packaging structure and manufacture process thereof Download PDFInfo
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- CN101976652B CN101976652B CN 201010277149 CN201010277149A CN101976652B CN 101976652 B CN101976652 B CN 101976652B CN 201010277149 CN201010277149 CN 201010277149 CN 201010277149 A CN201010277149 A CN 201010277149A CN 101976652 B CN101976652 B CN 101976652B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
The invention discloses a semiconductor packaging structure and a manufacture process thereof. The manufacture process of the semiconductor packaging structure comprises the steps of: configuring a packaging mother board on a support tool, wherein the packaging mother board is provided with a grid wall arranged vertically on the packaging mother board and the grid wall defines a plurality of concave parts on the packaging mother board; respectively jointing a plurality of first chips to the concave parts of the packing mother board, wherein each first chip is provided with silicon penetrating guide holes inside; forming first primer between each first chip and the corresponding packaging mother board; forming a cladding layer on the support tool; thinning the cladding layer and the grid wall from the upside of the support tool until the cladding layer above the grid wall and the first chip is completely removed; jointing a plurality of second chips to the first chips; forming second primer between each second chip and the corresponding first chip; separating the support tool from the packaging mother board, and cutting the packaging mother board to obtain a plurality of packaging units.
Description
Technical field
The present invention relates to a kind of semiconductor packaging, and particularly relate to a kind of Gestapelte halbleiterbausteine encapsulation technology.
Background technology
Therefore in information society now, the design of electronic product is to stride forward towards light, thin, short, little trend, develops such as Gestapelte halbleiterbausteine encapsulation etc. to help microminiaturized encapsulation technology.
The Gestapelte halbleiterbausteine encapsulation is to utilize the mode of vertical stacking that a plurality of semiconductor elements are packaged in the same encapsulating structure; So packaging density can be promoted so that the packaging body miniaturization; And the mode that solid capable of using is piled up shortens the path of the signal transmission between the semiconductor element; With signal transmitting speed between the lifting semiconductor element, and can the semiconductor element of difference in functionality be combined in the same packaging body.
Existing a kind of Gestapelte halbleiterbausteine packaging manufacturing process is that interior being embedded with worn silicon guide hole (ThroughSilicon Via; TSV) lower floor's chip chip bonding is on substrate and insert primer protection; Through grinding lower floor's chip thinning and the end that will wear the silicon guide hole are exposed out afterwards, carry out the pile up joint of upper strata chip again lower floor's chip.
Aforementioned manufacture craft causes impaired because of the high low head of substrate surface and lower floor's chip with the abrasive wheel bump for fear of lower floor's chip in process of lapping; Layer of protecting glue can behind lower floor's chip join to substrate, on carrier, be coated with, so that flat surfaces to be provided when grinding comprehensively.An end of waiting to wear the silicon guide hole is by after exposed, again with the remaining protection glue of removal of solvents.Yet this kind mode can produce protection glue and can't be removed fully, and has protection glue residual, causes the problem of substrate, lower floor's chip or packing colloid surface contamination.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor package and manufacture craft thereof, can avoid the existing protection glue of manufacture craft after grinding residual, cause the problem of substrate, lower floor's chip or packing colloid surface contamination.
A purpose more of the present invention is to provide a kind of semiconductor package and manufacture craft thereof; Be applicable to piling up of large-sized upper strata chip and undersized lower floor chip; Can after the levels chip join, insert primer, and can effectively control gel quantity and excessive glue problem.
To achieve these goals, specifically describe content of the present invention, propose a kind of semiconductor packages manufacture craft, comprise the following steps at this.At first, configuration one encapsulation motherboard is on a carrier.The encapsulation motherboard has away from a loading end of carrier and stands on the grid wall (wall matrix) on the loading end.Grid wall and loading end define a plurality of recesses jointly.Then, engage a plurality of first chips respectively, wherein have a plurality of silicon guide holes of wearing in each first chip to the said a plurality of recesses that encapsulate motherboard, and, one first primer formed between each first chip and corresponding encapsulation motherboard.Then, form a coating layer (overcoatlayer) on carrier.Coating layer covers the encapsulation motherboard and first chip.Then, come thinning coating layer and grid wall, removed fully until the coating layer that is positioned at grid wall top and first chip top by the carrier top.Then, expose the end of wearing the silicon guide hole in each first chip, and engage a plurality of second chips to said a plurality of first chips respectively.Then, form one second primer between each second chip and corresponding first chip.Then, separate carrier and encapsulation motherboard, and cut the encapsulation motherboard,, wherein encapsulate motherboard and be cut into a plurality of encapsulation base materials to obtain a plurality of encapsulation units.
In one embodiment of this invention, first primer can be preconfigured in the recess before engaging with the encapsulation motherboard at each first chip, or is received in each first chip after motherboard engages and encapsulates between the motherboard with encapsulating at each first chip.
In one embodiment of this invention; Second primer is before each second chip and corresponding first chip join, to be preconfigured on first chip, or is being received between each second chip and corresponding first chip after each second chip and corresponding first chip join.
In one embodiment of this invention, said semiconductor packages manufacture craft more is included in and exposes after each this end of wearing the silicon guide hole, and each this end of wearing the silicon guide hole is carried out Surface Machining.
In one embodiment of this invention, said semiconductor packages manufacture craft more is included in chip bonding second chip to the first chip, and forms after second primer, forms a packing colloid on the encapsulation motherboard.This packing colloid grating wall and second chip, and when cutting the encapsulation motherboard, cut packing colloid.
The present invention more proposes a kind of semiconductor package, comprises an encapsulation base material, one first chip, one first primer, one second chip and one second primer.The encapsulation base material has a loading end.First chip join is to encapsulating base material.Have a plurality of silicon guide holes of wearing in first chip.A upright side wall that has around first chip on the loading end of encapsulation base material, and the end face of side wall flushes with the end face of first chip in fact each other.First primer is disposed between first chip and the encapsulation base material.Second chip configuration is in first chip top, and be engaged to first chip wear the silicon guide hole.Second primer is disposed between second chip and first chip.
In one embodiment of this invention, side wall defines a recess jointly with the loading end of encapsulation base material, and first primer fills up this recess.
In one embodiment of this invention, the size of second chip is greater than the size of first chip.
In one embodiment of this invention, said semiconductor package more comprises a surface-treated layer, and it is disposed on each end of wearing outstanding first chip of silicon guide hole.
In one embodiment of this invention, said semiconductor package more comprises a plurality of soldered balls, and it is disposed at the bottom of encapsulation base material.
In one embodiment of this invention, said semiconductor package more comprises a packing colloid, and it is disposed on the encapsulation base material, and packing colloid covers the side wall and second chip.
In one embodiment of this invention, the side of the side of the side of packing colloid, side wall and encapsulation base material flushes in fact each other.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended accompanying drawing to elaborate as follows.
Description of drawings
Figure 1A-Fig. 1 K illustrates a kind of semiconductor packages manufacture craft according to one embodiment of the invention in regular turn;
Fig. 2 illustrates a kind of encapsulating structure of another embodiment of the present invention;
Fig. 3 illustrates a kind of encapsulating structure of another embodiment of the present invention;
Fig. 4 illustrates a kind of encapsulating structure of an embodiment more of the present invention.
The main element symbol description
10: carrier
12: adhesion coating
100: encapsulating structure
110: the encapsulation motherboard
110a: loading end
112: the grid wall
112a: the end face of grid wall
114: recess
117: side wall
117a: the side of side wall
119: the encapsulation base material
119a: the side of encapsulation base material
120: the first primers
130: the first chips
130a: the end face of first chip
132: wear the silicon guide hole
132a a: end of wearing the silicon guide hole
134: projection
136: surface-treated layer
140: coating layer
150: protective layer
160: the second primers
170: the second chips
180: packing colloid
180a: the side of packing colloid
188: soldered ball
190: Glue dripping head
200: encapsulating structure
270: the second chips
230: the first chips
300: encapsulating structure
400: encapsulating structure
H1: the thickness of grid wall
H2: the thickness of first chip
H3: the height of first primer
Embodiment
The present invention is provided with the grid wall with adequate thickness on the encapsulation motherboard; Wherein this grid wall can be incorporated in the existing substrate manufacture technology and make; For example; With the welding cover layer thickening on the encapsulation motherboard loading end, forming this grid wall, and the preferable thickness that is controlled in greater than the lower floor's chip after the thinning of the thickness of grid wall.When lower floor's chip is engaged to the encapsulation motherboard, and insert after the primer, on the encapsulation motherboard comprehensively coating one coating layer in order to carrying out follow-up grinding steps.Because the thickness of the thickness of the grid wall lower floor's chip after greater than thinning; Therefore when grinding lower floor chip to the end quilt of wearing the silicon guide hole is exposed; The coating layer that originally was arranged in grid wall top and lower floor chip top is removed at process of lapping fully; Therefore do not have the pollution problem that coating layer is residual and derive, even can save the cleaning step that removes residual coating layer together, thereby can significantly promote manufacture craft yield and efficient.
Figure 1A-Fig. 1 K illustrates a kind of semiconductor packages manufacture craft according to one embodiment of the invention in regular turn.
At first, shown in Figure 1A, configuration one encapsulation motherboard 110 is on a carrier 10.Figure 1A has illustrated the top view and the cutaway view of structure simultaneously.This encapsulation motherboard 110 for example is the substrate of printed circuit board (PCB) or other types.Has adhesion coating 12 on the carrier 10, in order to fixing encapsulation motherboard 110.Encapsulation motherboard 110 has away from a loading end 110a of carrier 10 and stands on the grid wall 112 on the loading end 110a.Grid wall 112 and loading end 110a define a plurality of recesses 114 jointly, and each recess 114 correspondence is carried out the zone of follow-up chip-stacked encapsulation step, to form encapsulation unit respectively.
At this, grid wall 112 for example is to be made up of the welding cover layer on the encapsulation motherboard 110,, with the welding cover layer thickening of encapsulation motherboard 110, has the grid wall 112 of adequate thickness with formation that is.The thickness of the grid wall 112 of this moment shows it with H1 in the drawings.Certainly, the grid wall 112 of present embodiment also can be to be formed on the loading end 110a of encapsulation motherboard 110 through extra manufacture craft.Yet, if adopt encapsulation motherboard 110 original welding cover layers to constitute grid wall 112, need not increase extra manufacturing process steps, promptly can not increase the cost burden of manufacture craft.
Then; Shown in Figure 1B; In each recess 114, form one first primer 120, and shown in Fig. 1 C, engage first chip 130 respectively to each recess 114; Wherein have in each first chip 130 and a plurality ofly wear silicon guide hole 132, and first chip 130 for example is to adopt hot pressing mode to be engaged to encapsulation motherboard 110 through a plurality of projections 134.After motherboard 110 engaged with encapsulation, first primer 120 can fill up first chip 130 and the space that encapsulates between the motherboard 110, and coating projection 134 at first chip 130.
In addition, the order of two steps being illustrated of aforementioned Figure 1B and Fig. 1 C can exchange.Please refer to Figure 1B ' and Fig. 1 C '; Present embodiment also can be selected to engage first chip 130 earlier to each recess 114 (shown in Figure 1B '); Again first primer 120 is filled in the recess 114 (shown in Fig. 1 C '); Make first primer 120 fill up the space between first chip 130 and the encapsulation motherboard 110, and coat projection 134.
In the present embodiment, the size of recess 132 also should keep plastic emitting (the first unnecessary primer 120 that promptly holds first chip, 130 bottoms) or supply a width of glue (dispensing underfill) except must be able to holding first chip 130.In other words, the amount that can estimate first primer 120 that maybe be unnecessary is in advance adjusted the gap of first chip 130 and recess 114 inwalls, or keeps and be enough to let Glue dripping head (the dispensing head) 190 of point gum machine platform the primer material inserted the gap of recess 114.This gap for example is about 1.0 millimeters (mm).
Then, shown in Fig. 1 D, form a coating layer 140 on carrier 10, this coating layer 140 covers encapsulation motherboard 110, grid wall 112 and first chip 130.This coating layer 140 can provide smooth surface, in order to carrying out follow-up grinding manufacture craft.
Then; Shown in Fig. 1 E; Come thinning coating layer 140, grid wall 112 and first chip 130 by carrier 10 tops; Coating layer 140 up to being positioned at grid wall 112 tops and first chip, 130 tops is removed fully, and the end 132a who wears silicon guide hole 132 in first chip 130 is exposed out.At this moment, the end face 112a of grid wall 112 can flush with the end face 130a of first chip 130 in fact each other.End face 130a by first chip 130 after the thinning representes with H2 apart from the height of loading end 110a in the drawings.In the present embodiment; Therefore coating layer 140 in order to ensure grid wall 112 tops and first chip, 130 tops can be removed after this step fully, and the thickness H1 of original formed coating layer 140 of Figure 1A must be greater than by the height H 2 of the end face 130a of first chip 130 after the thinning.
In addition, the amount of first primer 120 inserted at Figure 1B or Fig. 1 C ' of present embodiment is can be controlled.More detailed; If will be in the step shown in Fig. 1 E; The coating layer 140 of first primer, 120 tops is also removed fully, then like Fig. 1 C or Fig. 1 C ' just shown in the height H 3 of first primer 120 need be higher than the height H 2 of the end face 130a of first chip 130 after the thinning.So, after carrying out the step shown in Fig. 1 E, first primer 120 can fill up recess 114.
Then, shown in Fig. 1 F, optionally on coating layer 140, grid wall 112 and first chip 130, cover a protective layer 150 comprehensively.And, shown in Fig. 1 G, each this end 132a that wears silicon guide hole 132 outstanding first chips 130 is carried out Surface Machining (surface finish), to form a surface-treated layer (surface finish layer) 136.
Afterwards, shown in Fig. 1 G, above first chip 130, form one second primer 160, and shown in Fig. 1 H, what engage second chip 170 to each first chip 130 respectively wears silicon guide hole 132.With after first chip 130 engages, second primer 160 can fill up the space between first chip 130 and second chip 170 at second chip 170.
In addition, the order of two steps being illustrated of earlier figures 1G and Fig. 1 H can exchange.Please refer to Fig. 1 G ' and Fig. 1 H '; Present embodiment also can select to engage earlier second chip, 170 to first chips 130 (shown in Fig. 1 G '); Through the Glue dripping head 190 of point gum machine platform the primer material is inserted the space between first chip 130 and second chip 170 again, to form second primer 160.
In the some glue manufacture craft that Fig. 1 H ' is illustrated, because therefore first chip, 130 other grid walls 112 with equal height help carrying out a glue manufacture craft.Particularly; When shown in Fig. 1 H '; The size of second chip 170 is during greater than the size of first chip 130; Being positioned at first chip, 130 peripheral grid walls 112 still can provide complete plane, so the primer material can be inserted between first chip 130 and second chip 170 along the space between the grid wall 112 and second chip 170 smoothly.Compared to existing manufacture craft; The manufacture craft of present embodiment more is applicable to piling up of large-sized upper strata chip (like second chip 170) and undersized lower floor chip (like first chip 130) and some glue manufacture craft, and can effectively control gel quantity and excessive glue problem.
Then, shown in Fig. 1 I, present embodiment can optionally form a packing colloid 180 on encapsulation motherboard 10.This packing colloid 180 grating walls 112 and second chip 170.In other embodiments of the invention, also select not form packing colloid 180.
Then, shown in Fig. 1 J, separate carrier 10 and encapsulation motherboard 110, that is, make the bottom of encapsulation motherboard 110 break away from the adhesion coating 12 on the carrier 10.And, shown in Fig. 1 K, cut encapsulation motherboard 110, to obtain separate a plurality of encapsulation units 100, wherein encapsulate motherboard 110 and be cut into a plurality of encapsulation base materials 119, and grid wall 112 is cut into the side wall 117 around first chip 130.And, form a plurality of soldered balls 188 in the bottom of encapsulation base material 119.In addition; If in abovementioned steps, select to form packing colloid 180; Then when cutting encapsulation motherboard 110, also cut packing colloid 180 simultaneously, make the side 180a of packing colloid 180, the side 117a of side wall 117 and the side 119a of encapsulation base material 119 flush in fact each other.
Can obtain the encapsulating structure (being encapsulation unit) 100 shown in Fig. 1 J via aforementioned manufacture craft, wherein the size of second chip 170 is greater than the size of first chip 130, and covers packing colloid 180 on second chip 170.
Fig. 2 illustrates a kind of encapsulating structure of another embodiment of the present invention.As shown in Figure 2, encapsulating structure 200 is similar with the encapsulating structure 100 of previous embodiment, and both main differences are that the size of second chip 270 of encapsulating structure 200 is less than the size of first chip 230.In addition, encapsulating structure 200 can adopt the manufacturing process steps of previous embodiment to make equally, no longer repeats to give unnecessary details here.
Fig. 3 illustrates a kind of encapsulating structure of another embodiment of the present invention.As shown in Figure 3, encapsulating structure 300 is similar with the encapsulating structure 100 of previous embodiment, and both main differences are that encapsulating structure 300 does not have packing colloid.When the manufacturing process steps that adopts previous embodiment is made the encapsulating structure 300 of present embodiment, omitted the step of the formation packing colloid 180 shown in Fig. 1 I, and formed this encapsulating structure that does not have packing colloid 300.
Fig. 4 illustrates a kind of encapsulating structure of an embodiment more of the present invention.As shown in Figure 4, encapsulating structure 400 is similar with the encapsulating structure 200 of previous embodiment, and both main differences are that encapsulating structure 400 does not have packing colloid.When the manufacturing process steps that adopts previous embodiment is made the encapsulating structure 400 of present embodiment, omitted the step of the formation packing colloid 180 shown in Fig. 1 I, and formed this encapsulating structure that does not have packing colloid 400.
In sum, the present invention forms the grid wall with adequate thickness, and the preferable thickness that is controlled in greater than the lower floor's chip after the thinning of the thickness of grid wall.When grinding lower floor chip to the end quilt of wearing the silicon guide hole is exposed; The coating layer that originally was arranged in grid wall top and lower floor chip top is removed at process of lapping fully; Therefore do not have the pollution problem that coating layer is residual and derive; Even can save the cleaning step that removes residual coating layer together, thereby can significantly promote manufacture craft yield and efficient.In addition, semiconductor packages manufacture craft of the present invention is applicable to piling up of large-sized upper strata chip and undersized lower floor chip, can after the levels chip join, insert primer, and can effectively control gel quantity and excessive glue problem.
Though disclosed the present invention in conjunction with above embodiment; Yet it is not in order to limit the present invention; Be familiar with this operator in the technical field under any; Do not breaking away from the spirit and scope of the present invention, can do a little change and retouching, thus protection scope of the present invention should with enclose claim was defined is as the criterion.
Claims (14)
1. semiconductor packages manufacture craft comprises:
Configuration one encapsulation motherboard is on a carrier, and this encapsulation motherboard has away from a loading end of this carrier and stands on the grid wall on this loading end, and this grid wall and this loading end define a plurality of recesses jointly;
Engage those recesses of a plurality of first chips to this encapsulation motherboard respectively, have a plurality of silicon guide holes of wearing in each first chip;
Form one first primer between each first chip and corresponding this encapsulation motherboard;
Form a coating layer on this carrier, this coating layer covers and should encapsulate motherboard and those first chips;
Come this coating layer of thinning and this grid wall by this carrier top, removed fully until this coating layer that is positioned at this grid wall top and those first chips top;
Expose in each first chip those and wear an end of silicon guide hole;
Engage a plurality of second chips to those first chips;
Form one second primer between each second chip and corresponding this first chip;
Separate this carrier and this encapsulation motherboard; And
Cut this encapsulation motherboard, to obtain a plurality of encapsulation units, wherein this encapsulation motherboard is cut into a plurality of encapsulation base materials.
2. semiconductor packages manufacture craft as claimed in claim 1, wherein this first primer be each first chip be preconfigured in this recess before this encapsulation motherboard engages.
3. semiconductor packages manufacture craft as claimed in claim 1, wherein this first primer be each first chip be received between each first chip and this encapsulation motherboard after this encapsulation motherboard engages.
4. semiconductor packages manufacture craft as claimed in claim 1, wherein this second primer is before each second chip and corresponding this first chip join, to be preconfigured on this first chip.
5. semiconductor packages manufacture craft as claimed in claim 1, wherein this second primer is to be received between each second chip and corresponding this first chip after each second chip and corresponding this first chip join.
6. semiconductor packages manufacture craft as claimed in claim 1 wherein after exposing each this end of wearing the silicon guide hole, also comprises each this end of wearing the silicon guide hole is carried out Surface Machining.
7. semiconductor packages manufacture craft as claimed in claim 1; Wherein at those second chips of chip bonding to those first chips; And form after this second primer, also comprise forming a packing colloid on this encapsulation motherboard, this packing colloid covers this grid wall and those second chips; And when cutting this encapsulation motherboard, cut this packing colloid.
8. semiconductor package comprises:
The encapsulation base material has a loading end;
First chip is engaged to this encapsulation base material, has a plurality of silicon guide holes of wearing in this first chip, and upright on this loading end of this encapsulation base material have the side wall around this first chip, and the end face of this side wall flushes with the end face of this first chip in fact each other;
First primer is disposed between this first chip and this encapsulation base material;
Second chip is disposed at this first chip top, and be engaged to this first chip those wear the silicon guide hole; And
Second primer is disposed between this second chip and this first chip,
Wherein, those wear the end face of outstanding this first chip of silicon guide hole.
9. semiconductor package as claimed in claim 8, wherein this loading end of this side wall and this encapsulation base material defines a recess jointly, and this first primer fills up this recess.
10. semiconductor package as claimed in claim 8, wherein the size of this second chip is greater than the size of this first chip.
11. semiconductor package as claimed in claim 8 also comprises a surface-treated layer, is disposed on each end of wearing outstanding this first chip of silicon guide hole.
12. semiconductor package as claimed in claim 8 also comprises:
A plurality of soldered balls are disposed at the bottom of this encapsulation base material.
13. semiconductor package as claimed in claim 8 also comprises:
Packing colloid is disposed on this encapsulation base material, and this packing colloid covers this side wall and this second chip.
14. semiconductor package as claimed in claim 13, wherein the side of the side of the side of this packing colloid, this side wall and this encapsulation base material flushes in fact each other.
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| CN 201010277149 CN101976652B (en) | 2010-09-07 | 2010-09-07 | Semiconductor packaging structure and manufacture process thereof |
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| CN102637652B (en) * | 2012-04-27 | 2015-04-29 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation, integral semiconductor encapsulation adopting semiconductor encapsulation and manufacture method of semiconductor encapsulation |
| CN104409437B (en) * | 2014-12-04 | 2017-09-22 | 江苏长电科技股份有限公司 | Encapsulating structure rerouted after two-sided BUMP chip packages and preparation method thereof |
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| CN101330076A (en) * | 2007-06-20 | 2008-12-24 | 海力士半导体有限公司 | Through silicon via chip stack package capable of facilitating chip selection during device operation |
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| CN101330076A (en) * | 2007-06-20 | 2008-12-24 | 海力士半导体有限公司 | Through silicon via chip stack package capable of facilitating chip selection during device operation |
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