CN101969266A - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- CN101969266A CN101969266A CN2009101616819A CN200910161681A CN101969266A CN 101969266 A CN101969266 A CN 101969266A CN 2009101616819 A CN2009101616819 A CN 2009101616819A CN 200910161681 A CN200910161681 A CN 200910161681A CN 101969266 A CN101969266 A CN 101969266A
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Abstract
The invention discloses a charge pump circuit. The charge pump circuit is prevented from generating reverse flow by using a rectifier element, which can prevent energy stored in the charge pump circuit from reversely flowing into an input voltage source or energy stored in a capacitor at the output end from reversely flowing to the charge pump circuit and an input voltage source. A current limit unit is connected with an input power supply or/and connected to the output end, the invention can also avoid the problem that the input power supply provides heavy current to the charge pump circuit or/and the charge pump circuit provides heavy current to the output end to cause the overburning of elements of the charge pump circuit when generating short circuit.
Description
Technical field
The present invention relates to a kind of charge pump, relate in particular to and a kind ofly have that adverse current prevents and the charge pump of current limliting.
Background technology
Please refer to Fig. 1, Fig. 1 is the circuit diagram of existing charge pump circuit.This charge pump circuit comprises a full-bridge type commutation circuit, one first capacitor C in, one second capacitor C out, a voltage feedback circuit 30 and a control element 10.The full-bridge type commutation circuit has comprised four transistor switch SW1～SW4, by control signal Con_1, the Con_2 control of control element 10.Control element 10 produces control signal Con_1 when one first sequential, in order to oxide-semiconductor control transistors switch SW 1, SW2 conducting to form one first guiding path.At this moment, the first capacitor C in stores the electric power that an input voltage VDD transmits by first guiding path.Control element 10 produces control signal Con_2 when one second sequential, in order to oxide-semiconductor control transistors switch SW 3, SW4 conducting to form one second guiding path, the first capacitor C in transmits electric power to the second capacitor C out by second guiding path, makes the second capacitor C out can produce an output voltage V out.And first sequential and second sequential are interlaced with each other not overlapping, release energy by transistor switch SW3, SW1 are improper to avoid the second capacitor C out.
In the existing charge pump circuit, transistor switch SW1, SW3 are P type MOS (metal-oxide-semiconductor) transistor, in charge pump circuit starts as yet, input voltage VDD can transmit electric power to the second capacitor C out by the body diode of transistor switch SW1, SW3, make the rough input voltage VDD-2*VD that equals of cross-pressure of the second capacitor C out, wherein VD is the conducting voltage of diode.After charge pump circuit starts, output voltage V out will be higher than input voltage VDD.Therefore, with (0, Vout) transistor switch SW1, SW3 are switched on really and end for the switch level of control signal Con_1, Con_2, also can avoid simultaneously the problem of electric current adverse current, promptly the first capacitor C in energy stored is passed through transistor switch SW1 adverse current to input voltage VDD, and the second capacitor C out energy stored is by transistor switch SW3 adverse current to the first capacitor C in and input voltage VDD.Control element 10 under normal operation, the level of output voltage V out can make transistor switch SW1, SW3 end.So, please refer to Fig. 2 A, when the unusual condition that meets with short circuit etc. when output makes output voltage V out reduce to 0 volt, and make transistor switch SW1, SW3 remain on conducting state always.Therefore input voltage VDD will continue output and export sizable electric current I s to the second capacitor C out by transistor switch SW1, SW3, and transistor switch SW1, SW3 are burnt because of overheated.
In addition, also have with (0, VDD) and (0, Vout) be the circuit design of the switch level of control signal Con_1, Con_2.Refer again to Fig. 1, time schedule controller 14 connects input voltage VDD and output voltage V out, and utilizes a comparison circuit to judge that what person of input voltage VDD and output voltage is a height.At output voltage V out during less than input voltage VDD, with (0, VDD) be the switch level of control signal Con_1, Con_2, and at output voltage V out during greatly at input voltage VDD, with (0, Vout) be the switch level of control signal Con_1, Con_2, can between conducting state and cut-off state, switch really to guarantee transistor switch SW1, SW3.Make output voltage V out reduce to 0 volt suddenly when the output short circuit, after comparison circuit is judged input voltage VDD and is higher than output voltage V out, switched voltage will by (0, Vout) convert to (0, VDD).Yet the switched voltage transfer process postpones if having time, therefore in transfer process, and transistor switch SW1, SW3 conducting simultaneously, shown in Fig. 2 A, electric current I s can cause transistor switch SW1, SW3 overheated and the possibility of burning arranged.In addition, please refer to Fig. 2 B, when short-circuit condition occurs in second sequential, transistor switch SW3, SW4 conducting, the voltage of the first capacitor C in is increased to doubles input voltage VDD, transistor switch SW3 will bear twice input voltage VDD this moment, withstand voltage deficiency not only be arranged and the possibility of damage is arranged, and this moment, electric current I sa was also than the multiplication of the electric current I s shown in Fig. 2 A, and transistor switch SW3 is overheated and risk that burn greatly improves.
Summary of the invention
In view of the problems of the prior art, the present invention prevents charge pump circuit generation adverse current with rectifier cell, not only can avoid the situation of adverse current fully, and control signal can be directly with (0, VDD) be switch level, circuit design is more simple.And, import power supply to adding current limliting unit, the problem that transistor switch burns because of the super-high-current of flowing through in the time of also can avoiding being short-circuited between the output.
For reaching above-mentioned purpose, the invention provides a kind of charge pump circuit, comprise one first capacitor cell, one second capacitor cell, a charge path and a discharge path.Charge path connects this first capacitor cell to an input voltage source when one first sequential, so that this first capacitor cell is charged.Discharge path connects this first capacitor cell to an output when one second sequential, so that this first capacitor cell is discharged, wherein this first sequential and this second sequential stagger each other.Second capacitor cell is in order to store the energy that this first capacitor cell is discharged.Wherein, this discharge path has a current limliting unit, and a discharging current that flow to this second capacitor cell by this first capacitor cell is clamped within the predetermined output current limiting value.
The present invention also provides another kind of charge pump circuit, comprises first capacitor cell, one second capacitor cell, a charge path and a discharge path.Charge path connects this first capacitor cell to an input voltage source when one first sequential, so that this first capacitor cell is charged.Discharge path connects this first capacitor cell to an output when one second sequential, so that this first capacitor cell is discharged, wherein this first sequential and this second sequential stagger each other.Second capacitor cell is in order to store the energy that this first capacitor cell is discharged.Wherein, this discharge path has a rectification unit, releases energy to this first capacitor cell in order to prevent this second capacitor cell.
Above general introduction and ensuing detailed description are all exemplary in nature, are in order to further specify claim of the present invention.And relevant other objects and advantages of the present invention will be set forth in follow-up explanation and diagram.
Description of drawings
Fig. 1 is the circuit diagram of existing charge pump circuit.
Fig. 2 A is existing charge pump circuit current direction schematic diagram when short circuit.
Fig. 2 B is the existing charge pump circuit at short circuit current direction schematic diagram during the initial stage.
Fig. 3 is the schematic diagram of the charge pump circuit of one first preferred embodiment of the present invention.
Fig. 4 is the schematic diagram of the charge pump circuit of one second preferred embodiment of the present invention.
Fig. 5 is the schematic diagram of the charge pump circuit of one the 3rd preferred embodiment of the present invention.
The main element symbol description:
Control signal Con_1, Con_2 input voltage VDD
Output voltage V out voltage feedback signal VFB
Reference voltage V1 detection signal DET
The clock signal clk first capacitor C in
The second capacitor C out electric current I s, Isa
Control unit 100,200,300 oscillators 112,212,312
Time schedule controller 114,214,314 hysteresis comparators 116,216,316
Inverter 118,318 voltage feedback circuits 130,230,330
Protector 220,320 is crossed low pressure comparator 222,322
Excess temperature detector 224,324 output current limiting elements 235
Voltage divider 332 input current limiting elements 335
The first capacitor cell Ci, the second capacitor cell Co
The one P type MOS (metal-oxide-semiconductor) transistor PM1 the 2nd N type MOS (metal-oxide-semiconductor) transistor NM2
The 2nd P type MOS (metal-oxide-semiconductor) transistor PM2 the 3rd N type MOS (metal-oxide-semiconductor) transistor NM3
The 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 the 4th P type MOS (metal-oxide-semiconductor) transistor PM4
The 5th P type MOS (metal-oxide-semiconductor) transistor PM5 the 6th P type MOS (metal-oxide-semiconductor) transistor PM6
The 7th P type MOS (metal-oxide-semiconductor) transistor PM7 input voltage VDD
Output voltage V out input rectifying element D1
Output rectifier cell D2 reference voltage V1
Cross low-voltage variation voltage V2, V3 detection signal DET
Clock signal clk control signal S1, S1 ', S2
The first gold medal oxygen, half diode MD1, the second gold medal oxygen, half diode MD2
Cross low-voltage variation signal UVP overheat protector signal OTP
The guard signal PROT first input capacitance Ci1
The second input capacitance Ci2, the first two-carrier transistors diodes BD1
The second two-carrier transistors diodes BD2
Embodiment
Please refer to Fig. 3, Fig. 3 is the schematic diagram of the charge pump circuit of one first preferred embodiment of the present invention.Charge pump circuit comprises a control unit 100, one first capacitor cell Ci, one second capacitor cell Co, a charge path and a discharge path.Charge path comprises one the one P type MOS (metal-oxide-semiconductor) transistor PM1, one the 2nd N type MOS (metal-oxide-semiconductor) transistor NM2 and an input rectifying element D1.The one P type MOS (metal-oxide-semiconductor) transistor PM1 connects one first end of an input voltage VDD and the first capacitor cell Ci, and the negative terminal of parasitic diode connects input voltage VDD, anode connection output voltage V out.The 2nd N type MOS (metal-oxide-semiconductor) transistor NM2 connects one second end and the ground connection of the first capacitor cell Ci, and the negative terminal of parasitic diode connects input voltage VDD, anode connection ground.Input rectifying element D1 can have the element of rectification function for a diode or other, be connected between first end of the input voltage VDD and the first capacitor cell Ci, in order to prevent the generation of reverse current, the first capacitor cell Ci is unlikely releases energy to input voltage VDD.In the present embodiment, input rectifying element D1 is a diode, and its anode connects input voltage VDD and negative terminal connection output voltage V out.Discharge path comprises one the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3, one the 4th P type MOS (metal-oxide-semiconductor) transistor PM4 and an output rectifier cell D2.The 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 connects first end of an output voltage V out and the first capacitor cell Ci, and the negative terminal of parasitic diode connects input voltage VDD, anode connection output voltage V out.The 4th P type MOS (metal-oxide-semiconductor) transistor PM4 connects second end of an input voltage VDD and the first capacitor cell Ci, and the negative terminal of parasitic diode connects input voltage VDD, anode connection ground.Output rectifier cell D2 can have the element of rectification function for a diode or other, be connected between first end of the output voltage V out and the first capacitor cell Ci, in order to prevent the generation of reverse current, the second capacitor cell Co is unlikely releases energy to the first capacitor cell Ci and input voltage VDD.In the present embodiment, output rectifier cell D2 also is a diode, and its anode connects input voltage VDD and negative terminal connection output voltage V out.In addition, application scenario in the lower load of electricity needs, the second capacitor cell Co can use the grid equivalent input capacitance of MOS (metal-oxide-semiconductor) transistor (to be first end of the grid of MOS (metal-oxide-semiconductor) transistor as equivalent input capacitance, and drain, source electrode and substrate connect second end into equivalent input capacitance altogether), so can will build in the second capacitor cell Co in the wafer and reduce circuit cost.
It should be noted that in the present embodiment, the control signal S1 that is exported, the S2 of control unit 100, the switch level of S2 ' for (O, VDD).Under normal operation, a P type MOS (metal-oxide-semiconductor) transistor PM1 and the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 keep conducting, prevent that the function of adverse current from then being carried out by input rectifying element D1 and output rectifier cell D2 respectively.And when circuit abnormality caused output voltage V out to be lower than input voltage VDD, a P type MOS (metal-oxide-semiconductor) transistor PM1 and the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 can be cut off really.In addition; because the body diode conducting direction of a P type MOS (metal-oxide-semiconductor) transistor PM1 and the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 is with opposite by input rectifying element D1 and output rectifier cell D2 conducting direction; therefore when a P type MOS (metal-oxide-semiconductor) transistor PM1 and the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 are cut off during at circuit abnormality; input voltage VDD can't export energy to output voltage V out, so can reach the advantage of protective circuit.Moreover, for avoiding at circuit output end at the beginning of short circuit, the first capacitor cell Ci makes the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3, output rectifier cell D2 burn because of overheated by the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3, output rectifier cell D2 output super-high-current to output, the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 can use the P type MOS (metal-oxide-semiconductor) transistor with big conducting resistance, with the size of current that limits first capacitor cell Ci output within a predetermined safe current value.
Next please refer to Fig. 4, Fig. 4 is the schematic diagram of the charge pump circuit of one second preferred embodiment of the present invention.Charge pump circuit comprises a control unit 200, one first capacitor cell Ci, one second capacitor cell Co, a charge path, a discharge path and an output current limiting element 235.Compare with embodiment illustrated in fig. 3, in the charge path of present embodiment, omit a P type MOS (metal-oxide-semiconductor) transistor PM1 and replace input rectifying element D1 with the first gold medal oxygen, half diode MD1 (alleged in the present invention golden oxygen half diode is that finger grid, substrate are connected with drain electrode and show the MOS (metal-oxide-semiconductor) transistor of diode characteristic); In the discharge path of present embodiment, replace output rectifier cell D2 with the second gold medal oxygen, half diode MD2.In addition, increasing output current limiting element 235 burns it to avoid excessive electric current to flow through the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3.Output current limiting element 235 can be a resistance, because the first capacitor cell Ci is when charge pump circuit is operated, ceiling voltage is the input voltage VDD of twice, so can set suitable resistance value according to R=2*VDD/Ilo, wherein Ilo is the predetermined cut-off current of importing.
In the present embodiment, though omitted a P type MOS (metal-oxide-semiconductor) transistor PM1, do not influence the function of charge pump circuit.Under normal operation, the first gold medal oxygen, half diode MD1 still can reach the effect that prevents adverse current, and under circuit abnormality, the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 ends, the body diode of the 3rd P type MOS (metal-oxide-semiconductor) transistor PM3 is opposite with the conducting direction of the second gold medal oxygen, half diode MD2, can prevent that still input voltage VDD from transmitting the problem of energy to output voltage.
In addition, except that the circuit structure of the charge pump circuit of two above-mentioned embodiment, the present invention also can be applied to the charge pump circuit of other different circuit structures.Please refer to Fig. 5, Fig. 5 is the schematic diagram of the charge pump circuit of one the 3rd preferred embodiment of the present invention.In the present embodiment, charge pump circuit comprises a control unit 300, one first capacitor cell, one second capacitor cell Co, a charge path, a discharge path and an input current limiting element 335, and wherein first capacitor cell comprises one first input capacitance Ci1 and one second input capacitance Ci2.Input current limiting element 335 is connected between an input voltage VDD and first capacitor cell, is scheduled within the input cut-off current one by the input current of input voltage VDD to the first capacitor cell in order to strangulation.Input current limiting element 335 can be a resistance, and its suitable resistance value can be set wherein Ii according to R=2*VDD/Ii and be predetermined input cut-off current.
Charge path comprises one the one P type MOS (metal-oxide-semiconductor) transistor PM1, one the 2nd P type MOS (metal-oxide-semiconductor) transistor PM2, one the 3rd N type MOS (metal-oxide-semiconductor) transistor NM3 and one first two-carrier transistors diodes BD1 (alleged in the present invention two-carrier transistors diodes is meant that base stage is connected with collector electrode and shows the two-carrier transistor of diode characteristic).The one P type MOS (metal-oxide-semiconductor) transistor PM1 connects one first end of an input voltage VDD and the first input capacitance Ci1, and the negative terminal of parasitic diode connects input voltage VDD, anode connection output voltage V out.The 2nd P type MOS (metal-oxide-semiconductor) transistor PM2 connects one second end of the first input capacitance Ci1 and one first end of the second input capacitance Ci2, and the negative terminal of parasitic diode connects input voltage VDD, anode connection output voltage V out.The 3rd N type MOS (metal-oxide-semiconductor) transistor NM3 connects one second end and the ground connection of the second input capacitance Ci2, and the negative terminal of parasitic diode connects input voltage VDD, anode connection ground.When first sequential, a P type MOS (metal-oxide-semiconductor) transistor PM1, the 2nd P type MOS (metal-oxide-semiconductor) transistor PM2 and the 3rd N type MOS (metal-oxide-semiconductor) transistor NM3 conducting and other times are for ending.Therefore when first sequential, input voltage VDD makes the first input capacitance Ci1 and the second input capacitance Ci2 input voltage VDD that stores 0.5 times out of the ordinary to the first input capacitance Ci1 and the second input capacitance Ci2 charging of series connection.The first two-carrier transistors diodes BD1 is connected between first end of the input voltage VDD and the first input capacitance Ci1, in order to prevent the generation of reverse current, first capacitor cell is unlikely releases energy to input voltage VDD.
Discharge path comprises one the 4th P type MOS (metal-oxide-semiconductor) transistor PM4, one the 5th P type MOS (metal-oxide-semiconductor) transistor PM5, one the 6th P type MOS (metal-oxide-semiconductor) transistor PM6, one the 7th P type MOS (metal-oxide-semiconductor) transistor PM7 and one second two-carrier transistors diodes BD2.The 4th P type MOS (metal-oxide-semiconductor) transistor PM4 connects second end of the input voltage VDD and the first input capacitance Ci1, and the negative terminal of parasitic diode connects input voltage VDD, anode connection ground.The 5th P type MOS (metal-oxide-semiconductor) transistor PM5 connects first end of the first input capacitance Ci1 and first end of the second input capacitance Ci2, and the negative terminal of parasitic diode connects input voltage VDD, anode connection output voltage V out.The 6th P type MOS (metal-oxide-semiconductor) transistor PM6 connects second end of the first input capacitance Ci1 and second end of the second input capacitance Ci2, and the negative terminal of parasitic diode connects input voltage VDD, anode connection ground.The 7th P type MOS (metal-oxide-semiconductor) transistor PM7 connects first end of the second input capacitance Ci2 and the end of the second capacitor cell Co, and the negative terminal of parasitic diode connects input voltage VDD, anode connection output voltage V out.When second sequential, the 4th P type MOS (metal-oxide-semiconductor) transistor PM4, the 5th P type MOS (metal-oxide-semiconductor) transistor PM5, the 6th P type MOS (metal-oxide-semiconductor) transistor PM6 and the 7th P type MOS (metal-oxide-semiconductor) transistor PM7 conducting, and all the other times end.Therefore when second sequential, the first input capacitance Ci1 and the second input capacitance Ci2 transfer in parallel and are connected to input voltage VDD simultaneously, with 1.5 times of input voltage VDD discharges, the energy of release is stored on the second capacitor cell Co by the 7th P type MOS (metal-oxide-semiconductor) transistor PM7 and the second two-carrier transistors diodes BD2.The second two-carrier transistors diodes BD2 connects between the second capacitor cell Co and first capacitor cell, in order to prevent the generation of reverse current, makes that second capacitor cell is unlikely gets back to first capacitor cell releasing energy again.
Control unit 300 comprises an oscillator 312, time schedule controller 314, a hysteresis comparator 316, an inverter 318, a protector 320, a mistake low pressure comparator 322 and an excess temperature detector 324.Compare with embodiment shown in Figure 4, whether the mistake low pressure comparator 322 of present embodiment is by a voltage divider 332 dividing potential drop input voltage VDD, low excessively to judge input voltage VDD.When input voltage VDD crosses when low, promptly input voltage VDD is lower than one when crossing low-voltage variation voltage V2 through the voltage division signal of voltage divider 332 dividing potential drops, produces one and crosses low-voltage variation signal UVP, makes controller 300 enter protected mode.Because all the other operations of control unit 300 are similar to control unit 200 shown in Figure 4, so be not repeated at this.
The explanation of embodiment as described above, the present invention utilizes rectifier cell to prevent charge pump circuit generation adverse current, can avoid the stored energy adverse current of charge pump circuit to be fed back into the stored energy adverse current telegram in reply lotus pump circuit and the input voltage source of electric capacity of voltage source or output.Therefore, not only can avoid charge pump circuit generation adverse current fully, and control signal can be directly with (0, VDD) be switch level, circuit design is more simple.And, the present invention also utilizes the current limliting unit to connect the input power supply or/and be connected to output, in the time of also can avoiding being short-circuited, the input power supply provide super-high-current to charge pump circuit or/and the problem that the element that charge pump circuit provides super-high-current to make charge pump circuit to output burns.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (14)
1. charge pump circuit comprises:
One first capacitor cell;
One charge path connects this first capacitor cell to an input voltage source when one first sequential, so that this first capacitor cell is charged;
One discharge path connects this first capacitor cell to an output when one second sequential, so that this first capacitor cell is discharged, wherein this first sequential and this second sequential stagger each other; And
One second capacitor cell is in order to store the energy that this first capacitor cell is discharged;
Wherein, this discharge path has a current limliting unit, and a discharging current that flow to this second capacitor cell by this first capacitor cell is clamped within the predetermined output current limiting value.
2. charge pump circuit according to claim 1, wherein this current limliting unit is that a P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) connects this first capacitor cell and this second capacitor cell, this P type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) when conducting this discharging current of strangulation within this predetermined output current limiting value.
3. charge pump circuit according to claim 1, wherein this current limliting unit comprises an output current limiting element, in order to this discharging current of strangulation within this predetermined output current limiting value.
4. according to claim 2 or 3 described charge pump circuits, wherein this discharge path also comprises an output rectifier cell, releases energy to this first capacitor cell in order to prevent this second capacitor cell.
5. according to claim 2 or the 3rd described charge pump circuit, also comprise an input current limiting element, be scheduled within the input cut-off current one from the electric current of this input voltage source in order to strangulation.
6. charge pump circuit according to claim 1, wherein this charge path comprises an input rectifying element, releases energy to this input voltage source in order to prevent this first capacitor cell.
7. charge pump circuit according to claim 1, also comprise a control unit, in order to produce a plurality of control signals control this charge path at this first sequential conducting and this discharge path in this second sequential conducting, the level of wherein said a plurality of control signals is between the voltage level and a common level of this input voltage source.
8. charge pump circuit according to claim 7, wherein this control unit comprises a protector, produces a guard signal when the charge pump circuit abnormality, makes control unit end this charge path and this discharge path.
9. charge pump circuit comprises:
One first capacitor cell;
One charge path connects this first capacitor cell to an input voltage source when one first sequential, so that this first capacitor cell is charged;
One discharge path connects this first capacitor cell to an output when one second sequential, so that this first capacitor cell is discharged, wherein this first sequential and this second sequential stagger each other; And
One second capacitor cell is in order to store the energy that this first capacitor cell is discharged;
Wherein, this discharge path has a rectification unit, releases energy to this first capacitor cell in order to prevent this second capacitor cell.
10. charge pump circuit according to claim 9, also comprise an output current limiting unit and connect this first capacitor cell and this second capacitor cell, make by this first capacitor cell and flow to a discharging current strangulation of this second capacitor cell within a predetermined output current limiting value.
11. charge pump circuit according to claim 9, wherein this charge path comprises an input rectifying element, releases energy to this input voltage source in order to prevent this first capacitor cell.
12. charge pump circuit according to claim 11, also comprise a control unit, in order to produce a plurality of control signals control this charge path at this first sequential conducting and this discharge path in this second sequential conducting, the level of wherein said a plurality of control signals is between the voltage level and a common level of this input voltage source.
13. charge pump circuit according to claim 11 also comprises an input current limliting unit and connects this input voltage source, makes from the electric current strangulation of this input voltage source and is scheduled within the input cut-off current one.
14. charge pump circuit according to claim 12, wherein this control unit comprises a protector, produces a guard signal when the charge pump circuit abnormality, makes control unit end this charge path and this discharge path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101616819A CN101969266A (en) | 2009-07-28 | 2009-07-28 | Charge pump circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101616819A CN101969266A (en) | 2009-07-28 | 2009-07-28 | Charge pump circuit |
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| Publication Number | Publication Date |
|---|---|
| CN101969266A true CN101969266A (en) | 2011-02-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101616819A Pending CN101969266A (en) | 2009-07-28 | 2009-07-28 | Charge pump circuit |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103249213A (en) * | 2012-02-13 | 2013-08-14 | 东芝照明技术株式会社 | Power supply for illumination and luminaire |
| CN107046364A (en) * | 2016-02-05 | 2017-08-15 | 奕力科技股份有限公司 | Charge pump |
| CN109150144A (en) * | 2013-01-08 | 2019-01-04 | 联咏科技股份有限公司 | data control circuit |
| CN110794328A (en) * | 2019-10-30 | 2020-02-14 | 汉中一零一航空电子设备有限公司 | Detection circuit and detection method for detecting overload or short-circuit fault |
| CN118137814A (en) * | 2024-04-03 | 2024-06-04 | 杭州芯迈半导体技术有限公司 | Overcurrent protection circuit of charge pump and control method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7276960B2 (en) * | 2005-07-18 | 2007-10-02 | Dialog Semiconductor Gmbh | Voltage regulated charge pump with regulated charge current into the flying capacitor |
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2009
- 2009-07-28 CN CN2009101616819A patent/CN101969266A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7276960B2 (en) * | 2005-07-18 | 2007-10-02 | Dialog Semiconductor Gmbh | Voltage regulated charge pump with regulated charge current into the flying capacitor |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103249213A (en) * | 2012-02-13 | 2013-08-14 | 东芝照明技术株式会社 | Power supply for illumination and luminaire |
| US8941318B2 (en) | 2012-02-13 | 2015-01-27 | Toshiba Lighting & Technology Corporation | Power supply for illumination and luminaire |
| CN103249213B (en) * | 2012-02-13 | 2015-03-25 | 东芝照明技术株式会社 | Luminaire |
| CN109150144A (en) * | 2013-01-08 | 2019-01-04 | 联咏科技股份有限公司 | data control circuit |
| CN107046364A (en) * | 2016-02-05 | 2017-08-15 | 奕力科技股份有限公司 | Charge pump |
| CN110794328A (en) * | 2019-10-30 | 2020-02-14 | 汉中一零一航空电子设备有限公司 | Detection circuit and detection method for detecting overload or short-circuit fault |
| CN118137814A (en) * | 2024-04-03 | 2024-06-04 | 杭州芯迈半导体技术有限公司 | Overcurrent protection circuit of charge pump and control method thereof |
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Application publication date: 20110209 |