CN101964359B

CN101964359B - Bipolar transistor, forming method thereof and virtual ground circuit

Info

Publication number: CN101964359B
Application number: CN 200910055408
Authority: CN
Inventors: 季明华; 秦立瑛; 肖德元
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Beijing Corp
Priority date: 2009-07-24
Filing date: 2009-07-24
Publication date: 2013-06-19
Anticipated expiration: 2029-07-24
Also published as: CN101964359A

Abstract

The invention provides a bipolar transistor, a forming method thereof, a virtual ground circuit containing the bipolar transistor and a double-band-gap reference circuit. The bipolar transistor comprises silicon-on-insulator, base areas, emitting areas and collector areas; base area gate dielectric layers are positioned on top silicon, corresponding to the base areas; polysilicon layers are positioned on the base area gate dielectric layers; emitting electrodes are electrically connected with the emitting areas by first contact holes; collector electrodes are electrically connected with the collector areas by second contact holes; base area control electrodes are electrically connected with the polysilicon layers by third contact holes; and the conductivity types of the polysilicon layers are the same as the conductivity types of the base areas and opposite to the conductivity types of the emitting areas and the collector areas. The invention has the following advantages: the process forming the bipolar transistor is completely compatible with the traditional standard CMOS process; and the junction capacitance in the emitting areas/collector areas of the bipolar transistor is low, the base area current is formed by applying voltage on the base area control electrodes, extra base area contact hole process is not needed and the bipolar transistor has lower input capacitance.

Description

Bipolar transistor and forming method thereof, virtual ground circuit

Technical field

The present invention relates to technical field of semiconductors, particularly a kind of formation method of bipolar transistor, bipolar transistor and the method for driving bipolar transistor and virtual ground circuit and the two times of silicon bandgap voltage circuit that comprise bipolar transistor.

Background technology

Bipolar transistor has two kinds of basic structures: positive-negative-positive and NPN type are comprised of two back-to-back PN junctions.In this three-layer semiconductor, middle one deck is base (b), two-layer emitter region (e) and the collector region (c) of crying respectively in left and right.Form emitter junction between emitter region and base, form collector junction between collector region and base.

The structure of bipolar transistor and the research of manufacture method are long-standing, and the structure of common bipolar transistor and manufacture method can be with reference to No. 91104429.9 disclosed contents of Chinese patent application.

Prior art also discloses a kind of npn type bipolar transistor structure of utilizing existing nMOS transistor junction to be configured to, specifically please refer to shown in Figure 1ly, comprises p-type Semiconductor substrate 100; Be arranged in the dark N-shaped dopant well 101 (DNW) of Semiconductor substrate 100; Be arranged in the p-type dopant well 102 (PW) of Semiconductor substrate 100, described p-type dopant well 102 is surrounded by dark N-shaped dopant well 101; Be arranged in the n+ doped region of Semiconductor substrate 100, described n+ doped region is used to form nMOS transistorized source/drain electrode.Described dark N-shaped dopant well 101, p-type dopant well 102 and n+ doped region consist of npn bipolar transistor.Certainly, existing nMOS transistor arrangement also comprises gate dielectric layer 103 and polysilicon gate 104.

Equally, utilize the pMOS structure can also form the positive-negative-positive bipolar transistor.

In above-mentioned npn type bipolar transistor structure, dark N-shaped dopant well 101 consists of the emitter of bipolar transistor, the base stage that p-type dopant well 102 consists of bipolar transistor, the collector electrode that the n+ doped region consists of bipolar transistor, when in use, need to form electrode by contact hole respectively on emitter, base stage, collector electrode, then apply current source to use on base stage.

Simultaneously, in a large amount of integrated circuits, in digital to analog converter (DAC), analog to digital converter (ADC), linear voltage regulator and switching regulator, all need accurate and stable voltage reference source circuit.Reference voltage source directly affects performance and the precision of electronic system, so reference voltage source floats for temperature and the index request relevant with precision is higher.(Virtual ground referencecircuit) can realize high PSRR and low-temperature coefficient due to virtual ground circuit, is the reference source circuit of present various reference voltage source performance the bests.

In order to realize high accuracy, usually all use the intrinsic character voltage of silicon semiconductor material itself (silicon bandgap voltage) as reference voltage, but because silicon semiconductor material has certain temperature coefficient, institute thinks that solving temperature floats problem, usually selects a kind of temperature coefficient polarity with reference voltage opposite but device that absolute value is close or circuit (as Δ V _BECircuit), both are combined, temperature-compensating mutually makes the bulk temperature coefficient be approximately zero.

Summary of the invention

The problem that the present invention solves is to provide a kind of formation method of bipolar transistor, bipolar transistor and drives the method for bipolar transistor and virtual ground circuit and the two times of silicon bandgap voltage circuit that comprise bipolar transistor.

For addressing the above problem, the invention provides a kind of bipolar transistor, comprising: silicon-on-insulator, described silicon-on-insulator comprise silicon base, are positioned at oxygen buried layer and top layer silicon on silicon base successively; Base, emitter region and collector region are positioned at top layer silicon, and described base is between emitter region and collector region, and the conduction type of described emitter region and collector region is identical, and described base conduction type is opposite with emitter region and collector region; The base gate dielectric layer is positioned on top layer silicon corresponding to the position, base; Polysilicon layer is positioned on the base gate dielectric layer; Emitter is connected with emitter region electricity by the first contact hole; Collector electrode is connected with collector region electricity by the second contact hole; The base control electrode is connected with polysilicon layer electricity by the 3rd contact hole, and the conduction type of described polysilicon layer is identical with the base, and is opposite with emitter region and collector region.Also comprise: also comprise buffering area between described collector region and base, the doping type of described buffering area is identical with collector region, but doping content is less than collector region, and the interface of the interface between described buffering area and collector region and described emitter region and base favours described semiconductor substrate surface.

A kind of method of making bipolar transistor as above comprises: silicon-on-insulator is provided, and described silicon-on-insulator comprises silicon base, is positioned at oxygen buried layer and top layer silicon on silicon base successively; Be formed with the source region on top layer silicon; Carrying out first in active area injects; Define the zone, base in active area, zone, corresponding base forms base gate dielectric layer and polysilicon layer successively on top layer silicon; Carry out the 4th injection in polysilicon layer, described the 4th injection makes the polysilicon layer conduction type identical with the base; Carry out second and inject in the active area beyond the base, the conductivity type opposite of the conduction type of the described second ion that injects and the first ion that injects forms emitter region and collector region; Form the first interlayer dielectric layer on top layer silicon, cover described base gate dielectric layer and polysilicon layer; Form the first contact hole, the second contact hole and the 3rd contact hole in the first interlayer dielectric layer; Form conductive layer on the first interlayer dielectric layer, adopt conductive layer to form collector electrode, emitter and base control electrode, described emitter is connected with emitter region electricity by the first contact hole, described emitter is connected with collector region electricity by the second contact hole, and described base control electrode is connected with polysilicon layer electricity by the 3rd contact hole.

Also be included in and carry out the first additional injection in the zone, base, the conduction type of the described first additional ion that injects is identical with the conduction type of the first ion that injects.

Carry out second inject after, also carry out the 3rd injection in the active area beyond the base before forming the first interlayer dielectric layer, described the 3rd ion conduction type is identical with the second ionic conduction type of injecting, form the described base of connection and collector region buffering area, the described the 3rd direction of injecting favours described semiconductor substrate surface.

A kind of method that drives above-mentioned bipolar transistor comprises: apply the first voltage on the base control electrode; Apply second voltage on collector electrode; Apply tertiary voltage on emitter; Effect sub-collector top layer formation minority carrier at the formed electric field of above-mentioned voltage, described minority carrier is identical with the majority carrier type of base, and inflow base, form grid and cause leakage current, the charge carrier that the formation grid cause leakage current continues to flow to the emitter region, makes the PN junction forward conduction between base and emitter.

Described base conduction type is p-type, and collector region and emitter region conduction type are N-shaped, and the second voltage on the first voltage ratio collector electrode on described base control electrode is low, and the tertiary voltage on described emitter is lower than the first voltage.

Described base conduction type is N-shaped, and collector region and emitter region conduction type are p-type, on described base control electrode on the first voltage ratio collector electrode second voltage high, the tertiary voltage on described emitter is higher than second voltage.

A kind of virtual ground circuit with above-mentioned bipolar transistor comprises: first end and the second end have the first voltage difference between described first end and the second end; The first current source, an end is electrically connected to first end; The first bipolar transistor, emitter are electrically connected to the other end of the first current source; The first load, an end is electrically connected to the collector electrode of the first bipolar transistor, and the other end is electrically connected to the second end; The 3rd end and the 4th end have a second voltage poor between described the 3rd end and the 4th end; The second current source, an end is electrically connected to the 3rd end; The second bipolar transistor, emitter are electrically connected to the other end of the second current source; The second load, an end is electrically connected to the collector electrode of the second bipolar transistor, and the other end is electrically connected to the 4th end; The base control electrode of described the first bipolar transistor and the base control electrode of the second bipolar transistor are electrically connected, and as the output of described virtual ground circuit, described the first bipolar transistor and the second bipolar transistor are positive-negative-positive; Control unit, have first input end, the second input and output, first input end is electrically connected to the emitter of the first bipolar transistor, and the second input is electrically connected to the emitter of the second bipolar transistor, and output is electrically connected to the output of described virtual ground circuit; The collector current that described control unit makes the collector current of the emitter current of the first bipolar transistor and the first bipolar transistor be electric current, the emitter current that makes the second bipolar transistor and second bipolar transistor of the first current source output is the electric current that the second current source is exported; It is zero and to make the output voltage of described virtual ground circuit be zero that the value of the output current by selecting the first current source, the output current of the second current source and the first load and the second load makes the temperature drift coefficient of output voltage of the output of described virtual ground circuit.

Described the first bipolar transistor is identical with the second bipolar transistor structure; Described the first voltage difference and second voltage are poor identical; Described the first load is the first resistance and the second resistance, and described the second load is the second resistance.

Described first end and the external voltage source of the 3rd termination; Described the second end and the 4th end ground connection.

Doping content with polysilicon layer the second bipolar transistor described the first bipolar transistor is identical.

A kind of two times of silicon bandgap voltage circuit with above-mentioned bipolar transistor comprise: first end and the second end have the first voltage difference between described first end and the second end; The first current source, an end is electrically connected to first end; The first bipolar transistor, emitter are electrically connected to the other end of the first current source; The first load, an end is electrically connected to the collector electrode of the first bipolar transistor, and the other end is electrically connected to the second end; The 3rd end and the 4th end have a second voltage poor between described the 3rd end and the 4th end; The second current source, an end is electrically connected to the 3rd end; The second bipolar transistor, emitter are electrically connected to the other end of the second current source; The second load, an end is electrically connected to the collector electrode of the second bipolar transistor, and the other end is electrically connected to the 4th end; The base control electrode of described the first bipolar transistor and the base control electrode of the second bipolar transistor are electrically connected, and as the output of described two times of silicon bandgap voltage circuit, described the first bipolar transistor and the second bipolar transistor are the NPN type; Control unit, have first input end, the second input and output, first input end is electrically connected to the emitter of the first bipolar transistor, and the second input is electrically connected to the emitter of the second bipolar transistor, and output is electrically connected to the output of described two times of silicon bandgap voltage circuit; The collector current that described control unit makes the collector current of the emitter current of the first bipolar transistor and the first bipolar transistor be electric current, the emitter current that makes the second bipolar transistor and second bipolar transistor of the first current source output is the electric current that the second current source is exported; It is zero and to make the output voltage of the output of described two times of silicon bandgap voltage circuit be two times of silicon band gap that the value of the output current by selecting the first current source, the output current of the second current source and the first load and the second load makes the temperature drift coefficient of output voltage of the output of described two times of silicon bandgap voltage circuit.

Described first end and the 3rd end ground connection; Described the second end and the external voltage source of the 4th termination.Doping content with polysilicon layer the second bipolar transistor described the first bipolar transistor is identical.

Compared with prior art, the technical program has the following advantages: can indirectly apply voltage to the base by form the base control electrode on the base gate electrode, be similar to the gate electrode of traditional MOS transistor, need not the base electrode of directly making of the prior art so that the base is applied electric current on the base, the bipolar transistor structure that forms like this is substantially identical with traditional mos transistor structure, and the technique of this bipolar transistor of formation and traditional standard CMOS process are fully compatible; And the emitter region of bipolar transistor/collector region junction capacitance is less, forms the base electric current by apply voltage on the base control electrode, need not extra base contact hole technique, has less input capacitance.

The technical program is by forming doping type but doping content identical with collector region less than the buffering area of collector region between described collector region and base, can control puncture voltage between emitter region and collector region by controlling the 3rd implant angle and dosage, and undertaken by the 3rd injection that favours semiconductor substrate surface, can reduce the step that forms buffering area, reduce costs.

The technical program is by forming the base control electrode on the polysilicon layer on the base, be similar to the gate electrode of traditional MOS transistor, need not the base electrode of directly making of the prior art on the base, the bipolar transistor structure that forms like this is substantially identical with traditional mos transistor structure, and the technique of this bipolar transistor of formation and traditional standard CMOS process are fully compatible; And the emitter region of bipolar transistor/collector region junction capacitance is less, by applying voltage on the base control electrode through the coupling between base gate electrode and base dielectric layer, forming grid in the base causes leakage current and causes leakage current by grid and drive PN junction between base and emitter region, need not extra base contact hole technique, have less input capacitance; Simultaneously the polysilicon layer on the base is adulterated, make its conduction type identical with the base, can change the band gap of bipolar transistor.

The technical program is by forming doping type but doping content identical with collector region less than the buffering area of collector region between described collector region and base, can control puncture voltage between emitter region and collector region by controlling the 3rd angle of injecting and dosage, and undertaken by the 3rd injection that favours semiconductor substrate surface, can reduce the step that forms buffering area, reduce costs.

the virtual ground circuit that the technical program forms, because the bipolar transistor that adopts has the structure identical with the MOS transistor cardinal principle, can form the base electric current by apply voltage on the base control electrode by voltage control, need not to adopt that existing bipolar transistor forms with applying the step of current source in the knee reference source circuit on the base of bipolar transistor, and because the conduction type of polysilicon layer is identical with the base, changed the band gap of bipolar transistor, thereby what make that the virtual ground circuit that adopts this bipolar transistor can stable output is approximately zero voltage.

Description of drawings

Fig. 1 is existing bipolar transistor cross-sectional view;

Fig. 2 is the schematic flow sheet of method of the formation bipolar transistor of the first embodiment of the present invention;

Fig. 3 to 14 is structural representations of method of the formation bipolar transistor of the first embodiment of the present invention;

Figure 15 is the schematic flow sheet of method of the driving bipolar transistor of the third embodiment of the present invention;

Figure 16 is the structural representation of method of the driving bipolar transistor of the third embodiment of the present invention;

Figure 17, Figure 18 are the marks of bipolar transistor of the present invention;

Two times of silicon bandgap voltage circuit module schematic diagrames of the virtual ground circuit of Figure 19 fifth embodiment of the present invention, the 6th embodiment;

Figure 20 is the virtual ground circuit schematic diagram of the 5th embodiment;

Figure 21 is the reference voltage source circuit of the sixth embodiment of the present invention and two times of silicon bandgap voltage circuit diagrams of the 6th embodiment.

Embodiment

The present inventor finds, existing bipolar transistor applies electric current need to be applied directly on base stage to drive bipolar transistor, but adopts the area of the bipolar transistor that such scheme forms larger, and currentamplificationfactorβ is less.In order to improve the performance of bipolar transistor, prior art has been added more complicated structure (such as polysilicon emitter, n+ buried layer, epitaxial silicon, SiGe base stage etc.) to obtain high performance vertical bipolar transistor.Yet, the processing step that these add for bipolar transistor and thermal cycle have departed from standard CMOS process, therefore, can not use existing CMOS logical base and IP storehouse, therefore these method costs that form bipolar transistor are higher, therefore this high performance BiCMOS technology range of application is not extensive.

SOI (silicon-on-insulator) technology is considered to the most attractive technology of 32 nanometer nodes and following technology thereof, have and entirely exhaust and short channel length (i.e. thinner base thickness), the parasitic lateral bipolar transistor provides suitable performance, with the base contact hole of removing grid oxide layer and forming by polysilicon gate.The main technique of making the high-performance lateral bipolar transistor be to make thinner base shape with and contact hole, and the collector electrode of shallow doping is (to obtain higher BV _CEo), to the minimum process complexity of CMOS base process using.A kind of design that obtains the high-performance lateral bipolar transistor is by aiming at nitride side wall and the shallow p-type base that mixes collector electrode formation.Another kind of design is to have the polysilicon gap wall of employing and N-shaped impure collecting electrode p-type base.

The transistorized grid of nMOS on SOI and pMOS are introduced leakage current (GIDL) can be as the base electric current to open parasitic horizontal npn or pnp bipolar transistor.The present invention is defined as " lateral bipolar transistor that GIDL drives " in order to distinguish its drive pattern.The present inventor by suppress raceway groove transoid (by forming high threshold voltage), GIDL electric current and bipolar transistor performance can be improved, such as by improving the second implantation dosage, forming and entirely to exhaust the base and prevent transoid, form the less schemes such as channel length, added 4 masks in the present invention, the base that is respectively nMOS and pMOS carries out the first additional second injection of injecting and forming collector region and emitter region.

The lateral bipolar transistor that employing of the present invention GIDL drives has less emitter/collector junction capacitance, voltage control base electric current, need not additionally to form the base contact hole, and less input capacitance.The present invention gives a kind of upward virtual ground circuit of the bipolar transistor of the GIDL initiation of the CMOS of formation of SOI of the present invention that adopts.

Followingly describe specific embodiment in detail according to accompanying drawing, above-mentioned purpose and advantage of the present invention will be clearer.

1. the first embodiment

The present embodiment provides a kind of manufacture method of bipolar transistor, and its idiographic flow please refer to shown in Figure 2, comprises the steps:

Step S101 provides silicon-on-insulator, and described silicon-on-insulator comprises silicon base, is positioned at oxygen buried layer and top layer silicon on silicon base successively;

Step S102 is formed with the source region on top layer silicon;

Step S103 carries out first and injects in active area;

Step S104 forms base gate dielectric layer and polysilicon layer successively on top layer silicon;

Step S105 carries out the 4th injection in polysilicon layer, make the polysilicon layer conduction type identical with base conduction type to be formed;

Step S106, base gate dielectric layer and base gate electrode outside the zone, base are removed in zone, definition base.

Step S107 carries out second and injects in the active area beyond the base, the conductivity type opposite of the conduction type of the described second ion that injects and the first ion that injects forms emitter region and collector region;

Step S108 forms the first interlayer dielectric layer on top layer silicon, cover described base gate dielectric layer and polysilicon layer;

Step S109 forms the first contact hole, the second contact hole and the 3rd contact hole in the first interlayer dielectric layer;

Step S110, form conductive layer on the first interlayer dielectric layer, adopt conductive layer to form collector electrode, emitter and base control electrode, described emitter is connected with emitter region electricity by the first contact hole, described emitter is connected with collector region electricity by the second contact hole, and described base control electrode is connected with polysilicon layer electricity by the 3rd contact hole.

At first with reference to Fig. 3, execution in step S101 provides silicon-on-insulator (SOI) 100.Described silicon-on-insulator 100 comprises oxygen buried layer 102 on silicon base 101, silicon base 101 and the top layer silicon 103 on oxygen buried layer 102.

The conduction type of the top layer silicon 103 of described silicon-on-insulator 100 is p-type.Certainly, also can be N-shaped, this sentences p-type is that example is illustrated.For the formation method of NPN, PNP bipolar transistor is described, the present invention is illustrated simultaneously in the present embodiment, should too not limit protection scope of the present invention at this.

The thickness of the top layer silicon 103 of described silicon-on-insulator 100 is 10nm to 150nm.

Silicon-on-insulator 100 passes through to enclose the oxygen buried layer 102 of an insulation between two-layer silicon substrate, thereby transistor unit is vertically isolated.The material of above-mentioned oxygen buried layer 102 is silica normally, and thickness is about 100nm to 1 μ m, therefore again oxygen buried layer 102 is called and imbeds oxide skin(coating) (Buried Oxide, BOX).Oxygen buried layer 102 can make electronics flow to another transistor gate from a transistor gate effectively, does not allow unnecessary electronics leak on lower floor's silicon base 101.The advantages such as the semiconductor device that forms with silicon-on-insulator 100 has that parasitic capacitance is little, short-channel effect is little, speed is fast, integrated level is high, low in energy consumption, high temperature resistant and radioresistance.

Then execution in step S102, be formed with the source region on top layer silicon 103.Specifically comprise: at first form shallow trench on top layer silicon 103, so that the transistor that forms is carried out lateral isolation on silicon-on-insulator 100.Described shallow trench is divided into active area and area of isolation with top layer silicon 103, and namely on top layer silicon 103, the zone outside active area is area of isolation.

Form shallow trench processes as shown in Figure 4, the top layer silicon 103 on etching silicon-on-insulator 100 forms shallow trench 104 to exposing oxygen buried layer 102.

Then, at the interior filling dielectric material of shallow trench 104, form as shown in Figure 5.Dielectric substance in shallow trench 104 interior fillings can be identical with the material of oxygen buried layer 102, makes dielectric substance and oxygen buried layer 102 in shallow trench 104 interior fillings combine together fully.

In manufacture process, for shallow trench 104 is filled up fully, and obtain an even curface, usually also can carry out to silicon-on-insulator 100 step of cmp.Described cmp is those skilled in the art's customary means, does not repeat them here.

Through above-mentioned technique, formed active area.

Then, execution in step S103 carries out first and injects in active area, carries out the first purpose of injecting and prepares for the base (and MOS transistor) that forms bipolar transistor, specifically please refer to Fig. 6.

The described first ionic species that injects can be selected according to the bipolar transistor of manufacturing, when for example needing to make NPN transistor (or N-type MOS transistor), need to inject the p-type example, such as being the boron example, energy range is 1KeV to 60KeV, and dosage range is 1 * 10 ¹²cm ^-2To 1 * 10 ¹³cm ^-2When needing to make PNP transistor, need Implanted n-Type impurity, such as being phosphorus or arsenic ion, energy range is 5KeV to 300KeV, and dosage range is 1 * 10 ¹²cm ^-2To 1 * 10 ¹³cm ^-2Through above-mentioned injection, the concentration of the ion of the injection zone of formation is approximately 1 * 10 ¹⁷cm ^-3To 1 * 10 ²⁰cm ^-3

MOS transistor technique is corresponding with forming, and this step injects to be and forms simultaneously assorted trap (Well) technique that MOS transistor is mixed.

Through the first injection, form respectively the first injection region 105a of N-shaped and the first injection region 105b of p-type.

Simultaneously, in order further to increase the base concentration of formed bipolar transistor to prevent the base transoid, can also carry out the first additional injection in the first injection region 105a and the first injection region 105b, the base of the conduction type of the described first additional ion that injects and the bipolar transistor to be formed i.e. conduction type of the ion of the first injection is identical.Namely for npn type bipolar transistor, need to inject p-type impurity, such as being the boron ion, energy range is 1KeV to 60KeV, and dosage range is 1 * 10 ¹²cm ^-2To 1 * 10 ¹³cm ^-2For the positive-negative-positive bipolar transistor, need Implanted n-Type impurity, such as being phosphorus or arsenic ion, energy range is 5KeV to 300KeV, dosage range is 1 * 10 ¹²cm ^-2To 1 * 10 ¹³cm ^-2Through the described first additional injection, the doping content in the zone, base of bipolar transistor to be formed is approximately 2～10 times of doping content of the channel region of existing MOS transistor, therefore the top layer of base can be by the voltage transoid on the base gate electrode, of particular note, the described first additional injection is the step that is used in particular for bipolar transistor.

As a specific embodiment, for npn type bipolar transistor, the ion of injection is the boron ion, and the energy of injection is 10KeV, and dosage is 3 * 10 ¹²cm ^-2

As another specific embodiment, for the positive-negative-positive bipolar transistor, the ion of injection is phosphonium ion, and the energy of injection is 30KeV, and dosage is 2 * 10 ¹²cm ^-2

Carry out the first additional injection and need extra two mask plates (respectively for NPN type and positive-negative-positive bipolar transistor) that increase, the present invention suppresses base transoid (namely can improve base concentration by the first additional injection, formation entirely exhausts the base and prevents transoid), can improve GIDL electric current and bipolar transistor performance like this by the first additional injection.

The described first additional purpose of injecting is to increase base concentration, therefore only get final product in the base, but because the base area is less, in actual process, usually whole well region is carried out the first additional injection, then increased dosage amount in the technique of follow-up formation collector region and emitter region, neutralize with the ion that this step is injected.

Then execution in step S104, corresponding base regional location forms base gate dielectric layer and base gate electrode successively on top layer silicon, also forms the gate electrode of MOS transistor simultaneously.

With reference to Fig. 7, form successively base gate dielectric layer 116 and base gate electrode 117 on silicon-on-insulator 100.Described base gate dielectric layer 116 can be silica, silicon nitride, silicon oxynitride, can also be high dielectric constant material, such as hafnium oxide, aluminium oxide etc.Described base gate electrode 117 can be polysilicon or metal or metal nitride, such as being a kind of or its combination in any in tungsten, tungsten nitride, aluminium, silver, chromium, molybdenum, nickel, palladium, platinum, titanium, titanium nitride, tantalum, tantalum nitride etc.

Then, execution in step S105 carries out the 4th injection in polysilicon layer, makes the polysilicon layer conduction type identical with base conduction type to be formed; Specifically please refer to Fig. 8, the conduction type of the described the 4th ion that injects is identical with the base, opposite with the emitter region of follow-up formation and collector region.

If bipolar transistor is positive-negative-positive, described the 4th ion is the N-shaped ion, such as being phosphorus or arsenic ion.

If bipolar transistor is the NPN type, described the 4th ion is the p-type ion, such as being boron or boron fluoride ion.The 4th Implantation Energy scope of injecting and dosage range and MOS transistor heavy-doped source/drain electrode injection is identical, so the 4th injection can be implemented simultaneously with the heavy-doped source of MOS transistor/drain electrode.

Then with reference to figure 9, execution in step S106 defines the zone, base, removes base gate dielectric layer 116 and base gate electrode 117 outside the zone, base.

Concrete technology comprises: form photoresist layer on base gate electrode 117; Utilization exposes to photoresist layer with the mask plate of base (simultaneously also with the gate electrode of MOS transistor) shape, and the base shape on mask plate is transferred to photoresist layer; Develop, remove the photoresist layer outside the zone, base; Remove base base gate electrode 117 and base gate dielectric layer 116 parts in addition with plasma etching technology successively take photoresist layer as mask at last.Described plasma etching technology is those skilled in the art's customary means, does not repeat them here.Through above-mentioned etching, the part of the first injection region 105a of

base gate electrode

117 and 116 coverings of base gate dielectric layer and the first injection region 105b forms the zone, base.

Formation gate dielectric layer in above-mentioned definition base zone and the technique that forms described base gate dielectric layer 116 and base gate electrode 117 on the zone, base and existing CMOS technique is identical with the technique of gate electrode.

In the present embodiment, separator 118 can also be formed, as shown in figure 10 on the sidewall of the base gate dielectric layer 116 after etching and base gate electrode 117.Described separator 118 can adopt a kind of in silica, silicon nitride, silicon oxynitride or its combination.

Then execution in step S107, specifically please refer to Figure 11, carries out second and inject in the active area beyond the base, forms respectively low-doped p-type emitter region 112a, N-shaped emitter region 112b, p-type collector region 113a and N-shaped collector region 113b.Simultaneously, mask effect due to base gate dielectric layer 116 and base gate electrode 117 and separator 118, not carrying out second in the part first injection region 105a of correspondence and the first injection region 105b injects, namely do not carry out second in the zone, base and inject, this zone, base forms respectively

base

111a and 111b.

The conductivity type opposite of the conduction type of the described second ion that injects and the first ion that injects, for example, the first injection be the p-type ion, what inject in this step is the N-shaped ion; And if what inject to inject is the N-shaped ion first, what inject in this step is the p-type ion.And it is enough large that the ion concentration that this step is injected is wanted, because at first will neutralize to the first ion that injects.

The described second dosage that injects is at the 14 power orders of magnitude, and Implantation Energy is difference along with the kind difference of ion, if the described second ion that injects is N-shaped, ion can be phosphonium ion or arsenic ion, and energy range is 1Kev to 100KeV.

The described second dosage that injects is at the 14 power orders of magnitude, Implantation Energy is along with the kind of ion is different and different, as another specific embodiment, if the described second ion that injects is p-type, ion is boron or boron fluoride ion, and energy range is 1KeV to 100KeV.

The above-mentioned second technique of injecting is more similar but be not suitable for sharing than the technique of injecting with the low-doped leakage (LDD) of CMOS technique, main different because inject the energy or the dosage that both inject, to optimize between collector region and base buffering area (as described below) in order to reach required puncture voltage.But of particular note, even do not increase this second implantation step, the bipolar transistor of formation still can be worked, and just its puncture voltage is lower, specially illustrates at this, should too not limit protection scope of the present invention.

Then carry out the 3rd injection, part collector region and whole emitter region are further adulterated, to form Highly doped emitter and collector region.The collector region that is not further adulterated forms buffering area, and described the 3rd ion conduction type is identical with the second ionic conduction type of injecting.

In the present embodiment, the described the 3rd direction of injecting favours described top layer silicon 103 surfaces, specifically please refer to Figure 12, form heavily doped emitter region 120a, the 120b and lightly doped buffering area 114a, the 114b that are connected with 111b with base 111a, and the heavily doped collector region 119a, the 119b that are connected with

buffering area

114a, 114b respectively.

The described the 3rd angular range that injects is 30 ° to 60 °, preferred 40 ° to 50 ° scopes.The dosage range of the described the 3rd ion that injects is the 15 power orders of magnitude.

If adopt the 3rd injection of inclination of the present invention, be equivalent to collector region and emitter region have been carried out the injection of two steps, for optimized device performance, can be optimized the second injection condition according to the 3rd condition of injecting, such as suitably reducing the second dosage that injects, the doping of buffering area is reduced, promote the puncture voltage of buffering area between collector region and base.As for the adjustment to the second implantation dosage, the art personnel can carry out simple transformation according to the 3rd dosage that injects, and should too not limit protection scope of the present invention at this.

Execution in step S108 forms the first interlayer dielectric layer 121 on top layer silicon, cover described base gate dielectric layer 116 and base gate electrode 117.Specifically please refer to Figure 13, described the first interlayer dielectric layer 121 can be silicate glass or the advanced low-k materials of silica, silicon nitride, silicon oxynitride, doping, and described advanced low-k materials can be the carborundum etc. of doping.The purpose that forms described the first interlayer dielectric layer 121 is to isolating between each device layer.

Execution in step S109 and step S110 specifically please refer to Figure 14, comprising: at interior the

first contact hole

122a and 122b, the

second contact hole

123a and 123b and the 3rd contact hole 124a and the 124b of forming respectively of the first interlayer dielectric layer 121; Then form conductive layer on the first interlayer dielectric layer 121, adopt conductive layer to form respectively emitter 125a and 125b,

collector electrode

126a and 126b and

base control electrode

127a and 127b, described

emitter

125a and 125b are connected with 120b electricity with emitter region 120a with 122b by the first contact hole 122a respectively; Described

collector electrode

126a and 126b are connected with 119b electricity with collector region 119a with 123b by the second contact hole 123a respectively; Described

base control electrode

127a and 127b are connected with base gate electrode 117 electricity with 124b by the 3rd contact hole 124a respectively.

The present embodiment is by forming

base control electrode

124a and 124b on the base gate electrode 117 on the base, be similar to the gate electrode of traditional MOS transistor, need not the base electrode of directly making of the prior art on the base, the bipolar transistor structure that forms like this is substantially identical with traditional mos transistor structure, and the technique of this bipolar transistor of formation and traditional standard CMOS process are fully compatible; And the emitter region of bipolar transistor/collector region junction capacitance is less, forms the base electric current by apply voltage on the base control electrode, need not extra base contact hole technique, has better simply technique.

And complete and existing CMOS process compatible in the method for above-mentioned formation bipolar transistor, namely also can form MOS transistor on same wafer in the preparation bipolar transistor.The above-mentioned step that forms bipolar transistor of just having narrated especially is in this special instruction.

2. the second embodiment

Formed the bipolar transistor of the second embodiment of the present invention based on the technique of above-mentioned the first embodiment, specifically please refer to Figure 14, comprise: silicon-on-insulator 100, described silicon-on-insulator comprise silicon base 101, are positioned at oxygen buried layer 102 and top layer silicon 103 on silicon base 101 successively; Base 111a or 111b, emitter region 120a or 120b and collector region 119a or 119b, be positioned at top layer silicon 103, described base 111a is between emitter region 120a and collector region 119a, described base 111b is between emitter region 120b and collector region 119b, described emitter region 120a or 120b are identical with the conduction type of collector region 119a or 119b, and described base 111a or 111b conduction type and emitter region 120a or 120b and collector region 119a or 119b are opposite; Base gate dielectric layer 116 is positioned on top layer silicon 103 corresponding to base 111a or 111b position; Polysilicon layer 117 is positioned on base gate dielectric layer 116; Emitter 125a is connected with emitter region 120a electricity by the first contact hole 122a, and emitter 125b is connected with emitter region 120b electricity by the first contact hole 122b; Collector electrode 126a is connected with collector region 119a electricity by the second contact hole 123a, and collector electrode 126b is connected with collector region 119b electricity by the second contact hole 123b; Described bipolar transistor also comprises: base control electrode 127a or 127b, be connected with electricity with polysilicon layer 117 electricity by the 3rd contact hole 124a or 124b and be connected, the conduction type of described polysilicon layer 117 is identical with the base, opposite with emitter region 120a or 120b and collector region 119a or 119b, this point is opposite with traditional MOS transistor, and the conduction type of the polysilicon layer of traditional MOS transistor (gate electrode) is opposite with channel region (base that is equivalent to the application).

Also comprise buffering area 114a between described collector region 119a and base 111a, also comprise buffering area 114b between described collector region 119b and base 111b, the doping type of described

buffering area

114a or 114b is identical with

collector region

119a or 119b, but doping content is less than

collector region

119a or 119b.

Between described buffering area 114a and collector region 119a, the interface of the interface between buffering area 114b and collector region 119b and described emitter region 120a and base 111a, emitter region 120b and base 111b favours described top layer silicon 103 surfaces.

the polysilicon layer of the bipolar transistor base control electrode that forms in the present embodiment adulterates, its conduction type is identical with the base, different from traditional technical scheme, the conduction type of the polysilicon layer of traditional MOS transistor grid and channel region conductivity type opposite, the present invention is identical with the base by the conduction type that makes polysilicon layer, can change the conducting voltage (required the first voltage that applies on the base control electrode) of the present invention's bipolar transistor and make the output voltage V ref of band-gap reference source circuit move a band gap magnitude (as described in the third and fourth and the 5th embodiment hereinafter).

3. the 3rd embodiment

The present embodiment also provides the method for the conduction type of the polysilicon layer in a kind of driving the second embodiment bipolar transistor identical with the base, please refer to Figure 15, provides the idiographic flow schematic diagram that drives above-mentioned bipolar transistor, comprising:

Step S201 applies the first voltage on the base control electrode;

Step S202 applies second voltage on collector electrode;

Step S203 applies tertiary voltage on emitter; Effect sub-collector top layer formation minority carrier (Minority Carriers) at the formed electric field of above-mentioned voltage, described minority carrier number carrier type more than the base is identical, and inflow base, form grid and cause leakage current, the charge carrier that the formation grid cause leakage current continues to flow to the emitter region, makes the PN junction forward conduction between base and emitter.

The below provides driving method and principle for npn type bipolar transistor, please refer to Figure 16.In Figure 16, the layer of each label representative is same as described above, is introduced no longer one by one at this.

Apply the first voltage Vb on the base of described npn type bipolar transistor control electrode 127b; Apply second voltage Vc on collector electrode 126b; Apply tertiary voltage Ve on emitter 125b, the first voltage Vb on described base control electrode 127b is lower than the second voltage Vc on collector electrode 126b, and the tertiary voltage Ve on described emitter 125b is lower than the first voltage Vb.

top layer at the effect sub-collector 119b of the formed electric field of above-mentioned voltage forms minority carrier, be in this embodiment the hole, majority carrier type in the base 111b of described minority carrier and P type is identical, because the first voltage Vb on base control electrode 127b is low, described hole will be subject to the attraction of the formed electric field of this voltage, move and flow into base 111b to base 111b, form grid and cause leakage current, because the tertiary voltage Ve on described emitter is lower than the second voltage Vc on collector electrode, the electromotive force that is described base 111b is elevated, make the PN junction between base 111b and emitter region 120b form forward bias, thereby npn bipolar transistor is by forward conduction, penetrate electronics from the 120b of emitter region, oppositely flow in collector region 119b, for the β of base electric current doubly, thereby realize adopting the base to control the formed grid of voltage Vb and cause leakage current unlatching npn bipolar transistor, with prior art directly with the upper electrode that forms of base 111b, and the access current source is compared, has less bipolar transistor firing current.

As an embodiment, described the first voltage Vb is about and is less than or equal to 0.5Vdd, and described second voltage Vc is Vdd, and described tertiary voltage is 0V, and the silicon base voltage of described silicon-on-insulator is 0V.

If drive the positive-negative-positive bipolar transistor, also can adopt similar method, such as the first voltage Vb that applies on the base control electrode; Apply second voltage Vc on collector electrode; Apply tertiary voltage Ve on emitter, on described base control electrode, the first voltage Vb is higher than second voltage Vc on collector electrode, and the tertiary voltage Ve on described emitter is higher than second voltage Vc.In actual use, the tertiary voltage Ve on described emitter is necessarily higher than the second voltage Vc on collector electrode, so the forward bias a little of the PN junction between P type emitter region and N-type base, but N-type base and P type collector region PN junction are reverse bias, not conducting.in moment (such as at follow-up reference voltage source circuit, virtual ground circuit, amplifier in two times of silicon bandgap voltage circuit carries out in dynamic adjustment process) in situation, the first voltage Vb might be simultaneously higher than second voltage Vc and tertiary voltage Ve, make simultaneously P type collector region and top layer, emitter region transoid (electronics gathering), but the transoid electronics that only has the collector region top layer flow into the N-type base (make between emitter region and N-type base PN junction more forward conduction launch the hole), and top layer, emitter region transoid electronics can not flow into the N-type base (because of the current potential of N-type base lower) repel electronics and flow into from the top layer, emitter region), so the PN junction between P type collector region and N-type base can not be switched on.Generally, the first voltage Vb is between tertiary voltage Ve and second voltage Vc.

As an embodiment, described the first voltage Vb is about more than or equal to 0.5Vdd, and described second voltage Vc is 0V, and described tertiary voltage Ve is Vdd, and the silicon base voltage of described silicon-on-insulator is Vdd.

Above-mentioned Vdd is the voltage of external voltage source, such as being 3.8V, 2.5V, 1.8V, 1.0V etc.

but due to the doping polycrystalline silicon layer of the base control electrode (conductivity type opposite of the conduction type of conventional MOS transistorized polysilicon layer and channel region (base that be equivalent to the application) opposite to the transistorized polysilicon layer of conventional MOS, more than the application's base control electrode, the crystal silicon layer impure base region is identical, inner base control electrode can be with to collector region differ from a band gap magnitude), and band gap magnitude of required the first positive good job of voltage in addition on the base control electrode of the bipolar transistor that on the base control electrode, required the first voltage ratio doping polycrystalline silicon layer in addition is identical with the transistorized polysilicon layer of conventional MOS.

namely for the PNP bipolar transistor, due to the N-type polysilicon layer of base control electrode can be with made P type collector region top layer band curvature and tend to transoid (be P type collector region top layer band curvature approximately one can band gap (band gap), make electronics be gathered in the collector region top layer), on the base control electrode, required unlatching forms the voltage (being that the current potential of base control electrode is higher than the value of current potential on collector electrode) of GIDL electric current than the little band gap of voltage (being that the voltage of base control electrode is closer to collector voltage) of the unlatching formation GIDL electric current of the bipolar transistor identical with the transistorized polysilicon layer of conventional MOS.

If for npn bipolar transistor, because the P type polysilicon layer of base control electrode can be with and make N-type collecting zone top layer band curvature trend transoid (be N-type collecting zone top layer band curvature approximately can band gap (band gap) make void coalescence on the collecting zone top layer), the voltage (being the value of the current potential of base control electrode lower than collector potential) that on the base control electrode, required unlatching forms the GIDL electric current forms the large band gap of voltage (being that the voltage of base control electrode is closer to collector voltage) of GIDL electric current than the unlatching of the bipolar transistor identical with the transistorized polysilicon layer of conventional MOS.

4. the 4th embodiment

For convenient and image, bipolar transistor is carried out mark, the present inventor proposes following mark, as shown in Figure 17 and 18.

Figure 17 provides the mark of positive-negative-positive bipolar transistor P1, and Figure 18 provides the mark of npn type bipolar transistor N1, and described bipolar transistor P1 and N1 all have three extraction electrodes, represents respectively emitter e, collector electrode c and base control electrode b; For positive-negative-positive bipolar transistor P1, described emitter e is upper and the arrow head is inside, emitter e for npn type bipolar transistor N1 all has half arrow at the base control electrode b of lower and the outside described bipolar transistor P1 of arrow and N1, for positive-negative-positive bipolar transistor P1, described half arrow points to emitter e from collector electrode c, identical with the electron stream direction, flow to high voltage, for npn type bipolar transistor N1, described half arrow points to emitter e from collector electrode c, identical with the hole flow path direction, flow to low voltage.Adopt above-mentioned mark to represent in following circuit diagram.

The present invention also provides a kind of virtual ground circuit of the bipolar transistor with the second embodiment, Figure 19 provides the circuit module schematic diagram with above-mentioned bipolar transistor that the present embodiment provides, comprise: first end and the second end have the first voltage difference between described first end and the second end; The first current source I1, an end is electrically connected to first end; The first bipolar transistor BP1, described the first bipolar transistor BP1 has emitter, collector electrode and base control electrode, and described emitter is electrically connected to the other end of the first current source; The first load r1, an end is electrically connected to the collector electrode of the first bipolar transistor BP1, and the other end is electrically connected to the second end.

Described circuit also comprises: the 3rd end and the 4th end have a second voltage poor between described the 3rd end and the 4th end; The second current source I2, an end is electrically connected to the 3rd end; The second bipolar transistor BP2, described the second bipolar transistor BP2 has emitter, collector electrode and base control electrode, and described emitter is electrically connected to the other end of the second current source I2; The second load r2, an end is electrically connected to the collector electrode of the second bipolar transistor BP2, and the other end is electrically connected to the 4th end; The base control electrode of the base control electrode of described the first bipolar transistor BP1 and the second bipolar transistor BP2 is electrically connected, and as the output of described virtual ground circuit, described the first bipolar transistor BP1 and the second bipolar transistor BP2 are positive-negative-positive.

Described circuit also comprises: control unit 10, have first input end, the second input and output, described first input end is electrically connected to the emitter of the first bipolar transistor BP1, the second input is electrically connected to the emitter of the second bipolar transistor BP2, and output is electrically connected to the output of described band-gap reference source circuit; The collector current that described control unit 10 makes the collector current of the emitter current of the first bipolar transistor BP1 and the first bipolar transistor BP1 be electric current, the emitter current that makes the second bipolar transistor BP2 and the second bipolar transistor BP2 of the first current source I1 output is the electric current that the second current source I2 exports; The temperature drift coefficient of the output voltage of the output that the first voltage difference and second voltage are poor by selecting, the value of the output current of the output current of the first current source, the second current source and the first load and the second load makes described band-gap reference source circuit is zero.

It needs to be noted, but the base gate electrode of PNP bipolar transistor herein is N-type polysilicon layer (with the collector region conductivity type opposite).

According to the circuit of Figure 19, the reference voltage V of its output _refFor:

V _ref＝V _gd2+V _r2＝V _gd2+I _r2·r2；

Wherein, V _gd2Be voltage between the base gate electrode of the second bipolar transistor BP2 and collector region, V _r2Be the voltage on the second load r2, I _r2It is the electric current on the second load r2;

Control unit 10 makes on the base control electrode of the first bipolar transistor BP1 and the second bipolar transistor BP2 voltage identical, therefore:

I _r2＝I ₂＝(V _gd2-V _gd1-I ₁r ₁)/r ₂＝ΔV _gd/r ₂；

Because the electric current of the second current source output current and the first current source output always is designed to certain relation, suppose I herein ₂=nI ₁

V _ref=V _gd2+ Δ V _gdNr ₂/ (n r ₂+ r ₁);

Therefore, δ (V _ref/ δ T)=δ (V _gd2)/δ T+nr ₂/ (n r ₂+ r ₁) δ (Δ V _gd)/δ T

From experimental data δ (V _gd2)/δ T＜0, and δ (Δ V _gd)/δ T＞0;

And by adjusting nr ₂/ (n r ₂+ r ₁), can make δ (V _ref/ δ _T) be approximately zero, obtains stable output voltage V ref, namely by selection the first voltage difference with second voltage is poor, the value of output current, the first load r1 and the second load r2 of the output current of the first current source I1, the second current source I2, and V _gdWith Δ V _gdThe experimental temperature coefficient value, the temperature drift coefficient of output voltage that can make the output of described band-gap reference source circuit is zero.

In the present embodiment, the size of described the first bipolar transistor BP1 and the second bipolar transistor BP2 is identical with structure.

For the complexity that further reduces to regulate, can further optimize, poor identical such as choosing the first voltage difference and second voltage; Choosing the first load is the first resistance and the second resistance, and choosing the second load is the second resistance.

The below is illustrated described virtual ground circuit operation principle take the positive-negative-positive bipolar transistor as example.

5. the 5th embodiment

The present invention also provides a kind of virtual ground circuit of the bipolar transistor with the second embodiment, specifically please refer to Figure 20, and comprising: the first current source I1, input are electrically connected to the first external voltage source; The second current source I2, input are electrically connected to the second external voltage source; The first resistance R 1 and second resistance R 2, the one end ground connection of series connection; Amplifier K, two inputs are connected to respectively the output of the first current source I1 and the second current source I2; Described band-gap reference source circuit also comprises: the first bipolar transistor P1, emitter are electrically connected to the first current source I1 output, and collector electrode is electrically connected to the first resistance R 1 and the other end of the second resistance R 2, the i.e. ungrounded end of series connection; The second bipolar transistor P2, emitter is electrically connected to the output of the second current source I2, and collector electrode is electrically connected between first resistance R 1 and the second resistance R 2 of series connection; The base control electrode of the base control electrode of described the first bipolar transistor P1 and the second bipolar transistor P2 is connected to the output of amplifier K, and described output is as the output of virtual ground circuit, output reference voltage Vref; Described the first bipolar transistor P1 with the second bipolar transistor P2 be PNP transistor, the conduction type with polysilicon layer the second bipolar transistor P2 described the first bipolar transistor P1 is opposite with the base.

The described second external voltage source voltage is identical with the first external voltage source voltage, is Vdd.

Aforementioned control unit adopts described operational amplifier K, it is known that described operational amplifier K act as those skilled in the art institute, in this only briefly narration. operational amplifier K can dynamically adjust its output voltage according to the voltage of two input, even its input (+) is higher a little little by little than input (-), output voltage will be very high, until the voltage of input (+) input is identical with the voltage of input (-); Vice versa, even the input voltage of input (-) is little by little lower a little than the voltage of input (+), output voltage will be very high, until the voltage of input (+) input is identical with the voltage of input (-).According to above-mentioned action principle, the collector current that the collector current of the emitter current of the first bipolar transistor BP1 and the first bipolar transistor BP1 all can be exported electric current, the emitter current that makes the second bipolar transistor BP2 and the second bipolar transistor BP2 of the first current source I1 output all is output as the electric current of the second current source I2 output and the almost nil silicon bandgap voltage of final output acquisition temperature coefficient.

Output reference voltage V in Figure 20 _refFor:

V _ref＝V _gd2+V _R1＝V _gd2+I _R1·R1＝V _gd2+(n+1)·I ₁·R ₁；

Wherein, V _gd2Be voltage between the grid of bipolar transistor P2 and drain electrode, V _R1Be the voltage on the first resistance R 1, I _R1=(n+1) I ₁

I _R2＝I ₁＝(V _gd2-V _gd1)/R ₂＝ΔV _gd/R ₂；

V _ref＝V _gd2+(n+1)·ΔV _gd·(R ₁/R ₂)； (1)

In order to make δ V _ref/ δ T～0,

δ(V _ref/δT)＝δ(V _gd2)/δT+(n+1)·(R ₁/R ₂)·δ(ΔV _gd)/8T

Due to δ (V _gd2)/δ T＜0, and δ (Δ V _gd)/δ T＞0;

Therefore, by adjusting (n+1) (R ₁/ R ₂), can make δ (V _ref/ δ _T) be approximately zero, obtain the almost nil output voltage V ref of temperature coefficient.

For the positive-negative-positive bipolar transistor, above-mentioned δ (V _gd2)/δ T＜0 obtains based on following reasoning:

I _GIDL＝A·E _s·exp(-B/E _s)；

Wherein, A is that a constant is proportional to the collector region area; E _sBe the collector region surface field; B is constant; I _GIDLThe grid that are the first bipolar transistor P1 cause leakage current;

E _s＝(V _dg-E _g)/3T _ox；

Wherein, E _gBe silicon bandgap voltage value (approximately 1.2V); V _dgBe the voltage difference between collector region and base gate electrode; T _oxThickness when being silica for the base gate dielectric layer;

E _g＝1.12-2.4·10 ^-4·(T-300)

Following formula is drawn by empirical value; Wherein, T is temperature;

δ (I _GIDL)/δ T=I _GIDL(δ E _s/ δ T) (1/E _s) (1+B/E _s), due to I _GIDLRepresent the electric current of the output of current source I1 or I2, and the output current of current source I1 or I2 is more stable, temperature independent, therefore can set δ (I _GIDL)/δ T is approximately+and 0;

Therefore can draw δ E _s/ δ T～0=(δ V _gd/ δ T+2.410 ^-4)/3T _ox

Therefore, δ V _gd/ δ T=-2.410 ^-4＜0;

Above-mentioned δ (Δ V _gd)/δ T＞0 obtains based on following reasoning:

ΔI _GIDL＝I _GIDL1-I _GIDL2＝I _GIDL·(ΔE _s/E _s)(1+B/E _s)；

Wherein, I _GIDL2The grid that are the second bipolar transistor P2 cause leakage current

ΔE _s＝ΔV _gd/3T _ox；ΔV _gd＝3T _ox·ΔE _s；

δ(I _GIDL)/δT＝I _GIDL(δΔE _s/δT)(1/E _s)·(1+B/E _s)+I _GIDL(ΔE _s/E _s ²)(-δE _s/δT)(1+B/E _s)+I _GIDL(ΔE _s/E _s)·(-B/E _s ²)·(δE _s/δT)＝0；

So δ (Δ V _gd)/δ T=3T _ox(δ Δ E _s/ δ T)+Δ E _s3 (δ T _ox/ δ T)

＝3T _ox·(E _s/(1+B/E _s))·((ΔE _s/E _s ²)(δE _s/δT)(1+B/E _s)+(ΔE _s/E _s)·B/E _s ²)

(δE _s/δT)+ΔEs·3(δT _ox/δT)

＝3T _ox·(ΔE _s/E _s)·(δE _s/δT)·(1+(B/E _s)/(1+B/E _s)+3·ΔE _s·(δT _ox/δT)

Due to δ E _s/ δ T～0, (δ T _ox/ δ T)＞0, δ (Δ V _gd)/δ T＞0.

V herein _ref=E _s3T _ox, and Vgd～Eg, described Vgd is used for curved surface and can be with, so that Es is enough large, to attract minority carrier and to form the GIDL electric current.

With reference to Figure 20, in conjunction with the relevant description that drives the principle of PNP bipolar transistor in above-mentioned the 3rd embodiment, those skilled in the art can know, in the present embodiment, the doping type of base gate electrode is opposite with collector region, output voltage V ref draws close to the current potential of collector region, the band gap that namely descends, and namely output voltage V ref is approximately zero.But this output voltage from real " " different, be stable no-voltage, therefore not can with " " the phase short circuit, can not be subject to the impact of noise.

6. the 6th embodiment

The present embodiment also provides a kind of two times of silicon bandgap voltage circuit with npn type bipolar transistor of the present invention, the structure of described two times of silicon bandgap voltage circuit and above-mentioned virtual ground circuit structure similar, just wherein bipolar transistor is the NPN type, therefore the structure of described two times of silicon bandgap voltage circuit please refer to the associated description in Figure 19 and the 4th embodiment, does not add detailed description at this.

As one embodiment of the present of invention, the invention provides a kind of two times of concrete silicon bandgap voltage circuit, specifically please refer to Figure 21, comprise that the first resistance R 1 of series connection and the second resistance R 2, one ends are electrically connected to external voltage source; The first current source I1, an end ground connection; The second current source I2, an end ground connection; Amplifier K, two inputs are connected to respectively the other end of the first current source I1 and the second current source I2; Described band gap reference voltage source circuit also comprises: the first bipolar transistor N1, and emitter is electrically connected to the other end of the first current source I1, and collector electrode is electrically connected to the first resistance R 1 of series connection and the other end of the second resistance R 2; The second bipolar transistor N2, emitter is electrically connected to the other end of the second current source I2, and collector electrode is electrically connected between first resistance R 1 and the second resistance R 2 of series connection; The base control electrode of the base control electrode of described the first bipolar transistor N1 and the second bipolar transistor N2 is electrically connected to the output of amplifier K, and as the output of described two times of silicon bandgap voltage circuit, output reference voltage Vref.Described the first bipolar transistor and the second bipolar transistor are the NPN type

Control unit adopts described operational amplifier K, control unit, have first input end, the second input and output, first input end is electrically connected to the emitter of the first bipolar transistor, the second input is electrically connected to the emitter of the second bipolar transistor, and output is electrically connected to the output of described two times of silicon bandgap voltage circuit; The collector current that described control unit makes the collector current of the emitter current of the first bipolar transistor and the first bipolar transistor be electric current, the emitter current that makes the second bipolar transistor and second bipolar transistor of the first current source output is the electric current that the second current source is exported; It is zero and to make the output voltage of the output of described two times of silicon bandgap voltage circuit be two times of silicon band gap that the value of the output current by selecting the first current source, the output current of the second current source and the first load and the second load makes the temperature drift coefficient of output voltage of the output of described two times of silicon bandgap voltage circuit.

Described the first bipolar transistor is identical with the second bipolar transistor structure; Described the first voltage difference and second voltage are poor identical; Described the first load is the first resistance and the second resistance, and described the second load is the second resistance.Described first end and the 3rd end ground connection; Described the second end and the external voltage source of the 4th termination.Doping content with polysilicon layer the second bipolar transistor described the first bipolar transistor is identical.

Described two times of silicon bandgap voltage circuit, as shown in figure 21, but the base gate electrode of npn bipolar transistor herein is P type polysilicon layer (with the collector region conductivity type opposite).

With reference to Figure 21, description in conjunction with the principle of relevant driving N PN bipolar transistor in above-mentioned the 3rd embodiment, those skilled in the art can know, the doping type that changes the base gate electrode in the present embodiment is opposite with collector region, output voltage V ref draws close to the current potential of collector region, namely increase a band gap, be that output voltage V ref is two times of silicon bandgap voltage, namely be approximately 2.5V, this output voltage can replace the external voltage source of existing 2.5V, and the temperature coefficient of this voltage is zero substantially, and more stable, this voltage can not be subject to the impact of noise simultaneously.

Bipolar transistor of the present invention not only can be used for above-mentioned virtual ground circuit and two times of silicon bandgap voltage circuit, can also be applied to other digital circuits, such as inverter (inverter), logic gate (logicgates), static random access memory (SRAM) etc.

Although the present invention with preferred embodiment openly as above; but it is not to limit claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.

Claims

1. the virtual ground circuit of a bipolar transistor comprises:

First end and the second end have the first voltage difference between described first end and the second end;

The first current source, an end is electrically connected to first end;

The first bipolar transistor, emitter are electrically connected to the other end of the first current source;

The first load, an end is electrically connected to the collector electrode of the first bipolar transistor, and the other end is electrically connected to the second end;

The 3rd end and the 4th end have a second voltage poor between described the 3rd end and the 4th end;

The second current source, an end is electrically connected to the 3rd end;

The second bipolar transistor, emitter are electrically connected to the other end of the second current source;

The second load, an end is electrically connected to the collector electrode of the second bipolar transistor, and the other end is electrically connected to the 4th end;

The base control electrode of described the first bipolar transistor and the base control electrode of the second bipolar transistor are electrically connected, and as the output of described virtual ground circuit, described the first bipolar transistor and the second bipolar transistor are positive-negative-positive;

Wherein, the structure of described the first bipolar transistor or the second bipolar transistor comprises: silicon-on-insulator, described silicon-on-insulator comprise silicon base, are positioned at oxygen buried layer and top layer silicon on silicon base successively; Base, emitter region and collector region are positioned at top layer silicon, and described base is between emitter region and collector region, and the conduction type of described emitter region and collector region is identical, and described base conduction type is opposite with emitter region and collector region;

The base gate dielectric layer is positioned on top layer silicon corresponding to the position, base; Polysilicon layer is positioned on the base gate dielectric layer; Emitter is connected with emitter region electricity by the first contact hole; Collector electrode is connected with collector region electricity by the second contact hole; The base control electrode is connected with polysilicon layer electricity by the 3rd contact hole, and the conduction type of described polysilicon layer is identical with the base, and is opposite with emitter region and collector region;

Control unit, have first input end, the second input and output, first input end is electrically connected to the emitter of the first bipolar transistor, and the second input is electrically connected to the emitter of the second bipolar transistor, and output is electrically connected to the output of described virtual ground circuit;

The collector current that described control unit makes the collector current of the emitter current of the first bipolar transistor and the first bipolar transistor be electric current, the emitter current that makes the second bipolar transistor and second bipolar transistor of the first current source output is the electric current that the second current source is exported;

It is zero and to make the output voltage of described virtual ground circuit be zero that the value of the output current by selecting the first current source, the output current of the second current source and the first load and the second load makes the temperature drift coefficient of output voltage of the output of described virtual ground circuit.

2. virtual ground circuit as claimed in claim 1, is characterized in that, described the first bipolar transistor is identical with the second bipolar transistor structure; Described the first voltage difference and second voltage are poor identical; Described the first load is the first resistance and the second resistance, and described the second load is the second resistance.

3. virtual ground circuit as claimed in claim 2, is characterized in that, described first end and the external voltage source of the 3rd termination; Described the second end and the 4th end ground connection.

4. virtual ground circuit as claimed in claim 2, the doping content with polysilicon layer the second bipolar transistor described the first bipolar transistor is identical.

5. two times of silicon bandgap voltage circuit with bipolar transistor comprise:

The first current source, an end is electrically connected to first end;

The second current source, an end is electrically connected to the 3rd end;

The base control electrode of described the first bipolar transistor and the base control electrode of the second bipolar transistor are electrically connected, and as the output of described two times of silicon bandgap voltage circuit, described the first bipolar transistor and the second bipolar transistor are the NPN type;

Control unit, have first input end, the second input and output, first input end is electrically connected to the emitter of the first bipolar transistor, and the second input is electrically connected to the emitter of the second bipolar transistor, and output is electrically connected to the output of described two times of silicon bandgap voltage circuit;

It is zero and to make the output voltage of the output of described two times of silicon bandgap voltage circuit be two times of silicon band gap that the value of the output current by selecting the first current source, the output current of the second current source and the first load and the second load makes the temperature drift coefficient of output voltage of the output of described two times of silicon bandgap voltage circuit.

6. two times of silicon bandgap voltage circuit as claimed in claim 5, is characterized in that, described the first bipolar transistor is identical with the second bipolar transistor structure; Described the first voltage difference and second voltage are poor identical; Described the first load is the first resistance and the second resistance, and described the second load is the second resistance.

7. two times of silicon bandgap voltage circuit as claimed in claim 6, is characterized in that, described first end and the 3rd end ground connection; Described the second end and the external voltage source of the 4th termination.

8. two times of silicon bandgap voltage circuit as claimed in claim 6, the doping content with polysilicon layer the second bipolar transistor described the first bipolar transistor is identical.