CN101958708A - Clock circuit with delay function and related method thereof - Google Patents
Clock circuit with delay function and related method thereof Download PDFInfo
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- CN101958708A CN101958708A CN2009101607059A CN200910160705A CN101958708A CN 101958708 A CN101958708 A CN 101958708A CN 2009101607059 A CN2009101607059 A CN 2009101607059A CN 200910160705 A CN200910160705 A CN 200910160705A CN 101958708 A CN101958708 A CN 101958708A
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Abstract
The invention relates to a lock circuit with a delay function, comprising a first clock tree and a delay module, wherein the first clock tree is used for supplying a first clock signal and comprises a first clock root and a plurality of first subtrees; the delay module is coupled to the first clock root or one specific subtree in the plurality of first subtrees and used for delaying the first clock signal; and the delay module comprises at least two delay sections, and each delay section comprises a delay device and a connecting wire, wherein the delay time of each delay section is approximately same.
Description
Technical field
The relevant a kind of clock circuit of the present invention refers to a kind of clock circuit with delay feature especially.
Background technology
Clock balance (clock balancing) technology can be divided into " balance between clock (inter-clockbalancing) " and " clock internal balance (intra-clock balancing) " again.Wherein balance is between two different clock trees between clock, must keep the identical clock delay time (latency) to satisfy the requirement that time (setup time) is set.The clock internal balance then is must keep identical total delay time at subtrees different in the same clock trees to come the balance clock trees.
Present common way is (for example to be: buffer) follow in the clock trees (perhaps subtree) of one (one byone) adding time of delay than weak point for one, come the clock trees (perhaps subtree) of balancing delay time than weak point with delay cell.But this kind way need use a large amount of delay cell (buffer), and is neither very desirable for the consideration of cost and layout (layout); And each delay cell (buffer) has a minimum delay time, and causes the resolution of its delay not high.
Summary of the invention
One of purpose of the present invention is to provide a kind of clock circuit and method thereof with delay feature, to solve the problem in the prior art.
One of purpose of the present invention is to provide a kind of clock circuit and method thereof of utilizing the time of delay that connecting line causes, saves the number of delayer and/or increases its delay resolution.
Embodiments of the invention have disclosed a kind of clock circuit with delay feature, and it comprises one first clock trees and a Postponement module.First clock trees provides one first clock signal.First clock trees includes one first clock root and a plurality of first subtree.Postponement module is coupled to the specific subtree in the first clock root or a plurality of first subtree, is used for delay control one clock signal.Postponement module includes at least two and postpones sections, and each postpones section and includes a delayer and a connecting line, and wherein each postpones time of delay that section caused all about equally.
Embodiments of the invention have also disclosed a kind of related method thereof that is used for a clock circuit.Related method thereof comprises step: one first clock signal is provided; And utilize a Postponement module to postpone this first clock signal, and wherein this Postponement module includes at least two and postpones sections, and each postpones section and have a delayer and a connecting line, and wherein each postpones time of delay that section caused all about equally.
Embodiments of the invention have also disclosed a kind of clock circuit with delay feature, include: one first clock trees (clock tree) is used to provide one first clock signal; An and Postponement module, be coupled to this first clock trees, be used for postponing this first clock signal, this Postponement module includes: at least one postpones section, has a time of delay respectively, wherein each postpones section and includes a delayer and a connecting line, and should time of delay corresponding to the driving force of this delayer and the length of this connecting line.
Embodiments of the invention have also disclosed a kind of related method thereof that is used for a clock circuit, and this related method thereof includes: one first clock signal is provided; And utilize a Postponement module to postpone this first clock signal; Wherein, this Postponement module be utilize one time of delay form determine, wherein this Postponement module comprises at least one delayer and at least one connecting line.
Description of drawings
Fig. 1 has the schematic diagram of first embodiment of the clock circuit of delay feature for the present invention.
Fig. 2 has the schematic diagram of second embodiment of the clock circuit of delay feature for the present invention.
Fig. 3 has the schematic diagram of the 3rd embodiment of the clock circuit of delay feature for the present invention.
Fig. 4 goes up the form of the time of delay that connecting line caused of different length for the different delayer collocation of explanation.
Fig. 5 is used for the flow chart of an example operation of the related method thereof of a clock circuit for the present invention.
[main element label declaration]
100,200,300 clock circuits
110 first clock trees
120 first clock roots
ST11～ST1M first subtree
150,250 Postponement modules
DS1～DSK, DS1 '～DSK ' postpones section
The DL delayer
The N connecting line
CLK1 first clock signal
310 second clocks tree
320 second clock roots
ST21～ST2M second subtree
CLK2 second clock signal
INVCKQHD, INVCKNHD, INVCKMHD delayer kind
502～512 steps
Embodiment
Fig. 1 has the schematic diagram of first embodiment of the clock circuit 100 of delay feature for the present invention.Clock circuit 100 comprises in order to one first clock trees (clocktree) 110 and a Postponement module 150 of one first clock signal clk 1 to be provided.First clock trees 110 comprises one first clock root 120 and at least two first subtrees (as: a plurality of first subtree ST11～ST1M).In present embodiment, Postponement module 150 is coupled to the first clock root 120, is used for delay control one clock signal CLK1, yet this is not a restrictive condition of the present invention.In other embodiment, Postponement module 150 also can be coupled to the specific subtree among a plurality of first subtree ST11～ST1M, and wherein the total delay time of this specific subtree is the shortest among these a plurality of first subtree ST11～ST1M.As shown in Figure 1, Postponement module 150 comprises a plurality of delay section DS1～DSK, each postpones section DS1～DSK and includes a delayer DL and a connecting line N, wherein each postpones time of delay that section DS1～DSK caused all about equally, and the length of connecting line N is to be directly proportional with the driving force of delayer DL.Will explanation in detail in following examples about the relation between the driving force of the length of connecting line N and delayer DL.
Note that in the foregoing description a plurality of delay section DS1～DSK of Postponement module 150 are arranged in a helical form (spiral-type), but this is not a restrictive condition of the present invention.Please refer to Fig. 2, Fig. 2 has the schematic diagram of second embodiment of the clock circuit 200 of delay feature for the present invention.The framework of the clock circuit 200 of Fig. 2 and the clock circuit 100 of Fig. 1 are similar, and both differences are that in Fig. 2 a plurality of delay section DS1 '～DSK ' of Postponement module 250 is arranged in a ring-type (ring-type).Hence one can see that, and the number of a plurality of delay sections of Postponement module and the shape of being arranged thereof are not limited to.
Please refer to Fig. 3, Fig. 3 has the schematic diagram of the 3rd embodiment of the clock circuit 300 of delay feature for the present invention.The framework of the clock circuit 300 of Fig. 3 and the clock circuit 100 of Fig. 1 are similar, both differences are in Fig. 3, clock circuit 300 also comprises second clock tree 310, be used to provide second clock signal CLK2, second clock tree 310 comprises a second clock root 320 and a plurality of second subtree ST21～ST2M, wherein Postponement module 150 is coupled to the first clock root 120, and be used for adjusting clock delay time (latency) between first clock signal clk 1 and the second clock signal CLK2, so that this first clock signal clk 1 and second clock signal CLK2 (for example: synchronously reach a given reference phase difference, differ from 90 degree, or it is anti-phase).Without doubt, those skilled in the art should understand, and under spirit of the present invention, the various variations of the clock circuit that Fig. 1 to Fig. 3 mentioned all are feasible.For example, any permutation and combination of the clock circuit that Fig. 1 to Fig. 3 mentioned can be become a new alternate embodiment, this also is subordinate to the category that the present invention is contained.
Please note again, above-mentioned first embodiment and second embodiment is applicable in " clock internal balance (intra-clock balancing) " technology, can must keeps identical total delay time at subtrees different in the same clock trees and come the balance clock trees.The 3rd embodiment then is applicable in " balance between clock (inter-clock balancing) " technology, can must keep the satisfied requirement that the time is set of identical clock delay time between two different clock trees.
Please refer to Fig. 4, Fig. 4 goes up the form of the time of delay that connecting line caused of different length for the different delayer collocation of explanation.In present embodiment, be to be example with delayer INVCKQHD, INVCKNHD and INVCKMHD, the three is all an inverter, and adopt 0.11 micron system, wherein optimal delayer kind is INVCKNHD and INVCKMHD, because their size is not too large, be about half of INVCKQHD.With regard to INVCKNHD and INVCKMHD, the length of optimal connecting line is 500～800 microns (μ m), owing to be lower than 0.3 how second (ns) change-over time, therefore each postpones time of delay that section (including a delayer and a connecting line) caused and can not be subjected to signal integrity (Signal Integrity, influence SI).In addition, connecting line length be 500～800 microns time of delay approximately slightly connecting line length be 0 micron 3.5～6.2 times of time of delay, therefore, each postpones section (include a delayer and length be 500～800 microns a connecting line) and can save 2.5～5.2 delayer than independent use one delayer approximately.(layout engineer need not just layout goes out required time of delay easily according to the form of building up in advance (for example being Fig. 4) for Integratedcircuit, IC) layout for integrated circuit.For example, how second desire postpones 0.24, then can use " the INVCKQHD delayer+connection line length 1200 μ m " of two units or " the INVCKNHD delayer+connection line length 1200 μ m " of a unit.Certainly the more different time of delay units designs required time of delay more easily.In other words, its resolution will can not be subject to the time of delay (generally be about 0.03 how second) of delayer.How second for example how second be 0.029 the time of delay of " INVCKQHD delayer+connection line length 0 μ m ", and be about 0.039 the time of delay of " INVCKQHD delayer+connections line length 100 μ m " time, and then its resolution can be for 0.01 second (being 0.039-0.029) how.
Note that above-mentioned delayer can put into practice it by an inverter or a buffer, but the present invention is not limited thereto, also can adopt other element to put into practice it.In addition, 0.11 micron system only illustrates example of the present invention for being used for, but not restrictive condition of the present invention.
Can be understood by foregoing, each of Postponement module postpones section and all includes a delayer and a connecting line, and wherein each postpones time of delay that section caused all about equally, and the length of connecting line is to be directly proportional with the driving force of delayer.Thus, replace the time of delay that delayer causes, can save the number of delayer by adopting roughly isometric connecting line.In addition, a plurality of delay sections of Postponement module are arranged in a ring-type or a helical form, help the configuration of layout, to reach the purpose of saving cost and saving area.
Please refer to Fig. 5, Fig. 5 is used for the flow chart of an example operation of the related method thereof of a clock circuit for the present invention.Those skilled in the art can find corresponding step, its detailed description of Therefore, omited in the description by Fig. 1,2 of this specification, 3 embodiment.The step of above-mentioned flow process only for the present invention for feasible embodiment, and unrestricted restrictive condition of the present invention, and under the situation of spirit of the present invention, the method can also comprise other intermediate steps or several steps can be merged into one step, to do suitable variation.
Above-described embodiment only is used for technical characterictic of the present invention is described, is not to be used for limiting to category of the present invention.The disclosed clock circuit of the present invention with delay feature, not only applicable to balancing technique between clock also applicable to clock internal balance technology.Because each of Postponement module postpones time of delay that section caused all about equally, then can utilize roughly isometric connecting line to replace the time of delay that delayer causes, and saves the number of delayer.Moreover the length of the connecting line then difference of kind, driving force and the processing procedure of visual delayer is suitably adjusted it.In addition, be arranged in a ring-type or a helical form, more can reach and save cost and the purpose of saving area by a plurality of delay sections with Postponement module.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (24)
1. clock circuit with delay feature includes:
One first clock trees is used to provide one first clock signal, and this first clock trees includes:
One first clock root; And
A plurality of first subtrees; And
One Postponement module is coupled to the specific subtree in this first clock root or this a plurality of first subtrees, is used for postponing this first clock signal, and this Postponement module includes:
At least two postpone sections, and each postpones section and includes a delayer and a connecting line, and wherein each postpones time of delay that section caused all about equally.
2. clock circuit according to claim 1, wherein the length of this connecting line is to be directly proportional with the driving force of this delayer.
3. clock circuit according to claim 1, wherein this Postponement module couples this specific subtree, and the total delay time of this specific subtree is the shortest in these a plurality of first subtrees.
4. clock circuit according to claim 1, it also comprises:
One second clock tree is used to provide a second clock signal;
Wherein this Postponement module is coupled to this first clock root, and is used for adjusting the clock delay time between this first clock signal and this second clock signal.
5. clock circuit according to claim 1, wherein the length of this connecting line is 500～1200 microns.
6. clock circuit according to claim 1, wherein these at least two delay sections are arranged in a ring-type.
7. clock circuit according to claim 1, wherein these at least two delay sections are arranged in a helical form.
8. clock circuit according to claim 1, wherein these at least two delay sections are that foundation form one time of delay determines.
9. clock circuit according to claim 1, wherein these at least two delay sections have a time of delay respectively, and this time of delay is corresponding to the driving force of this delayer and the length of this connecting line.
10. related method thereof that is used for clock circuit, this related method thereof includes:
One first clock signal is provided; And
Utilize a Postponement module to postpone this first clock signal, wherein this Postponement module includes at least two and postpones section, and each delay section has a delayer and a connecting line;
Wherein each postpones time of delay that section caused all about equally.
11. method according to claim 10, wherein the length of this connecting line is to be directly proportional with the driving force of this delayer.
12. method according to claim 10, wherein this clock circuit comprises at least one first clock trees, and this first clock trees comprises one first clock root and a plurality of first subtree, and the step of utilizing this Postponement module to postpone this first clock signal comprises:
Utilize this Postponement module to adjust clock delay time between these a plurality of subtrees, wherein this Postponement module couples this specific subtree in these a plurality of first subtrees, and the total delay time of this specific subtree is the shortest in these a plurality of first subtrees.
13. method according to claim 10, this method also comprises:
One second clock signal is provided; And
The step of utilizing this Postponement module to postpone this first clock signal comprises:
Utilize this Postponement module to adjust the clock delay time of the one at least between this first clock signal and this second clock signal so that this first with this second clock signal have given reference phase difference.
14. method according to claim 10, wherein these at least two delay sections are that foundation form one time of delay determines.
15. method according to claim 10, wherein these at least two delay sections have a time of delay respectively, and this time of delay is corresponding to the driving force of this delayer and the length of this connecting line.
16. method according to claim 10, wherein, at least two of Postponement module postpone section and are arranged in a ring-type or a helical form.
17. the clock circuit with delay feature includes:
One first clock trees is used to provide one first clock signal; And
One Postponement module is coupled to this first clock trees, is used for postponing this first clock signal, and this Postponement module includes:
At least one postpones section, has a time of delay respectively, and wherein each postpones section and includes a delayer and a connecting line, and should time of delay corresponding to the driving force of this delayer and the length of this connecting line.
18. clock circuit according to claim 17, wherein these at least two delay sections are that foundation form one time of delay determines.
19. clock circuit according to claim 17, wherein this at least one delay section includes one first delay section and one second delay section.
20. clock circuit according to claim 19, wherein each postpones time of delay that section caused all about equally.
21. clock circuit according to claim 17 also includes:
One second clock tree is used to provide a second clock signal;
Wherein, utilize this Postponement module to adjust the clock delay time of the one at least between this first clock signal and this second clock signal so that this first with this second clock signal have a given reference phase difference.
22. a related method thereof that is used for a clock circuit, this related method thereof includes:
One first clock signal is provided; And
Utilize a Postponement module to postpone this first clock signal; Wherein, this Postponement module be utilize one time of delay form determine, wherein this Postponement module comprises at least one delayer and at least one connecting line.
23. method according to claim 22, wherein this Postponement module has a time of delay, and this time of delay is corresponding to the driving force of this delayer and the length of this connecting line.
24. method according to claim 22 also includes:
One second clock signal is provided; And
Utilize this Postponement module to adjust the clock delay time of the one at least between this first clock signal and this second clock signal so that this first with this second clock signal have a given reference phase difference.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101607059A CN101958708A (en) | 2009-07-17 | 2009-07-17 | Clock circuit with delay function and related method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101607059A CN101958708A (en) | 2009-07-17 | 2009-07-17 | Clock circuit with delay function and related method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN101958708A true CN101958708A (en) | 2011-01-26 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2009101607059A Pending CN101958708A (en) | 2009-07-17 | 2009-07-17 | Clock circuit with delay function and related method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110865962A (en) * | 2019-10-09 | 2020-03-06 | 北京空间机电研究所 | Dynamically configurable high-precision and high-reliability clock network |
| CN116341481A (en) * | 2023-05-26 | 2023-06-27 | 南京芯驰半导体科技有限公司 | Clock file confirmation method and device, electronic equipment and storage medium |
-
2009
- 2009-07-17 CN CN2009101607059A patent/CN101958708A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110865962A (en) * | 2019-10-09 | 2020-03-06 | 北京空间机电研究所 | Dynamically configurable high-precision and high-reliability clock network |
| CN116341481A (en) * | 2023-05-26 | 2023-06-27 | 南京芯驰半导体科技有限公司 | Clock file confirmation method and device, electronic equipment and storage medium |
| CN116341481B (en) * | 2023-05-26 | 2023-08-22 | 南京芯驰半导体科技有限公司 | Clock file confirmation method and device, electronic equipment and storage medium |
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Application publication date: 20110126 |