CN101944850A - Voltage step-up and down switching power circuit as well as control circuit and method thereof - Google Patents
Voltage step-up and down switching power circuit as well as control circuit and method thereof Download PDFInfo
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Abstract
The invention discloses a voltage step-up and down switching power circuit as well as a control circuit and a method thereof. The power circuit comprises three power switches and a diode or comprises four power switches, wherein the operation of the power switches converts an input voltage into an output voltage. The method comprises: obtaining a feedback signal relevant to the output voltage; comparing the feedback signal with a reference voltage to generate an error amplification signal; when the error amplification signal is between a first voltage and a second voltage, causing the voltage step-up and down switching power circuit to operate in the voltage step down conversion mode; when the error amplification signal is between a third voltage and a fourth voltage, causing the voltage step-up and down switching power circuit to operate in the voltage step up conversion mode; when the error amplification signal is between the second voltage and the third voltage, causing the voltage step-up and down switching power circuit to operate in the voltage step-up and down conversion mode; and operating each power switch at fixed pulse width, wherein the first voltage is less than the second voltage which is less than the third voltage which is less than the fourth voltage.
Description
Technical field
The present invention relates to a kind of buck and switch the formula power circuit, also relate to circuit and method that the control buck is switched the formula power circuit.
Background technology
See also Fig. 1, disclose a kind of method that buck is switched the formula power circuit of controlling in the U.S. Pat 6166527.Buck is switched the formula power circuit and is comprised inductance L, four power switch A, B, C, D, and control circuit 20.Four power switch A of control circuit 20 controls, B, C, the switching of D, input voltage vin is converted to output voltage V out, wherein input voltage vin may be higher or lower than output voltage V out, so power circuit may need to carry out the buck or boost conversion.In the control circuit 20, error amplifier 22 compares feedback signal FB (information of expression output voltage V out) with reference voltage Vref, produce error and amplify signal Vea. PWM comparator 27,28 amplifies signal Vea and voltage waveform VX and VY relatively with this error respectively, and logical circuit 29 produces switch controlling signal VA according to the comparative result of PWM comparator 27,28, VB, VC, VD, difference power controlling switch A, B, C, D.
Error is amplified signal Vea, voltage waveform VX and VY, switch controlling signal VA, VB, VC, the relation of VD as shown in Figure 2, when error was amplified signal Vea and dropped between voltage V1 and the V2, power circuit carried out pure step-down conversion, when error amplification signal Vea drops between voltage V2 and the V3, power circuit carries out the buck conversion, and when error amplification signal Vea dropped between voltage V3 and the V4, power circuit carried out pure boost conversion.Power switch C keeps opening circuit and power switch D keeps conducting when pure step-down translative mode, and power switch A keeps conducting and power switch B keeps opening circuit when pure boost conversion pattern.When the buck translative mode, as shown in the figure, the relativeness of amplifying signal Vea and voltage waveform VX according to error produces switch controlling signal VA, VB, and produce switch controlling signal VC according to the relativeness that error is amplified signal Vea and voltage waveform VY, VD, in other words power circuit (the switch C that boosts, D action) with the married operation of step-down (switch A, B action).
Being characterized as in institute is free of above-mentioned prior art, power switch A, B, C, D all operate in response to feedback signal FB.The shortcoming of this kind arrangement as shown in the figure, when error is amplified signal Vea and only intersected at minimum part with voltage waveform VX, still can produce switch controlling signal VA, VB and make switch A, the B action, but this action will produce switch cost (switchingloss) and energy dissipation is increased; Same situation also can occur in error when amplifying signal Vea and only intersect a little with voltage waveform VY.
Fig. 3 shows the framework of another prior art U.S. Pat 7176667, utilizes error amplifier 22 to produce two grouping errors in this case and amplifies signal Vea1 and Vea2, selects an input PWM comparator 27 and compares with voltage waveform OSC.In addition, a fixed pulse width is set in the circuit in addition produces circuit 25, logical circuit 29 produces switch controlling signal VA according to the output of PWM comparator 27 and the output of fixed pulse width generation circuit 25, VB, VC, VD, difference power controlling switch A, B, C, D.
See also Fig. 4, be divided into four translative mode in the U.S. Pat 7176667, except pure step-down translative mode M1 and pure boost conversion pattern M4, between is provided with step-down translative mode M2 of intermediary and the boost conversion pattern M3 of intermediary in addition, switch controlling signal VA in the step-down translative mode M2 of intermediary, VB follows the output of PWM comparator 27 and switch controlling signal VC, VD is a fixed pulse width, switch controlling signal VC in the step-down translative mode M3 of intermediary, VD follows the output of PWM comparator 27 and switch controlling signal VA, and VB is a fixed pulse width.
The shortcoming of above-mentioned prior art is, the controlling mechanism of four translative mode is comparatively complicated, fixed pulse width need be set in addition produce circuit 25 and other circuit element, and two intermediary's translative mode (M2 and M3) indication circuit operates in this interval chance to be increased, and four power switchs all move in intermediary's translative mode, increase switch cost and energy dissipation.
In view of this, the present invention is promptly at above-mentioned the deficiencies in the prior art, propose a kind of buck switch the formula power circuit with its control circuit and method, to reduce the energy conversion efficiency of switch cost and energy dissipation, raising power circuit.
Summary of the invention
One of the object of the invention is to overcome the deficiencies in the prior art and defective, proposes a kind of buck and switches the formula power circuit.
Another object of the present invention is to, propose a kind of circuit that buck is switched the formula power circuit of controlling.
Another object of the present invention is to, propose a kind of method that buck is switched the formula power circuit of controlling.
For reaching above-mentioned purpose, with regard to one of them viewpoint speech, the invention provides a kind of buck and switch the formula power circuit, comprise: an inductance has first end and second end; First power switch, first end of one end and this inductance couples, and its other end and an input voltage couple; Second power switch, first end of one end and this inductance couples, its other end ground connection; The 3rd power switch, second end of one end and this inductance couples, its other end ground connection; The 4th power switch, first end of one end and this inductance couples, and its other end and an output voltage couple; And a control circuit, control the operation of above four power switchs, make: when (1) this buck was switched formula power circuit and operated on the step-down translative mode, this first and second power switch carried out handover operation and the 3rd and the 4th power switch is failure to actuate; When (2) this buck was switched formula power circuit and operated on the boost conversion pattern, the 3rd and the 4th power switch carried out handover operation and this first and second power switch is failure to actuate; And when (3) this buck switching formula power circuit operated on the buck translative mode, this first and second power switch was with fixing first pulsewidth operation, and the 3rd and the 4th power switch is with fixing second pulsewidth operation.
Above-mentioned buck is switched in the formula power circuit, and the second or the 4th power switch can change and be diode.
Above-mentioned buck is switched the control circuit in the formula power circuit, also can comprise: an error amplifier, the feedback signal relevant with output voltage compared with a reference voltage; First waveform generator, produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between first voltage (V1) and second voltage (V2) maintains the tertiary voltage horizontal segment of (V3) a period of time, and is positioned at the vertical section at horizontal segment two ends; Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: maintains second voltage horizontal segment of (V2) a period of time, is positioned at the vertical section at horizontal segment two ends, and at least one the slope section between tertiary voltage (V3) and the 4th voltage (V4); V1＜V2＜V3＜V4 wherein; The first and second PWM comparators are compared the output of error amplifier respectively with first waveform and second waveform; And a logical circuit, its output according to the first and second PWM comparators produces controlling signal, the power controlling switch.
For reaching above-mentioned purpose, with regard to another viewpoint speech, the invention provides a kind of circuit that buck is switched the formula power circuit of controlling, this buck is switched the formula power circuit one input voltage is converted to an output voltage, this control circuit comprises: an error amplifier, the feedback signal relevant with output voltage compared with a reference voltage; First waveform generator, produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between first voltage (V1) and second voltage (V2) maintains the tertiary voltage horizontal segment of (V3) a period of time, and is positioned at the vertical section at horizontal segment two ends; Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: maintains second voltage horizontal segment of (V2) a period of time, is positioned at the vertical section at horizontal segment two ends, and at least one the slope section between tertiary voltage (V3) and the 4th voltage (V4); V1＜V2＜V3＜V4 wherein; The first and second PWM comparators are compared the output of error amplifier respectively with first waveform and second waveform; And a logical circuit, its output according to the first and second PWM comparators produces controlling signal.
For reaching above-mentioned purpose, just another viewpoint is sayed again, the invention provides a kind of buck and switch the control method of formula power circuit, this buck is switched the formula power circuit and is comprised three power switchs and a diode or comprise four power switchs, operation by power switch is converted to an output voltage with an input voltage, and this control method comprises: obtain the feedback signal relevant with output voltage; This feedback signal is compared with a reference voltage, produce error and amplify signal; When this error amplification signal is between first voltage and second voltage, makes this buck switch formula power circuit and operate on the step-down translative mode; When this error amplification signal is between tertiary voltage and the 4th voltage, makes this buck switch formula power circuit and operate on the boost conversion pattern; And when this error amplification signal is between second voltage and tertiary voltage, make this buck switch the formula power circuit and operate on the buck translative mode, and make each power switch respectively with fixing pulsewidth operation, wherein first voltage＜second voltage＜tertiary voltage＜the 4th voltage.
In control circuit in above-mentioned buck switching formula power circuit, the buck switching formula power circuit, the control method in the buck switching formula power circuit, should make (tertiary voltage-second voltage)＜(the 4th voltage-tertiary voltage) and (tertiary voltage-second voltage)＜(second voltage-first voltage).
Illustrate in detail below by specific embodiment, when the effect that is easier to understand purpose of the present invention, technology contents, characteristics and is reached.
Description of drawings
Fig. 1 marks a kind of buck switching formula power circuit of prior art;
Fig. 2 is the waveform corresponding to Fig. 1 circuit;
Fig. 3 marks the buck switching formula power circuit of another kind of prior art;
Fig. 4 is corresponding to the state transition table of Fig. 3 circuit (state machine);
Fig. 5 shows the embodiment of buck switching formula power circuit of the present invention;
Fig. 6 and Fig. 7 illustrate the effect of waveform RX and RY;
Fig. 8-10 explanation the present invention in step-down, boost, the operational scenario under the buck translative mode;
An execution mode of Figure 11 A-11C display waveform RX generator 23;
An execution mode of Figure 12 A-12C display waveform RY generator 24;
Another execution mode of Figure 13 A-13C display waveform RX generator 23;
Another execution mode of Figure 14 display waveform RX generator 23;
Several execution modes of Figure 15-17 display waveform RY generator 24;
Figure 18-19 explanation the present invention can be applicable to half synchronization lifting and presses the suitching type power circuit;
Other embodiment of Figure 20-22 display waveform RX and waveform RY.
Symbol description among the figure
20 control circuits
22 error amplifiers
23 waveform RX generators
24 waveform RY generators
25 fixed pulse width produce circuit
27, the 28PWM comparator
29 logical circuits
30 control circuits
70,80 line segments (illustrate and use)
A, B, C, D power switch
C1 electric capacity
The FB feedback signal
The i current source
The L inductance
OSC shakes waveform
T1, the T2 period
R resistance
RX, the RY voltage waveform
V1, V2, V3, V4, V2 ', V3 ' waveform RY generator voltage level
VA, VB, VC, VD switch controlling signal
VX, the VY triangular waveform
Vea, Vea1, the Vea2 error is amplified signal
The Vin input voltage
The Vout output voltage
The Vr reference voltage
The Vref reference voltage
The Vs voltage source
Z1, the Z2 zone
Ax, bx, cx, ay, by, cy waveform segment
Embodiment
Please refer to Fig. 5, wherein show first embodiment of the present invention.Buck is switched the formula power circuit and is comprised inductance L, four power switch A, B, C, D, and control circuit 30.Four power switch A of control circuit 30 controls, B, C, the switching of D is to be converted to input voltage vin output voltage V out.In the control circuit 30, error amplifier 22 compares feedback signal FB (information of expression output voltage V out) with reference voltage Vref, produce error and amplify signal Vea.Waveform RX generator 23 and waveform RY generator 24 produce waveform RX and RY respectively; PWM comparator 27,28 amplifies signal Vea and voltage waveform RX and RY relatively with this error respectively.Logical circuit 29 produces switch controlling signal VA according to the comparative result of PWM comparator 27,28, VB, VC, VD, difference power controlling switch A, B, C, D.
See also Fig. 6, one of characteristics of the present invention are waveform RX and the RY that waveform generator 23 and waveform generator 24 are produced.Waveform RX and RY are not simple triangular wave or sawtooth waveform, as shown in the figure, have special region Z1 and Z2 respectively in waveform RX and RY.In detail, in each cycle, waveform RX begins to rise from voltage V1, arrive voltage V2 after, promptly jump and maintain voltage V3, when end cycle, be returned to voltage V1 again.Waveform RY then begins from voltage V2, keeps to jump after a period of time to voltage V3 and rise, up to arriving voltage V4.In other words waveform RX comprises following wave band at least in each cycle: at least one the slope section ax between voltage V1 and voltage V2 maintains the horizontal segment bx of voltage V3 a period of time, and is positioned at the vertical section cx at horizontal segment two ends; And waveform RY comprises following wave band at least in each cycle: maintain the horizontal segment ay of voltage V2 a period of time, and at least one the slope section by between voltage V3 and voltage V4, and be positioned at the vertical section cy at horizontal segment two ends; V1＜V2＜V3＜V4 wherein.Except that These characteristics, according to the present invention, the gap Δ V between voltage V2 and the voltage V3 should be as much as possible little, that is (V3-V2)＜(V4-V3) and (V3-V2)＜(V2-V1).
The effect of above special region Z1 and Z2, and should make Δ V as much as possible little why, be described as follows.See also Fig. 7, when error amplification signal Vea drops between voltage V1 and the V2, power circuit carries out pure step-down conversion, when error amplification signal Vea drops between voltage V2 and the V3, power circuit carries out the buck conversion, when error amplification signal Vea dropped between voltage V3 and the V4, power circuit carried out pure boost conversion.As shown in the figure when error amplification signal Vea drops between voltage V2 and the V3, please note regional Z1 earlier, if waveform RX is simple triangular wave or sawtooth waveform, then the intersection point of error amplification signal Vea and sawtooth waveforms will be positioned on the line segment 70, and the rising edge of the falling edge of switch controlling signal VA and switch controlling signal VB also will be positioned on the line segment 70.Though error amplification this moment signal Vea only intersects a little with sawtooth waveforms, switch controlling signal VA, VB still can make switch A, and the B action causes switch cost.In like manner please note regional Z2 and line segment 80, if waveform RY is simple triangular wave or sawtooth waveform, then when error is amplified signal Vea and is only intersected a little with voltage waveform RY, switch controlling signal VC, VD still can make switch C, and the D action causes switch cost.Yet according to the present invention, waveform RX and RY are not simple triangular wave or sawtooth waveform, therefore crossing a little situation can not appear, the minimum ON time of the minimum shut-in time of switch controlling signal VA and switch controlling signal VB is w1, and the minimum shut-in time of the minimum ON time of switch controlling signal VC and switch controlling signal VD is w2, and wherein w1 can equate with w2 or not wait.In other words when error is amplified signal Vea and dropped among regional Z1 and the Z2, no matter the position standard that error is amplified signal Vea is how, all power switchs of power circuit are all with fixing minimum pulsewidth operation, so can avoid power switch constantly a little switching cause power consumption.This also means, when power circuit operates in the buck translative mode, and power switch A, B, C, the position of the operation of D and output voltage V out or feedback signal FB is accurate irrelevant, that is feedback regulation output voltage not, so power circuit should not often be operated or stay in the buck translative mode.According to the present invention, difference DELTA V between voltage V2 and the V3 is little far beyond prior art U.S. Pat 6166527, so power circuit of the present invention is less to be entered in the buck translative mode, can not stay in wherein (giving detailed description again) too for a long time with reference to Figure 10 in case enter yet.
Fig. 8 display error amplification signal Vea drops on the situation between voltage V1 and the V2, this moment, power circuit carried out pure step-down conversion, power switch C keeps opening circuit and power switch D maintenance conducting, control circuit 30 produces switch controlling signal VA according to feedback signal FB, VB, to switch A, B carries out FEEDBACK CONTROL.Fig. 9 display error amplification signal Vea drops on the situation between voltage V3 and the V4, this moment, power circuit carried out pure boost conversion, power switch A keeps conducting and power switch B keeps opening circuit, control circuit 30 produces switch controlling signal VC according to feedback signal FB, VD, to switch C, D carries out FEEDBACK CONTROL.
See also Figure 10, because the interval between voltage V2 and the voltage V3 is little, and when power circuit operates in the buck translative mode, power switch A, B, C, D is all with fixing minimum pulsewidth operation, therefore in case power circuit enters the buck translative mode, promptly can break away from once, enter boost or the step-down translative mode in.For example as shown in the figure, suppose that power circuit operates in the step-down translative mode originally, but when input voltage vin descends or other reason when causing error to amplify signal Vea to rise, power circuit enters buck translative mode (period T1), and this moment is because power switch A, B, C, D be all with fixing minimum pulsewidth operation, its to the power of output voltage V out supply greater than required, therefore error amplification signal Vea will descend rapidly, so power circuit is got back to step-down translative mode (period T2) rapidly.Voltage V2 ' and voltage V3 ' are the imaginary line corresponding to voltage V2 in the U.S. Pat 6166527 and voltage V3 among the figure, the operation in the buck translative mode in the whole operations of Figure 10 of the present invention and the U.S. Pat 6166527 can be contrasted.Period T1 and period T2 comprise two cycles in the example shown in Figure 10, and switch C, D only moves once, (period T1 and period T2 may comprise the more multicycle in the actual conditions to have the effect of frequency hopping (pulse-skipping), so the effect of frequency hopping will be more remarkable), will reduce the switch switch cost and make energy conversion efficiency better.
Waveform RX and waveform RY have several different methods to produce, and the present invention is not limited to wherein any execution mode.Below will illustrate wherein several, but to those skilled in the art, and after teaching of the present invention, should not have difficulty and analogize and think and various other variation.
Figure 11 A-11C marks wherein a kind of execution mode of waveform RX generator 23, the cycle of waveform RX is determined by time pulse signal CLK, power circuit produces one according to time pulse signal CLK and postpones signal (CLK+ delay), and its rising edge and time pulse signal CLK are synchronous but falling edge lags behind the falling edge of time pulse signal CLK.Postpone signal (CLK+ delay) according to this, current source i obtains first section waveform shown in Figure 11 A to capacitor C 1 charging when the cycle begins; When arrive postponing the falling edge of signal, RX changes and is connected in voltage V3, and capacitor C 1 discharge, second section waveform shown in the pie graph 11B; At last, end cycle, next cycle begins, and forms the 3rd section waveform shown in Figure 11 C.
Similarly, Figure 12 A-12C marks wherein a kind of execution mode of waveform RY generator 24, the cycle of waveform RY is determined by time pulse signal CLK, power circuit produces one according to time pulse signal CLK and postpones signal (CLK+ delay), and its rising edge and time pulse signal CLK are synchronous but falling edge lags behind the falling edge of time pulse signal CLK.Postpone signal (CLK+ delay) according to this, RY is connected in voltage V2 when the cycle begins, and capacitor C 1 discharge, obtains first section waveform shown in Figure 12 A; When arrive postponing the falling edge of signal, RY changes and is connected in capacitor C 1, and current source i is to capacitor C 1 charging, second section waveform shown in the pie graph 12B (lower end of capacitor C 1 is voltage V3); At last, end cycle, next cycle begins, and forms the 3rd section waveform shown in Figure 12 C.
Above Figure 11 A-11C and Figure 12 A-12C mode need produce the delay signal, and Figure 13 A-13C illustration does not need to utilize the mode that signal produces waveform RX that postpones.In phase I in cycle, current source i obtains first section waveform as shown in FIG. 13A to capacitor C 1 charging; When the voltage of capacitor C 1 upper end arrived voltage V2, the output of comparator changed RX and is connected in voltage V3 (voltage V3 is from ixR in this example), second section waveform shown in the pie graph 13B; At last, end cycle, time pulse signal CLK make capacitor C 1 discharge, and the output transform state of comparator changes RX and is connected in capacitor C 1, forms the 3rd section waveform shown in Figure 13 C.
The another kind of mode that produces waveform RX of Figure 14 illustration wherein changes resistance R into and capacitor C 1 polyphone, ixR=V3-V2 in this example.
Figure 15-17 shows does not respectively need to utilize the delay signal to produce several embodiment of waveform RY, among these embodiment is to utilize current source i to be controlled the time of first section waveform the time of capacitor C 1 charging.The waveform RY that each embodiment produced, the relativeness of its regional Z2 and slope section is slightly variant, also can adapt to various V2, V3, the setting of V4.Vs is a voltage source among Figure 17, and its magnitude of voltage is Vr-V3, and wherein Vr is any reference voltage, that is when the voltage of capacitor C 1 upper end arrives voltage V3, and the output transform state of comparator changes RY to be connected in the polyphone path of current source i and capacitor C 1.
More than to press the suitching type power circuit with the synchronization lifting with four power switchs be that example is illustrated, but the present invention is not limited thereto; Shown in Figure 18 and 19, the present invention also can be applicable to half synchronization lifting with three power switchs and presses in the suitching type power circuit.The step-down of the circuit of Figure 18, boost, the switch controlling signal of buck pattern is similar to Fig. 8-10, but do not need switch controlling signal VD; The step-down of the circuit of Figure 19, boost, the switch controlling signal of buck pattern is also similar to Fig. 8-10, but do not need switch controlling signal VB.
In addition, waveform RX and waveform RY are not limited to the sawtooth waveform shown in Fig. 6-10, and for example also can be the waveform shown in Figure 20-22, or the like.Waveform shown in Fig. 6-10 and Figure 20-22 all has following feature: waveform RX comprises in each cycle at least: at least one the slope section ax between voltage V1 and voltage V2, maintain the horizontal segment bx of voltage V3 a period of time, and be positioned at the vertical section cx at horizontal segment two ends; And waveform RY comprises following wave band at least in each cycle: maintain the horizontal segment ay of voltage V2 a period of time, and at least one the slope section by between voltage V3 and voltage V4, and be positioned at the vertical section cy at horizontal segment two ends.
Below at preferred embodiment the present invention is described, just the above for making those skilled in the art be easy to understand content of the present invention, is not to be used for limiting interest field of the present invention only.Under same spirit of the present invention, those skilled in the art can think and various equivalence changes.For example, power switch can also can be PMOSFET for NMOSFET, only needs alteration switch controlling signal VA, VB, VC, the phase place of VD.And for example, among Fig. 6-10 and Figure 20,21 the waveform RX, remove wave band ax, bx and cx still can add other wave band outward, and among the waveform RY, remove wave band ay, and by and cy still can add other wave band outward.Therefore, scope of the present invention should contain above-mentioned and other all equivalence variations.
Claims (16)
1. a buck is switched the formula power circuit, it is characterized in that, comprises:
One inductance has first end and second end;
First power switch, first end of one end and this inductance couples, and its other end and an input voltage couple;
Second power switch, first end of one end and this inductance couples, its other end ground connection;
The 3rd power switch, second end of one end and this inductance couples, its other end ground connection;
The 4th power switch, first end of one end and this inductance couples, and its other end and an output voltage couple; And
One control circuit is controlled the operation of above four power switchs, makes:
When this buck was switched formula power circuit and operated on the step-down translative mode, this first and second power switch carried out handover operation and the 3rd and the 4th power switch is failure to actuate;
When this buck was switched formula power circuit and operated on the boost conversion pattern, the 3rd and the 4th power switch carried out handover operation and this first and second power switch is failure to actuate; And
When this buck switching formula power circuit operated on the buck translative mode, this first and second power switch was with fixing first pulsewidth operation, and the 3rd and the 4th power switch is with fixing second pulsewidth operation.
2. buck as claimed in claim 1 is switched the formula power circuit, and wherein, this control circuit comprises:
One error amplifier is compared the feedback signal relevant with output voltage with a reference voltage;
First waveform generator, produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between the first voltage V1 and the second voltage V2 maintains the horizontal segment of tertiary voltage V3 a period of time, and is positioned at the vertical section at horizontal segment two ends;
Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: the horizontal segment that maintained for second voltage V2 a period of time, at least one slope section between tertiary voltage V3 and the 4th voltage V4, and be positioned at the vertical section at horizontal segment two ends, wherein V1＜V2＜V3＜V4;
The first and second PWM comparators are compared the output of error amplifier respectively with first waveform and second waveform; And
One logical circuit, its output according to the first and second PWM comparators produces controlling signal, control first, second, third, with the 4th power switch.
3. buck as claimed in claim 2 is switched the formula power circuit, wherein, and (V3-V2)＜(V4-V3) and (V3-V2)＜(V2-V 1).
4. a buck is switched the formula power circuit, it is characterized in that, comprises:
One inductance has first end and second end;
First power switch, first end of one end and this inductance couples, and its other end and an input voltage couple;
Second power switch, first end of one end and this inductance couples, its other end ground connection;
The 3rd power switch, second end of one end and this inductance couples, its other end ground connection;
Diode, first end of one end and this inductance couples, and its other end and an output voltage couple; And
One control circuit, control first, second, with the operation of the 3rd power switch, make:
When this buck was switched formula power circuit and operated on the step-down translative mode, this first and second power switch carried out handover operation and the 3rd power switch is failure to actuate;
When this buck was switched formula power circuit and operated on the boost conversion pattern, the 3rd power switch carried out handover operation and this first and second power switch is failure to actuate; And
When this buck switching formula power circuit operated on the buck translative mode, this first and second power switch was with fixing first pulsewidth operation, and the 3rd power switch is with fixing second pulsewidth operation.
5. buck as claimed in claim 4 is switched the formula power circuit, and wherein, this control circuit comprises:
One error amplifier is compared the feedback signal relevant with output voltage with a reference voltage;
First waveform generator, produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between the first voltage V1 and the second voltage V2 maintains the horizontal segment of tertiary voltage V3 a period of time, and is positioned at the vertical section at horizontal segment two ends;
Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: the horizontal segment that maintained for second voltage V2 a period of time, at least one slope section between tertiary voltage V3 and the 4th voltage V4, and be positioned at the vertical section at horizontal segment two ends, wherein V1＜V2＜V3＜V4;
The first and second PWM comparators are compared the output of error amplifier respectively with first waveform and second waveform; And
One logical circuit, its output according to the first and second PWM comparators produces controlling signal, control first, second, with the 3rd power switch.
6. buck as claimed in claim 5 is switched the formula power circuit, wherein, and (V3-V2)＜(V4-V3) and (V3-V2)＜(V2-V 1).
7. a buck is switched the formula power circuit, it is characterized in that, comprises:
One inductance has first end and second end;
First power switch, first end of one end and this inductance couples, and its other end and an input voltage couple;
Diode, first end of one end and this inductance couples, its other end ground connection;
Second power switch, second end of one end and this inductance couples, its other end ground connection;
The 3rd power switch, first end of one end and this inductance couples, and its other end and an output voltage couple; And
One control circuit, control first, second, with the operation of the 3rd power switch, make:
When this buck was switched formula power circuit and operated on the step-down translative mode, this first power switch carried out handover operation and this second and the 3rd power switch is failure to actuate;
When this buck was switched formula power circuit and operated on the boost conversion pattern, this second and the 3rd power switch carried out handover operation and this first power switch is failure to actuate; And
When this buck switching formula power circuit operated on the buck translative mode, this first power switch was with fixing first pulsewidth operation, and this second and the 3rd power switch is with fixing second pulsewidth operation.
8. buck as claimed in claim 7 is switched the formula power circuit, and wherein, this control circuit comprises:
One error amplifier is compared the feedback signal relevant with output voltage with a reference voltage;
First waveform generator, produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between the first voltage V1 and the second voltage V2 maintains the horizontal segment of tertiary voltage V3 a period of time, and is positioned at the vertical section at horizontal segment two ends;
Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: the horizontal segment that maintained for second voltage V2 a period of time, at least one slope section between tertiary voltage V3 and the 4th voltage V4, and be positioned at the vertical section at horizontal segment two ends, wherein V1＜V2＜V3＜V4;
The first and second PWM comparators are compared the output of error amplifier respectively with first waveform and second waveform; And
One logical circuit, its output according to the first and second PWM comparators produces controlling signal, control first, second, with the 3rd power switch.
9. buck as claimed in claim 8 is switched the formula power circuit, wherein, and (V3-V2)＜(V4-V3) and (V3-V2)＜(V2-V1).
10. a buck is switched the control circuit of formula power circuit, and this buck is switched formula power circuit one input voltage is converted to an output voltage, it is characterized in that this control circuit comprises:
One error amplifier is compared the feedback signal relevant with output voltage with a reference voltage;
First waveform generator, produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between the first voltage V1 and the second voltage V2 maintains the horizontal segment of tertiary voltage V3 a period of time, and is positioned at the vertical section at horizontal segment two ends;
Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: the horizontal segment that maintained for second voltage V2 a period of time, at least one slope section between tertiary voltage V3 and the 4th voltage V4, and be positioned at the vertical section at horizontal segment two ends, wherein V1＜V2＜V3＜V4;
The first and second PWM comparators are compared the output of error amplifier respectively with first waveform and second waveform; And
One logical circuit, its output according to the first and second PWM comparators produces controlling signal, controls this buck and switches the formula power circuit.
11. buck as claimed in claim 10 is switched the control circuit of formula power circuit, wherein, this buck is switched the formula power circuit and is comprised four power switchs, and four controlling signal of this logical circuit generation, to control this four power switchs respectively.
12. buck as claimed in claim 10 is switched the control circuit of formula power circuit, wherein, this buck is switched the formula power circuit and is comprised three power switchs, and three controlling signal of this logical circuit generation, to control this three power switchs respectively.
13. buck as claimed in claim 10 is switched the control circuit of formula power circuit, wherein, and (V3-V2)＜(V4-V3) and (V3-V2)＜(V2-V1).
14. a buck is switched the control method of formula power circuit, this buck is switched the formula power circuit and is comprised three power switchs and a diode or comprise four power switchs, operation by power switch is converted to an output voltage with an input voltage, it is characterized in that this control method comprises:
Obtain the feedback signal relevant with output voltage;
This feedback signal is compared with a reference voltage, produce error and amplify signal;
When this error amplification signal is between the first voltage V1 and the second voltage V2, makes this buck switch formula power circuit and operate on the step-down translative mode;
When this error amplification signal is between tertiary voltage V3 and the 4th voltage V4, makes this buck switch formula power circuit and operate on the boost conversion pattern; And
When this error amplification signal is between the second voltage V2 and tertiary voltage V3, makes this buck switch formula power circuit and operate on the buck translative mode, and make each power switch respectively with fixing pulsewidth operation, wherein V1＜V2＜V3＜V4.
15. buck as claimed in claim 14 is switched the control method of formula power circuit, wherein, and (V3-V2)＜(V4-V3) and (V3-V2)＜(V2-V1).
16. buck as claimed in claim 14 is switched the control method of formula power circuit, wherein, also comprises:
Produce first waveform, this waveform comprises following wave band at least in each cycle: at least one the slope section between the first voltage V1 and the second voltage V2 maintains the horizontal segment of tertiary voltage V3 a period of time, and is positioned at the vertical section at horizontal segment two ends;
Second waveform generator, produce second waveform, this waveform comprises following wave band at least in each cycle: the horizontal segment that maintained for second voltage V2 a period of time, at least one slope section between tertiary voltage V3 and the 4th voltage V4, and be positioned at the vertical section at horizontal segment two ends, wherein V1＜V2＜V3＜V4; And
With the error amplifier signal with first waveform and second waveform are compared respectively.
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| CN 200910149585 CN101944850B (en) | 2009-07-06 | 2009-07-06 | Voltage step-up and down switching power circuit as well as control circuit and method thereof |
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| CN 200910149585 CN101944850B (en) | 2009-07-06 | 2009-07-06 | Voltage step-up and down switching power circuit as well as control circuit and method thereof |
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| CN101944850B CN101944850B (en) | 2013-07-31 |
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