CN101944314B - Pattern generator, pattern data updating system and pattern data updating method - Google Patents
Pattern generator, pattern data updating system and pattern data updating method Download PDFInfo
- Publication number
- CN101944314B CN101944314B CN2009100886454A CN200910088645A CN101944314B CN 101944314 B CN101944314 B CN 101944314B CN 2009100886454 A CN2009100886454 A CN 2009100886454A CN 200910088645 A CN200910088645 A CN 200910088645A CN 101944314 B CN101944314 B CN 101944314B
- Authority
- CN
- China
- Prior art keywords
- unit
- radio frequency
- frequency units
- resolution chart
- zone bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Mobile Radio Communication Systems (AREA)
Abstract
The invention discloses a pattern generator, a pattern data updating system and a pattern data updating method. A main function module of the pattern generator comprises a radio frequency function unit for establishing communication linkages among multiple pattern generators. The pattern data updating system comprises the pattern generator with a radio frequency function, a pattern data transmission device and a wireless router, and achieves automatic updating of the pattern generator by using a wireless network. The pattern data updating method comprises the following steps: a CPU detects that updated bit zones exist in the radio frequency unit; under the control of the CPU, the radio frequency unit transmits the received test pattern data and the bit zones to a random storage unit; and the random storage unit downloads the stored test pattern data thereof to an FPGA unit, and stores the test pattern data and the bit zones to a nonvolatile storage unit to serve as a backup.
Description
Technical field
The present invention relates to a kind of liquid crystal panel testing fixture, particularly a kind of pattern generator, graph data update system and graph data update method.Belong to the LCD detection range.
Background technology
Pattern generator (Pattern Generator; Hereinafter to be referred as PG) be to be used for utilizing after liquid crystal panel is lighted display graphics to detect the device of the necessary use of defective institute that panel itself exists; The resolution chart data that the external graphics compiler generates are as the test signal of this PG of input, and wherein the attribute of resolution chart data comprises systematic parameter (like program name, storage format, read type etc.), liquid crystal panel parameter (like resolution, dominant frequency, Pixel Dimensions etc.) and the analog parameter (like voltage) etc. of test pattern.PG is through handling the resolution chart data of input; With each Parameters Transformation that comprises in the above-mentioned attribute is the signal that liquid crystal panel can receive; Finally on liquid crystal panel, show with graphics mode; Carry out the detection of graphic feature again, in order to the defective (like bad point) on the judgement liquid crystal panel and the grade of defective etc.
Fig. 1 is the structural representation of existing pattern generator.As shown in Figure 1, PG is made up of three big functional modules, comprising: (Signal Generator takes place in main functional modules 11, power module 12 and signal; Hereinafter to be referred as SG) module 13.The resolution chart data are through the peripheral I/O (Input/Output in the main functional modules 11; Hereinafter to be referred as I/O) unit 111 is input to main functional modules 11, at CPU (Central Processing Unit; Hereinafter to be referred as CPU) the resolution chart data are sent to storage unit 114 under 112 the control, store by this storage unit 114, and utilize field programmable gate array (Field Programmable Gate Array; Hereinafter to be referred as FPGA) unit 113 changes the various sequential control parameters that comprise in the resolution chart data into transistor-transistor logic level (Transistor-Transistor Logic; Hereinafter to be referred as TTL) signal is sent to SG module 13.SG module 13 receives the TTL signal transition for suitable liquid crystal panel Low Voltage Differential Signal (LowVoltage Differential Signaling; Hereinafter to be referred as LVDS) output; Simultaneously the voltage parameter that comprises in the resolution chart data is exported to power module 12.Power module 12 changes the input of conventional voltage into the predeterminated voltage value, like backlight voltage etc., is each chip power supply in the PG.
At present, the resolution chart data of graphical compiler output generally are kept on the PCWCIA storage card.PCMCIA, full name are Personal Computer Memory Card InternationalAssociation, are a kind of interface specifications that is used in specially on the portable equipments such as notebook, PDA or digital camera.When the resolution chart data among the PG need be upgraded; The PCWCIA storage card that stores the resolution chart data after the renewal is inserted the PCWCIA slot of PG, can the resolution chart data in the PCWCIA storage card be downloaded in the FPGA unit 113 among this PG after the PG start.
Because existing P G is single cpu mode; Be not have communication between a plurality of PG each other to connect; And the defective that said storage unit among the PG and FPGA unit all exist outage back information all to lose; Therefore every PG will be equipped with the PCWCIA storage card separately, so that when the PG power-off restarting, load required resolution chart data.This makes the resolution chart updating data on single PG, to carry out, thereby causes the loss of manpower and time cost.
Summary of the invention
The objective of the invention is for a kind of pattern generator, graph data update system and graph data update method are provided; Need load the shortcoming of required resolution chart data when restarting after pattern generator cuts off the power supply one by one to overcome; Thereby the operation of graphic simplicity generator is increased work efficiency.
To achieve these goals; The embodiment of the invention provides a kind of pattern generator; Comprise signal generating module, power module and the main functional modules that is connected with power module with said signal generating module, said main functional modules comprises central processing unit CPU, on-site programmable gate array FPGA unit, random memory unit and peripheral I/O unit; It is characterized in that said main functional modules also comprises:
Radio frequency units links to each other with random memory unit with said CPU, is used for acceptance test graph data and zone bit, and according to the data transfer instruction of said CPU said resolution chart data and zone bit is sent to said random memory unit.
The embodiment of the invention is added the less radio-frequency function in PG, for setting up communication link between many PG, having solved needs the separate unit operation, the defective that can't carry out overall situation control to a plurality of PG when PG upgrades required resolution chart data.
Another purpose of the present invention is in order a kind of graph data update system to be provided, a plurality of PG to be controlled by the overall situation in a LAN.
To achieve these goals, the embodiment of the invention also provides a kind of graph data update system, comprises a plurality of said pattern generators, also comprises graph data transmitting apparatus and wireless router, wherein:
Said wireless router is used for the address to said pattern generator dynamic assignment IP;
Said graph data transmitting apparatus is used for transmitting the resolution chart data of upgrading to the pattern generator of assigned ip address.
The embodiment of the invention is set up communication link between a plurality of PG, the graph data transmitting apparatus sends the resolution chart data of renewal according to the wireless router IP address allocated for the PG of assigned ip address.Through the control of LAN, simplified a plurality of PG updating steps, improved the dirigibility that a plurality of PG upgrade.
A further object of the present invention is for a kind of graph data update method is provided, and concrete steps comprise:
Step 1, pattern generator are normally in service, and the central processing unit CPU of said pattern generator detects radio frequency units and receives the updating mark position;
Step 2, send first data transfer instruction, control said radio frequency units and send resolution chart data and said zone bit to random memory unit to said radio frequency units;
Step 3, send download instruction, control said random memory unit said resolution chart data are downloaded in the on-site programmable gate array FPGA unit to said random memory unit.
The resolution chart data that the embodiment of the invention can utilize the radio frequency units automatic reception to upgrade solve the shortcoming that takes time and effort that the artificial ROMPaq of PG separate unit brings.
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
Description of drawings
Fig. 1 is the structural representation of existing pattern generator;
Fig. 2 is the structural representation of first embodiment of pattern generator of the present invention;
Fig. 3 is the structural representation of second embodiment of pattern generator of the present invention;
Fig. 4 is the structural representation of the 3rd embodiment of pattern generator of the present invention;
Fig. 5 is judgement unit workflow synoptic diagram among the 3rd embodiment of pattern generator of the present invention;
Fig. 6 is the structural representation of the embodiment of graph data update system of the present invention;
Fig. 7 is the method flow synoptic diagram of first embodiment of graph data update method of the present invention;
Fig. 8 is the normal runtime data update method of a PG schematic flow sheet among first embodiment of graph data update method;
Fig. 9 is the method flow synoptic diagram of second embodiment of graph data update method of the present invention;
Figure 10 is the normal runtime data update method of a PG schematic flow sheet among second embodiment of graph data update method.
Embodiment
Fig. 2 is the structural representation of first embodiment of pattern generator of the present invention.As shown in Figure 2, said PG is made up of main functional modules 21, power module 22 and SG module 23 3 parts.Said main functional modules 21 links to each other with power module 22 with said SG module 23.The main functional modules 21 of said PG comprises peripheral I/O unit 211, CPU212, FPGA unit 213, random memory unit 214 and radio frequency units 215.
In main functional modules 21, increase radio frequency units 215, link to each other with random memory unit 214 with CPU212.Said radio frequency units 215 adopts the single-chip solution; Chip operation is on 2.4GHz; Adopt IEEE 802.11b/g standard; Be used for acceptance test graph data and zone bit, and resolution chart data and zone bit be sent in the random memory unit 214 according to the data transfer instruction of CPU212.In the present embodiment, peripheral I/O unit 211 includes controller, mouse, and USB interface, interfaces such as PCWCIA storage card slot are connected with CPU212, are used to utilize PCWCIA storage card or USB flash disk to load the resolution chart data for PG.
Specifically set forth in the face of the principle of work of PG shown in Figure 2 down.When PG normal in service or normal boot-strap or power-off restarting; CPU212 assigns data transfer instruction to radio frequency units 215; Radio frequency units 215 is sent in the random memory unit 214 resolution chart data that receive and zone bit temporary under the control of this instruction.In the present embodiment, random memory unit 214 is a synchronous dynamic RAM (Synchronous DRAM; Hereinafter to be referred as SDRAM), SDRAM is made up of static asynchronous circuit fully, need not input clock signal; Also needn't refresh chip; Can directly cover gibberish, in case be characterized in outage, storage information above that will all disappear and can't recover.The capacity of SDRAM is 128Mb, enough stores 10 groups of above resolution chart data.After the temporary completion of buffering; CPU212 sends download instruction to SDRAM; The resolution chart data that buffering is temporary among the SDRAM download in the FPGA unit 213; Utilize circuit structure to realize the sequential control parameter that comprises in the resolution chart data through FPGA unit 213, after the configuration of completion controlled variable data output is passed to SG module 23 and power module 22.Power module 22 is system's power supply, and SG module 23 is the receivable signal of liquid crystal panel with the data-switching of main functional modules 21 outputs, finally on panel, shows with graphics mode, and the characteristic through test pattern is to judge liquid crystal panel defective and grade.In the present embodiment, FPGA unit 213 uses the Virtex-II series of Xilinx company, and the logic gate of this Series FPGA and I/O interface are extremely abundant, support most popular I/O interface standards.
Present embodiment is through adding radio frequency units 215 in the main functional modules 21 of PG; Make PG needn't use the manual work of PCWICA storage card to carry out the resolution chart Data Update of unit, can utilize the radio frequency units 215 automatic also resolution chart data of down loading updating that detect among the PG.And in the present embodiment, can make resource realization on central processing unit and the partial logic unit by using FPGA sheet, reduce PCB layout complexity through using high performance fpga chip.In the present embodiment, less radio-frequency functional unit 215 also can be bluetooth (Bluetooth), and infrared grade possesses the integrated circuit or the combinational circuit of wireless transmission merit.
Fig. 3 is the structural representation of second embodiment of pattern generator of the present invention.As shown in Figure 3, said PG is made up of main functional modules 31, power module 32 and SG module 33 3 parts.The main functional modules 31 of said PG comprises peripheral I/O unit 311, CPU312, FPGA unit 313, random memory unit 314, radio frequency units 315 and non-volatile memory cells 316.Wherein, The function of power module 32, SG module 33, peripheral I/O unit 311, FPGA unit 313, random memory unit 314 and radio frequency units 315 is identical with radio frequency units 215 with power module 22, SG module 23, peripheral I/O unit 211, FPGA unit 213, random memory unit 214 among first embodiment, repeats no more at this.
In the present embodiment, non-volatile memory cells 316 is a nonvolatile memory, like flash memory Flash; Be connected with CPU312, random memory unit 314 and FPGA unit 313, through voltage data are carried out erasable, be characterized in cutting off the power supply the back data can not disappear; Read or write speed is fast; Good stability is used for when knowing CPU312 when random memory unit 314 transmission download resolution chart data arrive the download instruction of FPGA unit 313, resolution chart data and zone bit in the backup random memory unit 314; When receiving the download instruction of CPU312 transmission, the resolution chart data of preserving are downloaded in the FPGA unit 313.
In the present embodiment, CPU312 comprises the detecting unit 312a and the first instruction sending unit 312b.Detecting unit 312a is used to detect radio frequency units 315 and whether receives the updating mark position; The first instruction sending unit 312b; Be used to receive the testing result that detecting unit 312a sends; If radio frequency units 315 receives the updating mark position, then send first data transfer instruction, control radio frequency units 315 is sent the resolution chart data to random memory unit 314; Also be used for when PG power-off restarting and detecting unit 312a detect radio frequency units 315 and do not receive the updating mark position, send to non-volatile memory cells 316 and download the resolution chart data of preserving download instruction to FPGA unit 313.
Specifically set forth in the face of the principle of work of PG shown in Figure 3 down.PG is normally in service, whether receives the resolution chart data and the zone bit of renewal in the detecting unit 312a detecting real-time radio frequency units 315.The first instruction sending unit 312b receives the testing result of detecting unit 312a; If the updating mark position is arranged; Then send first data transfer instruction to radio frequency units 315; Be sent among the SDRAM resolution chart data that receive and zone bit temporary; SDRAM downloads to the resolution chart data among the SDRAM in the FPGA unit 313 in the control of the download instruction of the first instruction sending unit 312b down on the one hand, the resolution chart data of keeping among the SDRAM and zone bit is sent among the Flash preserve on the other hand; Do not Update Information if having, PG normally moves.After PG normal boot-strap or outage are restarted; If detecting unit 312a does not detect radio frequency units 315 and receives the updating mark position; Then the first instruction sending unit 312b sends download instruction to Flash, and the resolution chart data of preserving among the Flash are downloaded in the FPGA unit 313.
Present embodiment increases non-volatile memory cells 316, makes the data that are stored in the non-volatile memory cells 316 can not lose because of outage.Non-volatile memory cells 316 is used for preserving the data that random memory unit 314 is kept in; Make when PG power-off restarting and radio frequency units 315 take place does not receive renewal; Needn't utilize the PCWCIA storage card; Only need to accomplish reconfiguring to FPGA unit 313 through being used to dispose the resolution chart data of FPGA unit 313 before the outage of downloading preservation in the non-volatile memory cells 316.After present embodiment has overcome the PG power-off restarting; Do not detecting under the situation about Updating Information; Need to insert the shortcoming that the PCWCIA storage card reconfigures PG; Make PG can realize loading fully automatically of resolution chart data, the defective of having avoided manual loading to bring has improved the dirigibility and the stability of PG operation.
Fig. 4 is the structural representation of the 3rd embodiment of pattern generator of the present invention.As shown in Figure 4, said PG is made up of main functional modules 41, power module 42 and SG module 43 3 parts.The main functional modules 41 of said PG comprises peripheral I/O unit 411, CPU412, FPGA unit 413, random memory unit 414, radio frequency units 415, non-volatile memory cells 416 and judgement unit 417.Wherein, The function of power module 42, SG module 43, peripheral I/O unit 411, FPGA unit 413, random memory unit 414 and radio frequency units 415 is identical with radio frequency units 315 with power module 32, SG module 33, peripheral I/O unit 311, FPGA unit 313, random memory unit 314 among second embodiment, repeats no more at this.
In the present embodiment, increase judgement unit 417, constitute by a numerical value comparator circuit.Fig. 5 is judgement unit workflow synoptic diagram among the 3rd embodiment of pattern generator of the present invention.As shown in Figure 5; Judgement unit 417 is used for when detecting unit 412a detects radio frequency units 415 and receives the updating mark position; Receive the updating mark position of radio frequency units 415 transmissions and the zone bit of the current saved that non-volatile memory cells 416 sends; Whether the zone bit of judging updating mark position and current saved is identical, and sends the differentiation result to CPU412.
In the present embodiment, CPU412 also comprises the second instruction sending unit 412c, receiving element 412d and the 3rd instruction sending unit 412e.The second instruction sending unit 412c; Be used for when detecting unit 412a has detected the updating mark position; Send the zone bit transfer instruction respectively to radio frequency units 415 and non-volatile memory cells 416, control radio frequency units 415 sends updating mark position to judgement unit 417 and non-volatile memory cells 416 sends zone bit to the judgement unit 417 of current saved; Also be used for detecting when not having the updating mark position, send to non-volatile memory cells 416 and download the resolution chart data of preserving download instruction to FPGA unit 413 as PG power-off restarting and detecting unit 412a.Receiving element 412d is used to receive the differentiation result that judgement unit 417 sends.The 3rd instruction sending unit 412e; Be used for if the differentiation result that receiving element 412d receives is different for the zone bit of updating mark position and current saved; Then send second data transfer instruction to radio frequency units 415, control radio frequency units 415 is sent resolution chart data and zone bit to random memory unit 414; If the differentiation result that receiving element 412d receives is identical for the zone bit of updating mark position and current saved; Then send the refusal data transfer instruction, stop radio frequency units 415 to send resolution chart data and zone bit to random memory unit 414 to radio frequency units 415.
Below in conjunction with Fig. 5 the principle of work of PG shown in Figure 4 is specifically set forth.PG is normally in service, whether receives the resolution chart data and the zone bit of renewal in the detecting unit 412a detecting real-time radio frequency units 415.The second instruction sending unit 412c receives the testing result of detecting unit 412a; Update Information if detected; Then on the one hand send the zone bit transfer instructions, the zone bit of the renewal that receives in the radio frequency units 415 is sent in the judgement unit 417 to radio frequency units 415; Send the zone bit transfer instruction to Flash on the other hand, the zone bit of preserving among the Flash is sent in the judgement unit 417.417 pairs of above-mentioned two zone bits of judgement unit compare, and judge whether the zone bit that upgrades is identical with the zone bit of current saved, and comparative result is sent among the receiving element 412d of CPU412.The 3rd instruction sending unit 412e sends instruction according to the differentiation result of receiving element 412d to radio frequency units 415; If it is different with the zone bit of current saved for the zone bit that upgrades to differentiate the result; Then send second data transfer instruction, the resolution chart data and the zone bit of the renewal that radio frequency units 415 is received are sent to SDRAM; If it is identical with the zone bit of current saved for the zone bit that upgrades to differentiate the result, then send the refusal data transfer instruction, stop radio frequency units 415 to send the resolution chart data that receive to SDRAM, PG continues normal operation.Behind PG normal boot-strap or power-off restarting; If detecting unit 412a detects and does not have the updating mark position; Then the second instruction sending unit 412c sends download instruction to Flash, and the resolution chart data of preserving among the Flash are downloaded to configuration circuit parameter in the FPGA unit 413.
Present embodiment increases judgement unit 417, has avoided the repeated downloads to the resolution chart data with identical zone bit, has improved the work efficiency when the PG Automatic Program is upgraded, and has reduced the Internet resources expense.
On the basis of the 3rd embodiment, judgement unit 417 is integrated in the CPU412, can improve the decision process speed of CPU412, simplify the PG inner structure, reduce production costs.Each Elementary Function is identical with the 3rd embodiment of PG among the PG, repeats no more at this.
Fig. 6 is the structural representation of the embodiment of graph data update system of the present invention.As shown in Figure 6, the graph data update system comprises a plurality of pattern generators with less radio-frequency function, graph data transmitting apparatus and wireless router.The 26S Proteasome Structure and Function of pattern generator can repeat no more at this with reference to above-mentioned Fig. 2 to embodiment shown in Figure 4.The graph data transmitting apparatus can be the PC main frame or the hand-hold wireless launch terminal of a band less radio-frequency function, and the PG that is used in the network sends the resolution chart data of upgrading.Wireless router to every PG dynamic assignment IP address, through the control of less radio-frequency transmitting apparatus, can selectively send the resolution chart data of upgrading to the PG of particular ip address through built-in DHCP function.Pattern generator is used for receiving the resolution chart data of the renewal of network, and pattern generator is upgraded.
Present embodiment utilizes wireless router to accomplish many networkings between the PG with less radio-frequency function; Accomplish the PG Configuration Online in batches through the graph data transmitting apparatus; Make a plurality of PG can be in a LAN by overall situation control, realize the Automatic Program down loading updating, greatly reduce manual work upgrade one by one PG consumed time and manpower; Simplify a plurality of PG updating steps, improved the dirigibility that a plurality of PG upgrade.
Fig. 7 is the method flow synoptic diagram of first embodiment of graph data update method of the present invention.As shown in Figure 7, specifically comprise following processing operation:
Random memory unit is a SDRAM, can directly cover gibberish, in case be characterized in outage, storage information above that will all disappear and can't recover.SDRAM is used for the resolution chart data and the zone bit of the renewal that temporary radio frequency units will receive.
Non-volatile memory cells carries out erasable to data through voltage, the back data that are characterized in cutting off the power supply can not disappear, and read or write speed is fast, and good stability is used for backing up the resolution chart data and the zone bit of random memory unit.
Fig. 8 is the normal runtime data update method of a PG schematic flow sheet among first embodiment of graph data update method.As shown in Figure 8, specifically comprise following processing operation:
Present embodiment utilizes the less radio-frequency function through making PG, the resolution chart data that automatic reception is upgraded, and the resolution chart data that are used for the configuration circuit parameter are backed up, make PG to load renewal fully automatically, simplified the step of PG artificial regeneration.
Fig. 9 is the method flow synoptic diagram of second embodiment of graph data update method of the present invention.On the basis of the said embodiment of Fig. 7; After CPU detects radio frequency units existence renewal; CPU sends before first data transfer instruction; Can also increase a discriminating step, be used for judging the current resolution chart data that are used for the configuration circuit parameter of resolution chart data and the PG of renewal which for up-to-date.As shown in Figure 9, specifically comprise following processing operation:
Step 201, PG normal boot-strap or because of power-off restarting;
Step 202, CPU detect in the radio frequency units whether have the resolution chart data of renewal and the zone bit of renewal, if there is the updating mark position, then execution in step 203, if there is not the updating mark position, then execution in step 204;
Step 203, CPU assign the zone bit transfer instruction to radio frequency units on the one hand; The zone bit of the renewal that receives is sent to judgement unit; Assign the zone bit transfer instruction to non-volatile memory cells on the other hand, the zone bit of preserving is sent to judgement unit, execution in step 205;
Step 204, CPU send download instruction to non-volatile memory cells, the resolution chart data of preserving in the non-volatile memory cells are downloaded in the FPGA unit execution in step 209;
Step 205, CPU receive the differentiation result that judgement unit sends; Send the instruction control data transmission according to differentiating the result; If the differentiation result is that the zone bit of updating mark position and current saved is different; Then execution in step 206, are that the zone bit of updating mark position and current saved is identical if differentiate the result, and then execution in step 207;
Step 206, CPU send second data transfer instruction to radio frequency units, and the control radio frequency units is sent resolution chart data and updating mark position, execution in step 208 to random memory unit;
Step 207, CPU send the refusal data transfer instruction to radio frequency units, and the renewal that stops radio frequency units to receive is sent to random memory unit, execution in step 204;
Step 208, under the control of CPU download instruction; Random memory unit downloads to the resolution chart data of its storage in the FPGA unit; Utilize circuit to realize the parameter in the resolution chart data, and resolution chart data and zone bit temporary in the random memory unit backuped to non-volatile memory cells;
Step 209, PG normally move, and produce the signal that is fit to liquid crystal panel, finally on liquid crystal panel, present new resolution chart.
Figure 10 is the normal runtime data update method of a PG schematic flow sheet among second embodiment of graph data update method.Shown in figure 10, specifically comprise following processing operation:
Present embodiment is through adding the less radio-frequency function in PG; Between PG, increase communication channel; Through to the renewal version information that receives and the comparison of current version information, the resolution chart data that are used to dispose PG are carried out automatic down loading updating, avoided the artificial shortcoming that is written into renewal; Improve PG and upgraded dirigibility, validity.
What should explain at last is: above embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although with reference to previous embodiment the present invention has been carried out detailed explanation, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (9)
1. pattern generator; Comprise signal generating module; Power module and the main functional modules that is connected with power module with said signal generating module; Said main functional modules comprises central processing unit CPU, on-site programmable gate array FPGA unit, random memory unit and peripheral I/O unit, it is characterized in that, said main functional modules also comprises:
Radio frequency units links to each other with random memory unit with said CPU, is used for acceptance test graph data and zone bit, and according to the data transfer instruction of said CPU said resolution chart data and zone bit is sent to said random memory unit;
Said main functional modules also comprises:
Non-volatile memory cells; Be connected with said CPU, random memory unit and FPGA unit; Be used for when knowing that said CPU when the said resolution chart data of said random memory unit transmission download arrive the download instruction of said FPGA unit, backs up said resolution chart data and said zone bit in the said random memory unit; When receiving the download instruction of said CPU transmission, the said resolution chart data of preserving are downloaded to said FPGA unit;
Said CPU comprises:
Detecting unit is used to detect said radio frequency units and whether receives the updating mark position.
2. pattern generator according to claim 1 is characterized in that, said CPU also comprises:
First instruction sending unit; Link to each other with said detecting unit; Be used to receive the testing result that said detecting unit sends; If said radio frequency units receives said updating mark position, then send first data transfer instruction to said radio frequency units, control said radio frequency units and send said resolution chart data to said random memory unit; Also be used for when said pattern generator power-off restarting and said detection when said radio frequency units does not receive said updating mark position, send to said non-volatile memory cells and to download the said resolution chart data of preserving download instruction to said FPGA unit.
3. pattern generator according to claim 1 is characterized in that, said main functional modules also comprises:
Judgement unit; Link to each other with said CPU, radio frequency units and non-volatile memory cells; Be used for when said detection when said radio frequency units receives said updating mark position; Receive the said updating mark position of said radio frequency units transmission and the zone bit of the current saved that said non-volatile memory cells sends, judge whether the zone bit of said updating mark position and said current saved is identical, and send the differentiation result to said CPU.
4. pattern generator according to claim 3 is characterized in that, said CPU also comprises:
Second instruction sending unit; Link to each other with said detecting unit; Be used for when said detection when said radio frequency units receives said updating mark position; Send the zone bit transfer instruction respectively to said radio frequency units and said non-volatile memory cells, control said radio frequency units and send zone bit to the said judgement unit that said updating mark position to said judgement unit and said non-volatile memory cells sends said current saved; Also be used for when said pattern generator power-off restarting and said detection when said radio frequency units does not receive said updating mark position, send to said non-volatile memory cells and to download the said resolution chart data of preserving download instruction to said FPGA unit;
Receiving element is used to receive the differentiation result that said judgement unit sends;
The 3rd instruction sending unit; Link to each other with said receiving element; If the said differentiation result that said receiving element receives is different for the zone bit of said updating mark position and said current saved; Then send second data transfer instruction, control said radio frequency units and send said resolution chart data and zone bit to said random memory unit to said radio frequency units; If the said differentiation result that said receiving element receives is identical for the zone bit of said updating mark position and said current saved; Then send the refusal data transfer instruction, stop said radio frequency units to send said resolution chart data and zone bit to said random memory unit to said radio frequency units.
5. a graph data update system is characterized in that, comprises each described pattern generator of claim 1～4, also comprises graph data transmitting apparatus and wireless router, wherein:
Said wireless router is used for the address to said pattern generator dynamic assignment IP;
Said graph data transmitting apparatus is used for transmitting the resolution chart data of upgrading to the pattern generator of assigned ip address.
6. graph data update method is characterized in that concrete steps comprise:
Step 1, pattern generator are normally in service, and the central processing unit CPU of said pattern generator detects radio frequency units and receives the updating mark position;
Step 2, send first data transfer instruction, control said radio frequency units and send resolution chart data and said zone bit to random memory unit to said radio frequency units;
Step 3, send download instruction, control said random memory unit said resolution chart data are downloaded in the on-site programmable gate array FPGA unit to said random memory unit.
7. graph data update method according to claim 6 is characterized in that, said step 3 also comprises: said resolution chart data and zone bit are backuped in the non-volatile memory cells.
8. graph data update method according to claim 7 is characterized in that,
Also comprise between said step 1 and the step 2:
Step 11, said CPU send the zone bit transfer instruction respectively to said radio frequency units and said non-volatile memory cells, control zone bit to the said judgement unit that said radio frequency units is sent updating mark position to judgement unit and said non-volatile memory cells transmission current saved;
Step 12, said CPU receive the differentiation result that said judgement unit sends;
Then said step 2 is specially:
Step 21, different if said differentiation result is the zone bit of said updating mark position and said current saved; Then send second data transfer instruction, control said radio frequency units and send said resolution chart data and said updating mark position to random memory unit to said radio frequency units; If said differentiation result is that the zone bit of said updating mark position and said current saved is identical, then send the refusal data transfer instruction to said radio frequency units.
9. according to claim 7 or 8 described graph data update methods, it is characterized in that, when said pattern generator power-off restarting and said CPU detect said radio frequency units and do not receive said updating mark position, also comprise:
Said CPU sends to said non-volatile memory cells and downloads the download instruction that the said resolution chart data of preserving arrive said FPGA unit, controls said non-volatile memory cells and sends said resolution chart data to the said FPGA unit of preserving.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100886454A CN101944314B (en) | 2009-07-06 | 2009-07-06 | Pattern generator, pattern data updating system and pattern data updating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100886454A CN101944314B (en) | 2009-07-06 | 2009-07-06 | Pattern generator, pattern data updating system and pattern data updating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101944314A CN101944314A (en) | 2011-01-12 |
| CN101944314B true CN101944314B (en) | 2012-10-31 |
Family
ID=43436288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100886454A Active CN101944314B (en) | 2009-07-06 | 2009-07-06 | Pattern generator, pattern data updating system and pattern data updating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101944314B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012131701A2 (en) * | 2011-03-11 | 2012-10-04 | The Tata Power Company Ltd. | Fpga system for processing radar based signals for aerial view display |
| CN102509315B (en) * | 2011-09-23 | 2014-04-30 | 中国航空工业集团公司洛阳电光设备研究所 | Stroke type symbol generator and writing method thereof |
| CN104407885B (en) * | 2014-10-31 | 2017-11-10 | 武汉精测电子技术股份有限公司 | Enter the method for line program loading to the FPGA in more pattern generators simultaneously |
| CN104679571B (en) * | 2015-03-25 | 2017-12-15 | 武汉精测电子技术股份有限公司 | Multiple pattern generators are entered with the apparatus and method that line program upgrades automatically simultaneously |
| CN107564492B (en) * | 2017-09-13 | 2021-07-09 | 武汉精测电子集团股份有限公司 | Adaptive cascade graphic signal generation system |
| CN108877613A (en) * | 2018-07-24 | 2018-11-23 | 武汉华星光电技术有限公司 | The test device and test method of display panel |
| US11557264B2 (en) | 2019-04-10 | 2023-01-17 | Hefei Reliance Memory Limited | Display driver system with embedded non-volatile memory |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1677117A (en) * | 2004-04-02 | 2005-10-05 | 明基电通股份有限公司 | Wireless detection system |
| CN2807289Y (en) * | 2004-11-12 | 2006-08-16 | 北京理工大学 | Liquid crystal photoelectric figure generator |
| TW200639418A (en) * | 2005-05-04 | 2006-11-16 | Univ Nat Tsing Hua | System for probing integrated circuit devices |
| KR100675322B1 (en) * | 2004-12-09 | 2007-01-26 | 엘지전자 주식회사 | Test Apparatus And Method For Plasma Display Module |
| CN101178660A (en) * | 2007-04-28 | 2008-05-14 | 四川长虹电器股份有限公司 | Memory data automatic update method |
-
2009
- 2009-07-06 CN CN2009100886454A patent/CN101944314B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1677117A (en) * | 2004-04-02 | 2005-10-05 | 明基电通股份有限公司 | Wireless detection system |
| CN2807289Y (en) * | 2004-11-12 | 2006-08-16 | 北京理工大学 | Liquid crystal photoelectric figure generator |
| KR100675322B1 (en) * | 2004-12-09 | 2007-01-26 | 엘지전자 주식회사 | Test Apparatus And Method For Plasma Display Module |
| TW200639418A (en) * | 2005-05-04 | 2006-11-16 | Univ Nat Tsing Hua | System for probing integrated circuit devices |
| CN101178660A (en) * | 2007-04-28 | 2008-05-14 | 四川长虹电器股份有限公司 | Memory data automatic update method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101944314A (en) | 2011-01-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101944314B (en) | Pattern generator, pattern data updating system and pattern data updating method | |
| CN102609286B (en) | A kind of FPGA configurator remote update system based on processor control and method thereof | |
| CN103942061A (en) | Battery firmware updating method, portable electronic device and rechargeable battery module | |
| CN101938566B (en) | Visual terminal debugging method and device | |
| CN103793238A (en) | Rack and method for simultaneously updating multiple basic input output systems thereof | |
| CN103136012A (en) | Computer system and update method of basic input-output system thereof | |
| US9543996B2 (en) | Method and system for initializing RF module through non-volatile control | |
| CN103365688A (en) | Method for automatic installation and synchronization of software between Android intelligent devices | |
| CN106874054A (en) | A kind of repeater inner module program on-line upgrading method and system | |
| CN104407881A (en) | Active RFID (radio frequency identification) firmware remote upgrading method | |
| CN109451098A (en) | FPGA accelerator card MAC Address configuration method, device and accelerator card | |
| CN108804232A (en) | A kind of method, host server and the system of supporting high in the clouds FPGA to dispose | |
| CN102033767B (en) | A kind of method of veneer and veneer online upgrading | |
| CN103488516A (en) | System repair method and electronic equipment | |
| CN104158709A (en) | Optical module identification method and port extender | |
| CN103105920A (en) | Energy-saving system and energy-saving method | |
| CN106649137A (en) | Nand Flash bad block management method and device and memory | |
| JP4727370B2 (en) | Wireless communication terminal and control method thereof | |
| CN116301294B (en) | System chip low-power-consumption implementation method, system chip, vehicle machine and equipment | |
| US11755439B2 (en) | Memory controller, test device and link identification method | |
| CN116298801A (en) | Chip testing device, method, electronic equipment and storage medium | |
| CN105354066A (en) | OTA (over the air) downloading method, device and intelligent terminal | |
| CN101515240A (en) | Digital signal processor loading method, electronic device and electronic system | |
| CN102083099A (en) | Base station and method and a device for electrifying same in single station mode | |
| CN108712290A (en) | network card driving method, device and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150703 Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150703 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150703 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing economic and Technological Development Zone, West Central Road, No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |