CN104407885B - Enter the method for line program loading to the FPGA in more pattern generators simultaneously - Google Patents
Enter the method for line program loading to the FPGA in more pattern generators simultaneously Download PDFInfo
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- CN104407885B CN104407885B CN201410616910.2A CN201410616910A CN104407885B CN 104407885 B CN104407885 B CN 104407885B CN 201410616910 A CN201410616910 A CN 201410616910A CN 104407885 B CN104407885 B CN 104407885B
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Abstract
The invention discloses the method for entering line program loading to the FPGA in more pattern generators simultaneously, including 1, user to log in computer；2nd, the pattern generator for needing to carry out ROMPaq loading is selected in computer；3rd, computer is established with selected pattern generator and communicated；4th, FPGA program upgrade files are chosen from computer, FPGA Loading Control agreements, FPGA Loading Control agreements corresponding to the ARM acquisitions of each pattern generator are issued to the ARM for the pattern generator for having built up communication in the form of broadcast packet by interchanger；5th, the ARM of every pattern generator according to the file path where FPGA upgrade files from computer the path corresponding to FPGA upgrade files copy in pattern generator；6th, the ARM of every pattern generator, the FPGA upgrade files of pattern generator are loaded into corresponding FPGA.The present invention can lift the FPGA programs upgrading efficiency of batch pattern generator.
Description
Technical field
The present invention relates to the journey of FPGA (Field-Programmable Gate Arrays, FPGA)
Sequence loading technique field, in particular to the method for entering line program loading to the FPGA in more pattern generators simultaneously.
Background technology
At present, it is necessary to be loaded to the FPGA programs in pattern generator after equipment shipment, loading procedure is one-to-one
Loading, the FPGA programs in more pattern generators can not be upgraded simultaneously.Meanwhile figure before each FPGA programs loading
Generator is required for carry file system (about 1 minute the time required to carry), and carry process one by one consumes largely
Time.
In addition, multiple SPI are connected by spi bus using an ARM (Advanced RISC Machines) processor
Class flash memory carries out one-to-many pattern generator FPGA programs upgrading, can meet the needs of volume production upgrades before shipment, but by
FPGA upgrading could be carried out after needing to disassemble FPGA from pattern generator, is not suitable for the scene liter after shipment
Level application.
The content of the invention
Present invention aim to provide a kind of while enter what line program loaded to the FPGA in more pattern generators
Method, this method can lift the FPGA programs upgrading efficiency of batch pattern generator.
In order to achieve this, enter line program loading while designed by the present invention to the FPGA in more pattern generators
Method, it is characterised in that it comprises the following steps：
Step 1：User logs in computer；
Step 2：Selecting in the upper strata pattern generator control software of computer multiple needs to carry out ROMPaq loading
Pattern generator；
Step 3：Computer is established with above-mentioned selected pattern generator by interchanger and communicated to connect；
Step 4：User chooses figure by operating upper strata pattern generator control software from the memory of computer
The FPGA program upgrade files of device, user operate upper strata pattern generator control software by interchanger in the form of broadcast packet to
Arm processor inside the above-mentioned pattern generator for having built up communication connection issues FPGA Loading Control agreements, and the FPGA adds
Carrying control protocol includes pattern generator storage frame address, pattern generator address, command word and version of an agreement, agreement text
This includes the file path where FPGA upgrade files, and the arm processor inside above-mentioned each pattern generator, which passes through, matches figure
Shape generator storage frame address, pattern generator address and FPGA Loading Control agreements corresponding to command word acquisition；
Step 5：Arm processor in every pattern generator is according to where the FPGA upgrade files obtained in step 4
File path copies FPGA upgrade files corresponding to the path in the memory of pattern generator to from computer；
Step 6：Arm processor in every pattern generator sends out figure according to pattern generator internal communication protocol
FPGA upgrade files in the memory of raw device are loaded into corresponding FPGA, that is, are completed simultaneously in more pattern generators
FPGA enters the process of line program loading.
Beneficial effects of the present invention：
The present invention is realized by above-mentioned steps while enters line program loading to the FPGA in more pattern generators and (risen
Level), while to more pattern generator carry file system, greatly improve the efficiency of batch pattern generator upgrading, contract
The short time of pattern generator batch upgrade, also, more pattern generators need to only be connect by interchanger during upgrading
Enter computer, it is not necessary to pull down FPGA from pattern generator, escalation process is convenient, and the pattern generator that is particularly suitable for use in goes out
Batch upgrade after goods.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention；
Wherein, 1-computer, 2-pattern generator, 3-interchanger.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail：
Enter the method for line program loading to the FPGA in more pattern generators simultaneously as shown in Figure 1, it is characterised in that it
Comprise the following steps：
Step 1：User logs in computer 1, and (user logs in computer 1 by super code, and only power user just has upgrading
Authority)；
Step 2：Selecting in the upper strata pattern generator control software of computer 1 multiple needs to carry out ROMPaq loading
Pattern generator 2, (pattern generator 2 can individually be upgraded, the multiselect of pattern generator 2 can be upgraded, can also be whole
All pattern generators 2 in individual pattern generator storage frame upgrade together)；
Step 3：Computer 1 is established with above-mentioned selected pattern generator 2 by interchanger 3 and communicated to connect；
Step 4：User chooses figure to send out by operating upper strata pattern generator control software from the memory of computer 1
The FPGA program upgrade files of raw device, user operate upper strata pattern generator control software by interchanger 3 with the shape of broadcast packet
Formula issues FPGA Loading Control agreements to the arm processor inside the above-mentioned pattern generator 2 for having built up communication connection, should
FPGA Loading Controls agreement includes pattern generator storage frame address, pattern generator address, command word and version of an agreement, should
Version of an agreement includes the file path where FPGA upgrade files, and the arm processor inside above-mentioned each pattern generator 2 passes through
Match pattern generator storage frame address, pattern generator address and FPGA Loading Control agreements corresponding to command word acquisition；
Step 5：Arm processor in every pattern generator is according to where the FPGA upgrade files obtained in step 4
File path copies FPGA upgrade files corresponding to the path in the memory of pattern generator 2 to from computer 1；
Step 6：Arm processor in every pattern generator sends out figure according to pattern generator internal communication protocol
FPGA upgrade files in the memory of raw device 2 are loaded into corresponding FPGA, that is, are completed simultaneously in more pattern generators
FPGA enter line program loading process.
In above-mentioned technical proposal, the command word includes upgrade command word and querying command word.
In the step 3 of above-mentioned technical proposal~6, the upper strata pattern generator control software of computer 1 is regularly to each figure
The FPGA ROMPaq stress states of the current each pattern generator 2 of arm processor inquiry of generator 2, and by each figure
The FPGA ROMPaqs stress state of generator 2 is shown that upgrading progress prompts user, upgrading by progress bar in computer 1
During do not allow user to carry out other operations to computer 1 or pattern generator 2.
In above-mentioned technical proposal, the FPGA ROMPaqs stress state includes current upgrading progress, upgrading failure, upgrading
Complete or upgrade overtime four kinds of states.
In above-mentioned technical proposal, the communication ends of the computer 1 connect the communication of each pattern generator 2 by interchanger 3
End.
The present invention can realize to work as by above-mentioned design has pattern generator 2 selected individually to load FPGA programs for the first time
During failure, next time can individually choose these pattern generators 2 to be reloaded.
User is carried out by the Update modules (upgraded module) in the pattern generator control software of upper strata in the present invention
The loading operation of FPGA programs, upper strata pattern generator control software pass through the ARM in JCMCPA communication modules and pattern generator 2
Processor carries out UDP (User Datagram Protocol, UDP) data interaction, and arm processor is responsible for obtaining
Take and load FPGA programs.
The content that this specification is not described in detail belongs to prior art known to professional and technical personnel in the field.
Claims (3)
1. method that is a kind of while entering line program loading to the FPGA in more pattern generators, it is characterised in that it is included such as
Lower step：
Step 1：User logs in computer (1)；
Step 2：Multiple figures for needing to carry out ROMPaq loading are selected in the upper strata pattern generator control software of computer (1)
Shape generator (2)；
Step 3：Computer (1) is established with above-mentioned selected pattern generator (2) by interchanger (3) and communicated to connect；
Step 4：User chooses figure by operating upper strata pattern generator control software from the memory of computer (1)
The FPGA program upgrade files of device, user operate upper strata pattern generator control software by interchanger (3) with the shape of broadcast packet
Formula issues FPGA Loading Control agreements to the internal arm processor of the above-mentioned pattern generator (2) for having built up communication connection, should
FPGA Loading Controls agreement includes pattern generator storage frame address, pattern generator address, command word and version of an agreement, should
Version of an agreement includes the file path where FPGA upgrade files, and the internal arm processor of above-mentioned each pattern generator (2) leads to
Overmatching pattern generator storage frame address, pattern generator address and FPGA Loading Controls association corresponding to command word acquisition
View；
Step 5：Arm processor in every pattern generator is according to the file where the FPGA upgrade files obtained in step 4
Path copies FPGA upgrade files corresponding to the path in the memory of pattern generator (2) to from computer (1)；
Step 6：Arm processor in every pattern generator is according to pattern generator internal communication protocol, by pattern generator
(2) the FPGA upgrade files in memory are loaded into corresponding FPGA, that is, are completed simultaneously in more pattern generators
FPGA enters the process of line program loading；
The command word includes upgrade command word and querying command word；
In step 3~6, the upper strata pattern generator control software of computer (1) is regularly to each pattern generator (2)
The FPGA ROMPaq stress states of the current each pattern generator (2) of arm processor inquiry, and by each pattern generator
(2) FPGA ROMPaqs stress state is shown that upgrading progress prompts user by progress bar in computer (1).
2. method that is according to claim 1 while entering line program loading to the FPGA in more pattern generators, it is special
Sign is：The FPGA ROMPaqs stress state includes current upgrading progress, upgrading failure, upgrading is completed or upgrading time-out four
Kind state.
3. method that is according to claim 1 while entering line program loading to the FPGA in more pattern generators, it is special
Sign is：The communication ends of the computer (1) connect the communication ends of each pattern generator (2) by interchanger (3).
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| CN201410616910.2A CN104407885B (en) | 2014-10-31 | 2014-10-31 | Enter the method for line program loading to the FPGA in more pattern generators simultaneously |
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| CN104407885B true CN104407885B (en) | 2017-11-10 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104679571B (en) * | 2015-03-25 | 2017-12-15 | 武汉精测电子技术股份有限公司 | Multiple pattern generators are entered with the apparatus and method that line program upgrades automatically simultaneously |
| CN104935786B (en) * | 2015-05-28 | 2018-03-27 | 武汉精测电子集团股份有限公司 | A kind of method of image signal source and its processing picture signal based on soft processor |
| CN107870756B (en) * | 2017-10-26 | 2021-02-02 | 武汉精测电子集团股份有限公司 | Method and system for synchronously controlling multiple graphic signal generators |
| CN112241281B (en) * | 2020-10-14 | 2024-02-06 | 四川九洲空管科技有限责任公司 | Batch upgrading method and system for digital radar TR (transmitter/receiver) module FPGA (field programmable Gate array) program |
| CN113742003B (en) * | 2021-09-15 | 2023-08-22 | 深圳市朗强科技有限公司 | Program code execution method and device based on FPGA chip |
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| CN103677905A (en) * | 2013-11-30 | 2014-03-26 | 成都天奥信息科技有限公司 | Remote configuration program upgrading circuit of FPGA (field programmable gate array) embedded terminal |
| CN203588252U (en) * | 2013-11-30 | 2014-05-07 | 成都天奥信息科技有限公司 | Upgrading circuit for FPGA (Field Programmable Gate Array) configuration program |
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| US9411701B2 (en) * | 2013-03-13 | 2016-08-09 | Xilinx, Inc. | Analog block and test blocks for testing thereof |
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| CN101944314A (en) * | 2009-07-06 | 2011-01-12 | 北京京东方光电科技有限公司 | Pattern generator, pattern data updating system and pattern data updating method |
| CN102662718A (en) * | 2012-05-03 | 2012-09-12 | 天津市英贝特航天科技有限公司 | Module for starting multiple user programs by single Flash |
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Address after: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee after: Wuhan fine test electronics group Limited by Share Ltd Address before: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee before: Wuhan Jingce Electronic Technology Co., Ltd. |