CN101938667A - 3D (Three Dimensional) digital video signal processing method and device thereof - Google Patents
3D (Three Dimensional) digital video signal processing method and device thereof Download PDFInfo
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- CN101938667A CN101938667A CN 201010252157 CN201010252157A CN101938667A CN 101938667 A CN101938667 A CN 101938667A CN 201010252157 CN201010252157 CN 201010252157 CN 201010252157 A CN201010252157 A CN 201010252157A CN 101938667 A CN101938667 A CN 101938667A
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Abstract
The invention discloses a 3D (Three Dimensional) digital video signal processing method and a device thereof. The method comprises the following steps of: connecting an external 3D digital video signal source and receiving; detecting a format of the signal; receiving and storing the signal; processing the spatial domain of the signal; processing the time domain of the signal, outputting the signal, and the like. The device comprises a field programmable gate array (FPGA) chip, an HDMI1.4A receiving circuit, a micro processing unit (MCU), an infrared 3D signal synchronous sending circuit, an image storage, a 3D video image simulation sender and a 3D video digital sender. The invention provides an effective path for the display of a 3D digital video, which makes the traditional television in the family of a consumer show a 3S image without modification.
Description
Technical field
The present invention relates to 3D Display Technique field, particularly a kind of 3D digital video signal processing method and device thereof.
Background technology
Stereo display technique is the forward position research topic that shows the field at present, it is the main support link of virtual reality technology, it is the primary study direction of message area, its core is utilization computer graphics, image processing and an optical technology, initial data is converted to figure or image parameter shows on screen three-dimensionally, and can carry out theory, method and the technology of interactive process.It relates to many technical fields such as computer graphics, image processing, computer-aided design, computer vision and man-machine interaction, transducer, automation servo system.The virtual demonstration of 3D is to realize by the telepresenc of stereoscopic vision, has become one of focus of various countries' research since the eighties in 20th century.Countries and regions such as Japan, Korea S, America and Europe have taken the lead in beginning the basic research that 3D shows, and obtain achievement successively in the nineties.In the CES exhibitions in 2010, increasing 3D display application product is constantly gushed out in the CES2010 exhibition.At present, the 3D Display Technique of 4 kinds of comparative maturities has been arranged on the market, comprised the color solid three-dimensional, polarization two-dimensional, stereoscopic three-dimensional, and DLP-Link technology.
Color solid three-dimensional release time on market is the longest, and principle is also simple, and cost is minimum.The principle of this technology is fairly simple, by physics principle, uses the filter of different colours to carry out picture and filters, and makes a picture can produce two width of cloth images, and modal filter color is normally red/indigo plant, red/green, perhaps red/green grass or young crops.
The polarization three-dimensional is compared with the color solid 3-D technology, and the polarization 3-D technology promotes very obvious aspect the image quality of stereopsis.Add that by two projectors and two polarized lenses the combination of anaglyph spectacles realizes 3D effect.The cost of polaroid glasses is also cheap relatively simultaneously, and minimum dozens of yuan just can buy.But the drawback of this class technology needs two projectors, and cost is higher.
Stereoscopic three-dimensional is present our modal a kind of 3D shadow casting technique.Current nearly all 3D movie theatre all is this equipment that adopts.The stereoscopic three-dimensional technology mainly is to have adopted the form of frame sequence to produce stereo-picture.The realization of stereoscopic three-dimensional technology needs three key elements, and at first the refresh rate of projected picture need reach per second 120 frames, secondly needs an Infrared Projector and the 3D anaglyph spectacles that can receive infrared signal.
Summary of the invention
The objective of the invention is a large amount of television sets (PDP, LCD projector etc.) of selling in recent years on the market, it possesses DVI, HDMI or rgb signal interface, but not the 3D TV, by a kind of 3D digital video signal processing method and device, existing this type of television set need not be reequiped also can show the 3D image, thereby save consumer's cost and social resources.
The object of the present invention is achieved like this:
A kind of 3D digital video signal processing method is characterized in that this method may further comprise the steps:
A) connect outside 3D digital video signal source and receive the 3D digital video signal;
B) the 3D digital video signal that receives being carried out format detection, is that television set or display carry out best resolution detection to display unit simultaneously;
C) receive storage 3D digital video signal;
D) the 3D digital video signal spatial domain of butt joint harvesting storage is handled, and makes it become the best resolution of display unit, optimal brightness, best chroma format;
E) the 3D digital video signal time-domain of butt joint harvesting storage is handled, and makes it become the best frame frequency form of display unit;
F) to treated 3D digital video signal output, promptly the 3D digital video signal is processed into displayable 2D image sequence of display unit and output, right and left eyes synchronous control signal output simultaneously.
A kind of 3D apparatus for processing of video signals, this device comprises:
One field programmable gate array (FPGA) chip;
One HDMI1.4A receiving circuit, connecting field programmable gate array (FPGA) chip is its incoming video signal also;
One microprocessor (MCU) connects field programmable gate array (FPGA) chip and produces the information exchange signal according to outside input triggering signal;
One infrared 3D signal Synchronization transtation mission circuit connects field programmable gate array (FPGA) chip and connects the infrared control 3D rendering by infrared ray and observe glasses, for it provides infrared right and left eyes synchronizing signal;
One video memory connects field programmable gate array (FPGA) chip, as the 3D video memory;
One 3D video image analog transmitter connects field programmable gate array (FPGA) chip, and the 3D digital video signal of output is transformed into the analog rgb signal, supplies with television set or display and shows;
One 3D digital video transmitter connects field programmable gate array (FPGA) chip, and output 3D digital video signal is supplied with television set or display and shown;
Wherein: described field programmable gate array (FPGA) chip comprises:
One digital video image processor circuit calculates and the processing core as control and 3D digital video signal;
One high-speed data memory interface circuit connects digital video image processor circuit, storage input digit video data Frame, superimposed image data Frame and output 3D digital of digital video data Frame;
One right and left eyes picture synchronization signal detects and control circuit, connects digital video image processor circuit, detects the sequence of left-right images of 3D video player;
One right and left eyes image replacement device circuit connects digital video image processor circuit, and according to the optimum frame frequency that receives the 3D digital of digital video data is inserted Frame and handle, and carries out the Frame sequence and resets;
One 3D digital video signal output circuit is to the output of vision signal.
The present invention has been for the demonstration of 3D digital video provides a kind of effective way, existing television set need not be reequiped also can show the 3D image.
Description of drawings
Fig. 1 is apparatus of the present invention structural representation
Fig. 2 is field programmable gate array in apparatus of the present invention (FPGA) structured flowchart
Fig. 3 is the inventive method flow chart
Fig. 4 is apparatus of the present invention workflow diagram
Embodiment
Consult Fig. 3, the concrete steps of the inventive method are:
A) connect outside 3D digital video signal source and receive the 3D digital video signal;
B) the 3D format digital video signal detects: the signal from the 3D signal source is carried out format detection, display unit (television set or display) is carried out best resolution detect;
C) the 3D digital video signal receives storage: the 3D digital video signal is received and stores;
D) 3D digital video signal spatial domain is handled: the 3D digital video signal processing is become the best resolution of display unit, optimal brightness, best chroma format;
E) 3D digital video signal time-domain is handled: the 3D digital video signal processing is become the best frame frequency form of display unit;
F) output of 3D digital video signal and the output of right and left eyes synchronous control signal: the 2D image sequence that the 3D digital video signal processing becomes display unit (television set or display) to show is also exported; Right and left eyes synchronous control signal output simultaneously.
Consult Fig. 1, apparatus of the present invention HDMI1.4A signal receiver links to each other by video bus with field programmable gate array (FPGA) chip, it comprises the video data of 24bit or 30bit width, clock signal, line synchronizing signal, Frame synchronizing signal and data effective index signal, signals such as SCL and SDA; Microprocessor MCU links to each other with FPGA with signals such as SDA by SCL;
Video memory links to each other with FPGA by signals such as 32bit width data bus and the timely clock systems of 22bit width address bus; Infrared 3D signal Synchronization transmitter links to each other with FPGA by the 1bit data wire; Infrared 3D signal Synchronization transmitter is observed glasses by infrared ray and infrared control 3D rendering and is linked to each other; 3D video image digit emitter (DVI) links to each other with FPGA by same video bus with 3D video image analog transmitter (DAC), it comprises the video data of 24bit or 30bit width, clock signal, line synchronizing signal, Frame synchronizing signal and data effective index signal, signals such as SCL and SDA; 3D video image digit emitter (DVI) links to each other with television set or display by the DVI cable; 3D video image analog transmitter (DAC) links to each other with television set or display by 75 ohm of RGB cables of simulation.
The signal input port of apparatus of the present invention is connected in a television set or display by HDMI (DVI) interface, the output (DVI or RGB) that the HDMI holding wire connects outside 3D video signal source (BD-player, DVD-player or PC), viewers wear 3D glasses constitute a 3D display system.
Hardware configuration code (software) burning is loaded into after powering in the programmable chip (FPGA) in the FPGA configuring chip automatically.
The HDMI1.4A signal receiver links to each other with MCU by the I2c bus, implements the TMDS differential signal of outside 3D video signal source (BD-player, DVD-player or PC etc.) input is received and is decoded into the RGB digital video signal or the YCbcr digital video signal of 24 of numerals or 30 bit widths under MCU control; It may be frame-packing, the side-by-side of 24Hz, also may be top-and-bottom; It can support the decoding of speed up to the signal of high-definition digital video line by line (1080p 60hz) of 148.5MHz.
Fpga chip receives the RGB digital video signal or the YCbcr digital video signal of HDMI signal receiving and decoding circuit output, and digital video signal is sent to the video memory circuit, fpga chip is finished video image and is dynamically reached static various processing, and output to digital rgb or Ycbcr form, 3D video image digit emitter (DVI) or 3D video image analog transmitter (DAC), final demonstration output is connected in external television or display by the DVI line; Simultaneously, fpga chip detects 3D Frame sequence signal and produces the 3D synchronous control signal; The 3D synchronous control signal is connected to infrared 3D signal Synchronization transmitter, and infrared 3D signal Synchronization transmitter sends this synchronizing signal and observes glasses to the infrared control 3D rendering, and 3D rendering observation glasses and 3D rendering sequence are synchronous, can observe 3D rendering clearly.
Consult Fig. 2, fpga chip comprises 3D digital video image processor circuit, the detection of right and left eyes picture synchronization signal and control circuit, high-speed data memory interface circuit, right and left eyes image replacement device circuit, I2c interface circuit and 3D digital video signal output circuit in apparatus of the present invention.
3D digital video image processor circuit receives the 3D digital video signal (YCbCr) of HDMI signal receiving and decoding circuit output, at first digital video signal is sent in the high-speed data memory circuitry (DDR2); Then 3D digital video image processor circuit to the digital of digital video data of storage in the high-speed data memory circuitry (DDR2) according to the needs that show amplify, dwindle, processing such as enhancing, denoising; 3D digital video image processor circuit also the digital of digital video data of storing in the high-speed data memory circuitry is carried out brightness (brightness and contrast's adjustment) and colourity is handled (color enhancing, colour temperature conversion, bandwidth expansion etc.); Right and left eyes image replacement device circuit is inserted the Frame processing according to receiving television set or the receivable optimum frame frequency of display to the 3D digital of digital video data, and carries out the Frame sequence and reset; Last 3D digital video image processor circuit is looked video data to the 3D numeral of storing in high-speed data memory circuitry (DDR2) output buffer and is delivered to 3D digital video output circuit; It is digital rgb or Ycbcr form.
Consult Fig. 4, apparatus of the present invention workflow: after system powered on, microprocessor MCU loaded initialize routine automatically, and entered holding state S0; And whether monitoring HDMI signal receiver has effective 3D vision signal input; No useful signal rests on the S0 state; Effective 3D vision signal is arranged, and s1 then gets the hang of;
The S1 state, microprocessor MCU reads the television set of connection or the DDC of display by the I2C bus, determines the classification of 3D display device, and by calculating, the device MCU that is untreated exports the fpga chip configuration control signal, and s2 gets the hang of;
The S2 state, fpga chip is according to configuration control signal load configurations program from flash, corresponding 3D digital video image processor circuit, the detection of right and left eyes picture synchronization signal and control circuit, high-speed data memory interface circuit, right and left eyes image replacement device circuit, 3D digital video signal output circuit generate, and s3 gets the hang of;
S3 state, 3D digital video image processor circuit receive the 3D digital video signal (YCbCr) of HDMI signal receiving and decoding circuit output, at first digital video signal are sent in the high-speed data memory circuitry (DDR2); Then 3D digital video image processor circuit to the digital of digital video data of storage in the high-speed data memory circuitry (DDR2) according to the needs that show amplify, dwindle, processing such as enhancing, denoising; 3D digital video image processor circuit also the digital of digital video data of storing in the high-speed data memory circuitry is carried out brightness (brightness and contrast's adjustment) and colourity is handled (color enhancing, colour temperature conversion, bandwidth expansion etc.); Right and left eyes image replacement device circuit is inserted the Frame processing according to receiving television set or the receivable optimum frame frequency of display to the 3D digital of digital video data, and carries out the Frame sequence and reset; Last 3D digital video image processor circuit is looked video data to the 3D numeral of storing in high-speed data memory circuitry (DDR2) output buffer and is delivered to 3D digital video output circuit; It is digital rgb or Ycbcr form, 3D video image digit emitter (DVI) or 3D video image analog transmitter (DAC), and final the demonstration is output in external tv machine or display; Simultaneously, programmable chip (FPGA) detects 3D Frame sequence signal and produces the 3D synchronous control signal; The 3D synchronous control signal sends to the infrared control 3D rendering at infrared 3D signal Synchronization transmitter and observes glasses, and 3D rendering observation glasses and 3D rendering sequence are synchronous, can observe 3D rendering clearly.
Claims (2)
1. 3D digital video signal processing method is characterized in that this method may further comprise the steps:
A) connect outside 3D digital video signal source and receive the 3D digital video signal;
B) the 3D digital video signal that receives being carried out format detection, is that television set or display carry out best resolution detection to display unit simultaneously;
C) receive storage 3D digital video signal;
D) the 3D digital video signal spatial domain of butt joint harvesting storage is handled, and makes it become the best resolution of display unit, optimal brightness, best chroma format;
E) the 3D digital video signal time-domain of butt joint harvesting storage is handled, and makes it become the best frame frequency form of display unit;
F) to treated 3D digital video signal output, promptly the 3D digital video signal is processed into displayable 2D image sequence of display unit and output, right and left eyes synchronous control signal output simultaneously.
2. 3D digital video signal processing apparatus is characterized in that this device comprises:
One field programmable gate array chip;
One HDMI 1.4A receiving circuit, connecting field programmable gate array chip is its incoming video signal also;
One microprocessor connects field programmable gate array chip and produces the information exchange signal according to outside input triggering signal;
One infrared 3D signal Synchronization transtation mission circuit connects field programmable gate array chip and connects the infrared control 3D rendering by infrared ray and observe glasses, for it provides infrared right and left eyes synchronizing signal;
One video memory connects field programmable gate array chip, as the 3D video memory;
One 3D video image analog transmitter connects field programmable gate array chip, and the 3D digital video signal of output is transformed into the analog rgb signal, supplies with television set or display and shows;
One 3D digital video transmitter connects field programmable gate array chip, and output 3D digital video signal is supplied with television set or display and shown;
Wherein: described field programmable gate array chip comprises:
One digital video image processor circuit calculates and the processing core as control and 3D digital video signal;
One high-speed data memory interface circuit connects digital video image processor circuit, storage input digit video data Frame, superimposed image data Frame and output 3D digital of digital video data Frame;
One right and left eyes picture synchronization signal detects and control circuit, connects digital video image processor circuit, detects the sequence of left-right images of 3D video player;
One right and left eyes image replacement device circuit connects digital video image processor circuit, and according to the optimum frame frequency that receives the 3D digital of digital video data is inserted Frame and handle, and carries out the Frame sequence and resets;
One 3D digital video signal output circuit is to the output of vision signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010252157 CN101938667A (en) | 2010-08-13 | 2010-08-13 | 3D (Three Dimensional) digital video signal processing method and device thereof |
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| CN 201010252157 CN101938667A (en) | 2010-08-13 | 2010-08-13 | 3D (Three Dimensional) digital video signal processing method and device thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102568514A (en) * | 2012-01-05 | 2012-07-11 | 青岛艾孚高清技术有限公司 | Three-dimensional (3D) high definition multi-media player |
| CN102685439A (en) * | 2012-05-28 | 2012-09-19 | 上海海事大学 | Device and method for realizing image data transmission control with field programmable gate array (FPGA) |
| WO2013071939A2 (en) | 2011-10-11 | 2013-05-23 | Oü Unipower | Method and a system for displaying and watching three-dimensional images on the screen |
| WO2013152531A1 (en) * | 2012-04-09 | 2013-10-17 | 杭州立体世界科技有限公司 | High definition stereoscopic video drive and stereoscopic video conversion method thereof |
| CN108282599A (en) * | 2017-01-04 | 2018-07-13 | 深圳市巨烽显示科技有限公司 | A kind of 3D display device and Endoscope-assisted diagnostic system |
| CN112866677A (en) * | 2019-11-26 | 2021-05-28 | 西安诺瓦星云科技股份有限公司 | Signal emitter and display system |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2013071939A2 (en) | 2011-10-11 | 2013-05-23 | Oü Unipower | Method and a system for displaying and watching three-dimensional images on the screen |
| CN102568514A (en) * | 2012-01-05 | 2012-07-11 | 青岛艾孚高清技术有限公司 | Three-dimensional (3D) high definition multi-media player |
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| WO2013152531A1 (en) * | 2012-04-09 | 2013-10-17 | 杭州立体世界科技有限公司 | High definition stereoscopic video drive and stereoscopic video conversion method thereof |
| CN102685439A (en) * | 2012-05-28 | 2012-09-19 | 上海海事大学 | Device and method for realizing image data transmission control with field programmable gate array (FPGA) |
| CN108282599A (en) * | 2017-01-04 | 2018-07-13 | 深圳市巨烽显示科技有限公司 | A kind of 3D display device and Endoscope-assisted diagnostic system |
| CN112866677A (en) * | 2019-11-26 | 2021-05-28 | 西安诺瓦星云科技股份有限公司 | Signal emitter and display system |
| CN112866677B (en) * | 2019-11-26 | 2023-12-05 | 西安诺瓦星云科技股份有限公司 | Signal transmitter and display system |
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Application publication date: 20110105 |