CN104581109A - 3D digital video signal processing method and device - Google Patents
3D digital video signal processing method and device Download PDFInfo
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- CN104581109A CN104581109A CN201310512507.0A CN201310512507A CN104581109A CN 104581109 A CN104581109 A CN 104581109A CN 201310512507 A CN201310512507 A CN 201310512507A CN 104581109 A CN104581109 A CN 104581109A
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Abstract
The invention discloses a 3D digital video signal processing method and a device thereof, wherein the method comprises the following steps: connecting an external 3D digital video signal source and receiving; detecting the format of the signal; receiving and storing signals; processing the signal space domain: processing the signal time domain and outputting the signal; the device consists of a Field Programmable Gate Array (FPGA) chip, an HDMI1.4A receiving circuit, a Microprocessor (MCU), an infrared 3D signal synchronous transmitting circuit, an image memory, a 3D video image analog transmitter and a 3D video digital transmitter. The invention provides an effective way for displaying 3D digital video, so that the existing television set in the home of a consumer can display 3D images without modification.
Description
Technical field
The present invention relates to 3D Display Technique field, particularly a kind of 3D digital video signal processing method and device thereof.
Background technology
Stereo display technique is the Some Questions To Be Researched showing field at present, it is the main support link of virtual reality technology, it is the primary study direction of message area, its core uses computer graphics, image procossing and optical technology, initial data is converted to figure or image parameter dimensionally shows and can carry out theory, the Method and Technology of interactive process on screen.It relates to many technical fields such as computer graphics, image procossing, computer-aided design, computer vision and man-machine interaction, transducer, automation servo system.The virtual display of 3D is realized by the telepresenc of stereoscopic vision, become one of focus of various countries' research since the eighties in 20th century.The countries and regions such as Japan, Korea S, America and Europe take the lead in starting the basic research of 3D display, and obtain achievement successively in the nineties.In CES exhibitions in 2010, increasing 3D display application product is constantly gushed out in CES2010 exhibition.At present, market there is the 3D Display Technique of 4 kinds of comparative maturities, comprised color solid three-dimensional, polarization two-dimensional, stereoscopic three-dimensional, and DLP-Link technology.
It is the longest that color solid three-dimensional commercially releases the time, and principle is also simple, and cost is minimum.The principle of this technology is fairly simple, and by physics principle, use the filter of different colours to carry out picture optical filtering, make a picture can produce two width images, modal filter color is normally red/blue, red/green, or red/blue or green.
Polarization is three-dimensional compared with color solid 3-D technology, and polarization 3-D technology promotes clearly in the image quality of stereopsis.Add that the combination of anaglyph spectacles realizes 3D effect by Liang Tai projector and two pieces of polarized lenses.The cost also relative moderate of polaroid glasses simultaneously, minimum dozens of yuan just can buy.But the drawback of this kind of technology needs Liang Tai projector, and cost is higher.
Stereoscopic three-dimensional is current our modal a kind of 3D shadow casting technique.Current nearly all 3D movie theatre is all this equipment adopted.Stereoscopic three-dimensional technology mainly have employed the form of frame sequence to produce stereo-picture.Secondly the realization of stereoscopic three-dimensional technology needs three key elements, and first the refresh rate of projected picture needs to reach 120 frames per second, needs an Infrared Projector and one can receive the 3D anaglyph spectacles of infrared signal.
Summary of the invention
The object of the invention is for a large amount of television sets that market is sold in recent years (PDP, LCD projector etc.), it possesses DVI, HDMI or rgb signal interface, but not 3D TV, by a kind of 3D digital video signal processing method and device, this type of television set existing in consumer family need not be reequiped and also can show 3D image, thus save consumer's cost and social resources.
The object of the present invention is achieved like this:
A kind of 3D digital video signal processing method, is characterized in that the method comprises the following steps:
A) connect outside 3D digital video signal source and receive 3D digital video signal;
B) format detection is carried out to the 3D digital video signal received, best resolution detection is carried out to display unit and television set or display simultaneously;
C) storage 3D digital video signal is received;
D) the 3D digital video signal spatial domain process of docking harvesting storage, becomes display unit best resolution, optimal brightness, best chroma format;
E) the 3D digital video signal time-domain process of docking harvesting storage, becomes the best frame frequency form of display unit;
F) export treated 3D digital video signal, namely 3D digital video signal is processed into the displayable 2D image sequence of display unit and exports, and right and left eyes synchronous control signal exports simultaneously.
A kind of 3D apparatus for processing of video signals, this device comprises:
One field programmable gate array (FPGA) chip;
One HDMI1.4A receiving circuit, connecting field programmable gate array (FPGA) chip is also its incoming video signal;
One microprocessor (MCU), connects field programmable gate array (FPGA) chip and produces information exchange signal according to outside input triggering signal;
One infrared 3D signal synchronized transmission circuit, connects field programmable gate array (FPGA) chip and connects infrared control 3D rendering by infrared ray and observe glasses, for it provides infrared right and left eyes synchronizing signal;
One video memory, connects field programmable gate array (FPGA) chip, as 3D video memory;
One 3D video image analog transmitter, connects field programmable gate array (FPGA) chip, and the 3D digital video signal exported is transformed into analog rgb signal, supply television set or display display;
One 3D digital video transmitter, connects field programmable gate array (FPGA) chip, exports 3D digital video signal, supply television set or display display;
Wherein: described field programmable gate array (FPGA) chip comprises:
One digital video image processor circuit, calculates and process core as control and 3D digital video signal;
One high-speed data processing device interface circuit, connects digital video image processor circuit, stores input digital of digital video data frame, superimposed image data frame and exports 3D digital of digital video data frame;
One right and left eyes picture synchronization signal detects and control circuit, connects digital video image processor circuit, detects the sequence of left-right images of 3D video player;
One right and left eyes image resets device circuit, connects digital video image processor circuit, and carries out interleave process according to the optimum frame frequency received to 3D digital of digital video data, carries out frame sequence replacement;
One 3D digital video signal output circuit, to the output of vision signal.
The present invention is that the display of 3D digital video provides a kind of effective way, existing television set in consumer family need not be reequiped and also can show 3D image.
Accompanying drawing explanation
Fig. 1 is apparatus of the present invention structural representation
Fig. 2 is field programmable gate array (FPGA) structured flowchart in apparatus of the present invention
Fig. 3 is the inventive method flow chart
Fig. 4 is apparatus of the present invention workflow diagram
Embodiment
Consult Fig. 3, the concrete steps of the inventive method are:
A) connect outside 3D digital video signal source and receive 3D digital video signal;
B) 3D format digital video signal detects: carry out format detection to the signal from 3D signal source, carry out best resolution detection to display unit (television set or display);
C) 3D digital video signal receives and stores: 3D digital video signal is received and stores;
D) 3D digital video signal spatial domain process: 3D digital video signal processing is become display unit best resolution, optimal brightness, best chroma format;
E) 3D digital video signal time-domain process: 3D digital video signal processing is become the best frame frequency form of display unit;
F) 3D digital video signal exports and the output of right and left eyes synchronous control signal: 2D image sequence 3D digital video signal processing being become display unit (television set or display) to show also exports; Right and left eyes synchronous control signal exports simultaneously.
Consult Fig. 1, apparatus of the present invention HDMI1.4A signal receiver is connected by video bus with field programmable gate array (FPGA) chip, it comprises the video data of 24bit or 30bit width, clock signal, line synchronizing signal, frame synchronizing signal and data effective index signal, the signals such as SCL and SDA; Micro-processor MCV is connected with FPGA by signals such as SCL with SDA;
Video memory is connected with FPGA by signals such as 32bit width data bus and 22bit width address bus and clock controls; Infrared 3D signal synchrotransmitter is connected with FPGA by 1bit data wire; Infrared 3D signal synchrotransmitter is observed glasses by infrared ray and infrared control 3D rendering and is connected; 3D video image digit emitter (DVI) is connected with FPGA by same video bus with 3D video image analog transmitter (DAC), it comprises the video data of 24bit or 30bit width, clock signal, line synchronizing signal, frame synchronizing signal and data effective index signal, the signals such as SCL and SDA; 3D video image digit emitter (DVI) is connected with television set or display by DVI cable; 3D video image analog transmitter (DAC) is connected with television set or display by simulation 75 ohm of RGB cables.
The signal input port of apparatus of the present invention connects HDMI (DVI) interface of outside 3D video signal source (BD-player, DVD-player or PC) by HDMI holding wire, output (DVI or RGB) is connected to a television set or display, viewers wear 3D glasses, form a 3D display system.
Hardware configuration code (software) burning, in FPGA configuring chip, is loaded into after powering in programmable chip (FPGA) automatically.
HDMI1.4A signal receiver is connected with MCU by I2c bus, and under MCU controls, enforcement receives the TMDS differential signal that outside 3D video signal source (BD-player, DVD-player or PC etc.) inputs and is decoded into RGB digital video signal or the YCbcr digital video signal of numeral 24 or 30 bit widths; Its may be 24Hz frame-packing, side-by-side, also may be top-and-bottom; It can support that speed is up to the decoding of the signal of high-definition digital video line by line (1080p60hz) of 148.5MHz.
Fpga chip receives RGB digital video signal or the YCbcr digital video signal of the output of HDMI signal receiving and decoding circuit, and digital video signal is sent to video memory circuit, fpga chip completes the dynamic and static various process of video image, and arrive with digital rgb or Ycbcr formatted output, 3D video image digit emitter (DVI) or 3D video image analog transmitter (DAC), final display translation is connected to external television or display by DVI line; Meanwhile, fpga chip detects 3D frame sequence signal and produces 3D synchronous control signal; 3D synchronous control signal is connected to infrared 3D signal synchrotransmitter, and infrared 3D signal synchrotransmitter sends this synchronizing signal and observes glasses to infrared control 3D rendering, and 3D rendering observes glasses and 3D rendering sequence synchronization, can observe 3D rendering clearly.
Consult Fig. 2, in apparatus of the present invention, fpga chip comprises 3D digital video image processor circuit, right and left eyes picture synchronization signal detects and control circuit, high-speed data processing device interface circuit, right and left eyes image replacement device circuit, I2c interface circuit and 3D digital video signal output circuit.
3D digital video image processor circuit receives the 3D digital video signal (YCbCr) that HDMI signal receiving and decoding circuit exports, and first digital video signal is sent in high-speed data processing device circuit (DDR2); Then 3D digital video image processor circuit the digital of digital video data stored in high-speed data processing device circuit (DDR2) amplified according to the needs of display, reduce, strengthen, the process such as denoising; 3D digital video image processor circuit also carries out brightness (brightness and contrast's adjustment) and colourity process (color enhancement, color conversion, bandwidth broadning etc.) to the digital of digital video data stored in high-speed data processing device circuit; Right and left eyes image resets device circuit and carries out interleave process according to reception television set or the receivable optimum frame frequency of display to 3D digital of digital video data, and carries out frame sequence replacement; Last 3D digital video image processor circuit delivers to 3D digital video output circuit the 3D numeral stored in high-speed data processing device circuit (DDR2) output buffer depending on video data; It is digital rgb or Ycbcr form.
Consult Fig. 4, apparatus of the present invention workflow: after system electrification, Micro-processor MCV automatic loading initialize routine, and enter holding state S0; And monitor HDMI signal receiver and whether have effective 3D vision signal to input; Without useful signal, rest on S0 state; Have effective 3D vision signal, then get the hang of s1;
S1 state, Micro-processor MCV reads the DDC of television set or the display connected by I2C bus, determines the classification of 3D display device, and by calculating, untreated device MCU exports fpga chip configuration control signal, and get the hang of s2;
S2 state, fpga chip is according to configuration control signal load configurations program from flash, corresponding 3D digital video image processor circuit, right and left eyes picture synchronization signal detect and control circuit, high-speed data processing device interface circuit, right and left eyes image resets device circuit, 3D digital video signal output circuit generates, and get the hang of s3;
S3 state, 3D digital video image processor circuit receives the 3D digital video signal (YCbCr) that HDMI signal receiving and decoding circuit exports, and first digital video signal is sent in high-speed data processing device circuit (DDR2); Then 3D digital video image processor circuit the digital of digital video data stored in high-speed data processing device circuit (DDR2) amplified according to the needs of display, reduce, strengthen, the process such as denoising; 3D digital video image processor circuit also carries out brightness (brightness and contrast's adjustment) and colourity process (color enhancement, color conversion, bandwidth broadning etc.) to the digital of digital video data stored in high-speed data processing device circuit; Right and left eyes image resets device circuit and carries out interleave process according to reception television set or the receivable optimum frame frequency of display to 3D digital of digital video data, and carries out frame sequence replacement; Last 3D digital video image processor circuit delivers to 3D digital video output circuit the 3D numeral stored in high-speed data processing device circuit (DDR2) output buffer depending on video data; It is digital rgb or Ycbcr form, 3D video image digit emitter (DVI) or 3D video image analog transmitter (DAC), and final display translation is in external tv machine or display; Meanwhile, programmable chip (FPGA) detects 3D frame sequence signal and produces 3D synchronous control signal; 3D synchronous control signal is sent to infrared control 3D rendering at infrared 3D signal synchrotransmitter and observes glasses, and 3D rendering observes glasses and 3D rendering sequence synchronization, can observe 3D rendering clearly.
Claims (2)
1. a 3D digital video signal processing method, is characterized in that the method comprises the following steps:
A) connect outside 3D digital video signal source and receive 3D digital video signal;
B) format detection is carried out to the 3D digital video signal received, best resolution detection is carried out to display unit and television set or display simultaneously;
C) storage 3D digital video signal is received;
D) the 3D digital video signal spatial domain process of docking harvesting storage, becomes display unit best resolution, optimal brightness, best chroma format;
E) the 3D digital video signal time-domain process of docking harvesting storage, becomes the best frame frequency form of display unit;
F) export treated 3D digital video signal, namely 3D digital video signal is processed into the displayable 2D image sequence of display unit and exports, and right and left eyes synchronous control signal exports simultaneously.
2. a 3D digital video signal processing apparatus, is characterized in that this device comprises:
One field programmable gate array chip;
One HDMI1.4A receiving circuit, connecting field programmable gate array chip is also its incoming video signal;
One microprocessor, connects field programmable gate array chip and produces information exchange signal according to outside input triggering signal.
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| CN201310512507.0A CN104581109A (en) | 2013-10-25 | 2013-10-25 | 3D digital video signal processing method and device |
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| CN201310512507.0A CN104581109A (en) | 2013-10-25 | 2013-10-25 | 3D digital video signal processing method and device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105430495A (en) * | 2015-11-25 | 2016-03-23 | Tcl集团股份有限公司 | Method and system for processing module TV video signal |
| CN105491369A (en) * | 2016-01-12 | 2016-04-13 | 深圳多哚新技术有限责任公司 | VR video data processing system |
-
2013
- 2013-10-25 CN CN201310512507.0A patent/CN104581109A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105430495A (en) * | 2015-11-25 | 2016-03-23 | Tcl集团股份有限公司 | Method and system for processing module TV video signal |
| CN105430495B (en) * | 2015-11-25 | 2019-04-16 | Tcl集团股份有限公司 | A kind of method and system of module TV 3D video frequency signal processing |
| CN105491369A (en) * | 2016-01-12 | 2016-04-13 | 深圳多哚新技术有限责任公司 | VR video data processing system |
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