CN101937841A - Method and structure for reducing grid resistance of power MOSFET (metal oxide semiconductor field-effect transistor) - Google Patents
Method and structure for reducing grid resistance of power MOSFET (metal oxide semiconductor field-effect transistor) Download PDFInfo
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- CN101937841A CN101937841A CN2009100575328A CN200910057532A CN101937841A CN 101937841 A CN101937841 A CN 101937841A CN 2009100575328 A CN2009100575328 A CN 2009100575328A CN 200910057532 A CN200910057532 A CN 200910057532A CN 101937841 A CN101937841 A CN 101937841A
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Abstract
The invention discloses a method and structure for reducing the grid resistance of a power metal oxide semiconductor field-effect transistor (MOSFET). The method comprises the following steps: etching a polysilicon gate groove; growing a silicon dioxide layer; back-etching the silicon dioxide layer so as to form a clearance protection on gate oxides on the top of the polysilicon gate groove; growing a titanium layer; and carrying out rapid thermal annealing on the titanium layer so as to form titanium silicides. Based on the technology of an original power MOS device, in the invention, the grid resistance is only on the level of metal resistance and the grid resistance of the power MOSFET is reduced without adding additional photo-masks and by increasing little cost and forming the titanium silicides, thereby improving the operating frequency of the power MOSFET, obtaining a power MOSFET with faster response speed and increasing the properties of the power MOSFET greatly.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method and structure of power field effect transistor.
Background technology
Before the power field effect transistor invention, have only the power bipolar transistor in high speed, medium power range, to use.The power bipolar transistor was invented in phase early 1950s, constantly perfect along with technology, and people can produce operating current amperes up to a hundred, withstand voltage bipolar power transistor up to 600 volts.
But there are some defectives in essence in the bipolar power transistor service behaviour.At first, bipolar power transistor is a current control device, needs a very big base current to guarantee that it is stabilized in a certain operating state, is generally 1/5～1/10 of collector current.Thereby, just need a bigger reverse base drive electric current in order to obtain high speed turn-off speed.These characteristics make its base drive circuit unusual complicated and expensive.Secondly, add at the same time under big electric current and the high-tension situation, also be easy to generate the second breakdown failure phenomenon at bipolar transistor.In addition, be difficult in design the bipolar power component unit is together in parallel, the forward voltage drop that loads on the bipolar transistor descends along with the rising of temperature, causes electric current to be diverted on certain device, causes this components from being damaged.
In order to solve the limitation on the above-mentioned bipolar power component performance, people developed power field effect transistor (MOS) in 1970.In power field effect transistor, control signal is added on the gate electrode, and gate electrode and semiconductor surface are kept apart by one deck dielectric (being generally silicon dioxide).Required control signal only is a bias voltage, works or does not have when closing constant electric current to flow.Even under the 100KHz condition of work, when device state changed, grid current only provided a very little gate capacitance charging and the electric current of discharge.Simultaneously, its grid drive circuit has also been simplified in the high input impedance of MOS greatly.
Opposite with bipolar power component, MOS is an one pole type device.Electric current is formed by the majority carrier transmission, does not have electronics to inject phenomenon, thereby when device turn-offs, does not have the storage of electronics and the time delay phenomenon that electron recombination causes.The switching speed that MOS had is than the high several magnitude of speed of bipolar transistor.This specific character is particularly noticeable at the high frequency power circuit, because under this condition of work, the power loss of switch is most important.MOS adds under big electric current and the high-tension condition at the same time, shows superior trouble free service performance, promptly can bear big electric current and high-tension impact over a period to come and does not take place because the destructiveness brought of second breakdown lost efficacy.The design that can be arranged in parallel at an easy rate of what is more important, MOS unit, this is because the forward voltage drop on the MOS increases along with the rising of temperature.This specific character makes electric current uniform distribution between the device of parallel connection.
Just because of these advantages of MOS, make it be widely used in computer, mobile phone, sound equipment, automobile circuit, radio circuit, and among the high frequency power switched power supply.
And discharge and recharge the computing formula of time by MOS
As can be known, for the channel power MOS device, influencing the device operating frequency has two key factors, and the one, resistance, the 2nd, grid oxygen electric capacity.Reduce electric capacity or resistance, can both make the time that discharges and recharges of device short more, the operating frequency of device is also just high more.As shown in Figure 1, for the adjustment of resistance, usual method just changes its doping content.The effect that changes this method raising of its doping content operating frequency is unsatisfactory, can't reduce resistance significantly.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method that reduces the power field effect transistor resistance, can be on the technology basis of original power MOS (Metal Oxide Semiconductor) device, do not increase extra light shield, increase few cost, reduce the power field effect transistor resistance, thereby improve the operating frequency of power field effect transistor, the speed that meets with a response is power field effect transistor faster, and the power field effect transistor performance is significantly promoted.
In order to solve above technical problem, the invention provides a kind of method that reduces the power field effect transistor resistance; May further comprise the steps: step 1, etch polysilicon grid groove; Step 2, growth layer of silicon dioxide layer; Step 3, return to carve described silicon dioxide layer, form gap protection at grid groove top gate oxide place; Step 4, growth one deck titanium coating; Step 5, carry out rapid thermal annealing, form the titanium silicide.
Beneficial effect of the present invention is: on the technology basis of original power MOS (Metal Oxide Semiconductor) device, do not increase extra light shield, increase few cost, by forming the titanium silicide, make resistance only be the resistance magnitude of metal, reduce the power field effect transistor resistance, thereby improve the operating frequency of power field effect transistor, the speed that meets with a response is power field effect transistor faster, and the power field effect transistor performance is significantly promoted.
The present invention also provides a kind of structure that reduces the power field effect transistor resistance; Comprise source electrode, trap and drain electrode; Between source electrode and drain electrode, grid is arranged; There is gate oxide partly to surround described grid; Titanium silicide is arranged at the top at described grid; Between described Titanium silicide and the described gate oxide silicon dioxide gap protection is arranged.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is existing groove type power field-effect transistor structure generalized section;
Fig. 2 is the described power field effect transistor structural profile of an embodiment of the invention schematic diagram;
Fig. 3 is the flow chart of the described method of the embodiment of the invention.
Embodiment
The method of reduction power field effect transistor resistance of the present invention; May further comprise the steps:
Step 1, when the grid polycrystalline silicon etching, carve the darker groove of relative common power field effect transistor, the degree of depth of described groove is approximately 1500～3000 dusts; This step was carried out before injection of trap (Well) ion and the injection of source (Source) ion; Do injection of trap (Well) ion and the injection of source (Source) ion by normal process then.
Compare with present known polysilicon gate groove, structure is the same substantially, but polysilicon gate groove of the present invention is darker than the polysilicon gate groove of present known power MOS (Metal Oxide Semiconductor) device, and doing like this is to give the following titanium silicide that will form in order to reserve some spaces.
Step 2, finish that trap (Well) ion injects and after source (Source) ion injects, with the certain thickness silicon dioxide of method growth one deck of chemical vapor deposition according to step 1 is described.The thickness of this layer silicon dioxide can be 1500～2500 dusts.
Step 3, return with dry etching and to carve described silicon dioxide layer, form gap protection at grid groove top gate oxide place;
Method growth one deck titanium coating of step 4, usefulness physical vapor deposition; The thickness of this titanium coating can be 300～500 dusts.
Step 5, carry out rapid thermal annealing twice, form the titanium silicide.
A distortion of the present invention is can carry out source ion earlier to inject, and injects one step of back increase grid polycrystalline silicon etching at source ion and carves a darker groove
The present invention also provides a kind of structure that reduces the power field effect transistor resistance simultaneously; Comprise source electrode, trap and drain electrode; Between source electrode and drain electrode, grid is arranged; There is gate oxide partly to surround described grid; Titanium silicide is arranged at the top at described grid; Between described Titanium silicide and the described gate oxide silicon dioxide gap protection is arranged.
Main points of the present invention are long layer of metal silicide layer on grid polycrystalline silicon, make resistance only be the resistance magnitude of metal, and discharge and recharge the computing formula of time according to MOS
As can be known, reduce resistance after, can both make the time that discharges and recharges of device short more, the operating frequency of device is also just high more.
The present invention is not limited to execution mode discussed above.More than the description of embodiment is intended in order to describe and illustrate the technical scheme that the present invention relates to.Based on the conspicuous conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches purpose of the present invention.
Claims (9)
1. method that reduces the power field effect transistor resistance; It is characterized in that, may further comprise the steps:
Step 1, etch polysilicon grid groove;
Step 2, growth layer of silicon dioxide layer;
Step 3, return to carve described silicon dioxide layer, form gap protection at grid groove top gate oxide place;
Step 4, growth one deck titanium coating;
Step 5, carry out rapid thermal annealing, form the titanium silicide.
2. the method for reduction power field effect transistor resistance as claimed in claim 1; It is characterized in that, in described step 2, use the method growthing silica layer of chemical vapor deposition.
3. the method for reduction power field effect transistor resistance as claimed in claim 1; It is characterized in that, in described step 3, carry out returning of silicon dioxide layer and carve with dry etching.
4. the method for reduction power field effect transistor resistance as claimed in claim 1; It is characterized in that, in described step 4, use the method growing metal titanium layer of physical vapor deposition.
5. the method for reduction power field effect transistor resistance as claimed in claim 1; It is characterized in that, in described step 5, carry out rapid thermal annealing twice.
6. the method for reduction power field effect transistor resistance as claimed in claim 1; It is characterized in that in described step 1, the thickness of etch polysilicon grid groove is 1500～3000 dusts.
7. the method for reduction power field effect transistor resistance as claimed in claim 1; It is characterized in that in described step 2, the thickness of described silicon dioxide layer is 1500～2500 dusts.
8. the method for reduction power field effect transistor resistance as claimed in claim 1; Be characterised in that in described step 4, the thickness of titanium coating is 300～500 dusts.
9. reduce the structure of power field effect transistor resistance; Comprise source electrode, trap and drain electrode;
Between source electrode and drain electrode, grid is arranged;
There is gate oxide partly to surround described grid;
It is characterized in that Titanium silicide being arranged at the top of described grid;
Between described Titanium silicide and the described gate oxide silicon dioxide gap protection is arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100575328A CN101937841A (en) | 2009-07-02 | 2009-07-02 | Method and structure for reducing grid resistance of power MOSFET (metal oxide semiconductor field-effect transistor) |
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| CN2009100575328A CN101937841A (en) | 2009-07-02 | 2009-07-02 | Method and structure for reducing grid resistance of power MOSFET (metal oxide semiconductor field-effect transistor) |
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| CN101937841A true CN101937841A (en) | 2011-01-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403210A (en) * | 2011-11-29 | 2012-04-04 | 无锡中微晶园电子有限公司 | Process for self alignment of previously non-crystallized filled high temperature Ti on silicide |
| CN102800704A (en) * | 2012-08-29 | 2012-11-28 | 上海宏力半导体制造有限公司 | Trench MOS (Metal Oxide Semiconductor) transistor and manufacture method thereof, and integrated circuit |
-
2009
- 2009-07-02 CN CN2009100575328A patent/CN101937841A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403210A (en) * | 2011-11-29 | 2012-04-04 | 无锡中微晶园电子有限公司 | Process for self alignment of previously non-crystallized filled high temperature Ti on silicide |
| CN102800704A (en) * | 2012-08-29 | 2012-11-28 | 上海宏力半导体制造有限公司 | Trench MOS (Metal Oxide Semiconductor) transistor and manufacture method thereof, and integrated circuit |
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Application publication date: 20110105 |