CN101937720A - Test system of high-speed dynamic random access memory - Google Patents
Test system of high-speed dynamic random access memory Download PDFInfo
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- CN101937720A CN101937720A CN 201010165054 CN201010165054A CN101937720A CN 101937720 A CN101937720 A CN 101937720A CN 201010165054 CN201010165054 CN 201010165054 CN 201010165054 A CN201010165054 A CN 201010165054A CN 101937720 A CN101937720 A CN 101937720A
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- dynamic ram
- test macro
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Abstract
The invention discloses a test system of a high-speed dynamic random access memory. The test system comprises a test device which comprises a mainboard, a drive board connected with the mainboard, and an adaptation board connected with the drive board, wherein the drive board is connected with the adaptation board through a coaxial cable, and the mainboard outputs high-frequency signals to the drive board and then the drive board outputs the high-frequency signals to the adaptation board through the coaxial cable. The test system has the characteristics of small high-frequency test signal attenuation, low manufacturing and maintenance costs and high performance.
Description
[technical field]
The invention belongs to the high-frequency digital field tests, particularly a kind of high speed dynamic RAM test macro.
[background technology]
Development of computer proposes higher requirement to the travelling speed and the memory space of stochastic and dynamic storer, is to guarantee the reliable condition precedent of operation effectively of computer system and every electricity function index of storer is tested accurately.Along with improving constantly of dynamic RAM frequency of operation, for the difficulty of test and the also increase thereupon of testing cost of storer and memory module.In fact, along with the frequency of operation of high speed dynamic RAM is more and more higher, also more harsh for the requirement of the framework of testing apparatus and electric property thereof.
[summary of the invention]
In order to solve the above-mentioned technical matters of prior art, be necessary to provide a kind of low cost and high performance high speed dynamic RAM test macro.
The present invention solves the technical scheme that existing technical matters adopts: a kind of high speed dynamic RAM test macro, comprise testing apparatus, described testing apparatus comprises mainboard, drive plate that is connected with mainboard and the adaptation board that is connected with drive plate, connect by concentric cable between described drive plate and the adaptation board, described mainboard output high-frequency signal outputs to described adaptation board by concentric cable behind drive plate.
In a kind of high speed dynamic RAM of the present invention test macro, described testing apparatus quantity is at least one, and described testing apparatus is connected to computing machine by USB (universal serial bus).
In a kind of high speed dynamic RAM of the present invention test macro, described mainboard comprises the programmable processor that is used to produce the high-frequency test signal, and described programmable processor is connected with drive plate.
In a kind of high speed dynamic RAM of the present invention test macro, described mainboard also comprises the delay calibration circuit, described programmable processor connects described drive plate via described delay calibration circuit, and described delay calibration circuit is used for the high-frequency signal of programmable processor output is postponed to handle.
In a kind of high speed dynamic RAM of the present invention test macro, described programmable processor comprises a plurality of signal generating units and the also string/deserializer that is connected with described a plurality of signal generating units, and described programmable processor adopts multiple programming
In a kind of high speed dynamic RAM of the present invention test macro, the clock treatment circuit that described mainboard also comprises clock generator and is used for the clock signal of clock generator output is handled.
In a kind of high speed dynamic RAM of the present invention test macro, described drive plate comprises driver and comparer, and described concentric cable one end is connected to driver, and the other end connects described adaptation board.
In a kind of high speed dynamic RAM of the present invention test macro, described adaptation board comprises slot, described concentric cable is connected to slot by the RF connector, and tested device also is connected to slot when test, and test signal outputs to tested device by concentric cable.
In a kind of high speed dynamic RAM of the present invention test macro, described slot position can be adjusted according to tested device dimensions difference.
Described drive plate number is for being at least two, and described at least two drive plates are erect and are arranged on the described mainboard, and described adaptation board both sides connect at least two drive plates by connector respectively.
Compared to prior art, a kind of high speed dynamic RAM of the present invention test macro adopts concentric cable inlet wire high-frequency signal transmission, has effectively avoided the high-frequency signal that the harmful effect of circuit board via, cabling and electromagnetic interference (EMI) causes in prior art decay.And the employing concentric cable can freely be adjusted the position of slot, thereby satisfies the tested device testing requirement of different specification size.In addition, the present invention adopts the split design of mainboard, drive plate and adaptation board, can effectively improve practicality of the present invention and reduce maintenance cost.Such as, when needs test different components, as memory chip and memory module, because the specification difference of tested device only needs to change adaptation board and gets final product.In addition, adopt the split design,, only need to change corresponding circuit board and get final product, and do not need as needing to change whole testing apparatus in the prior art if mainboard, drive plate and an adaptation board part break down.In addition, adopt the structure of driver and comparer, easily test signal voltage and sequential.Therefore, a kind of high speed dynamic RAM of the present invention test macro has lower cost and superior performance.The present invention has solved the difficult problem that the high-frequency digital test is faced from framework and test circuit.
[description of drawings]
Fig. 1 is the block diagram of a kind of high speed dynamic RAM of the present invention test macro one better embodiment.
Fig. 2 is the schematic perspective view of testing apparatus shown in Figure 1.
Fig. 3 is that the sequential of high speed dynamic RAM test macro shown in Figure 1 is adjusted block diagram.
Fig. 4 is the block diagram of programmable processor shown in Figure 1.
[embodiment]
Be described in further detail below in conjunction with accompanying drawing and embodiments of the present invention.
Seeing also Fig. 1, is the block diagram of a kind of high speed dynamic RAM of the present invention test macro one better embodiment.Described high speed dynamic RAM test macro 10 comprises computing machine 11 and a plurality of testing apparatuss 20 that are connected by USB (universal serial bus) (USB) with computing machine 11.Described computing machine 11 comprises the special test interface, and the tester can obtain test result by described computing machine 11.
Seeing also Fig. 2, is the schematic perspective view of testing apparatus 20 shown in Figure 1.Described testing apparatus 20 comprises that mainboard 21, drive plate 22, adaptation board 23 are connected the cable 200 of drive plate 22 and adaptation board 23 with many.In the present embodiment, described drive plate 22 numbers are two, and are erected at mainboard 21 both sides respectively.Described adaptation board 23 both sides are connected with described drive plate 22 by connector 24 respectively.Described mainboard 21 is connected to computing machine 11 by USB.In the change embodiment of the present invention, the number of drive plate 22 is one or more,
Described mainboard 21 comprises programmable processor 30, clock generator 40, clock treatment circuit 50 and delay calibration circuit 60.Described drive plate 22 comprises driver/comparer 221.Described adaptation board 23 comprises slot 25.Described cable 200 1 ends are connected to driver/comparer 221, and the other end is connected to slot 25 by the RF connector.In the present embodiment, described adaptation board 23 comprises two slots 25, and (device under testing DUT) is connected on the slot 25 as memory chip or module tested device.Described cable 200 is concentric cable.In other change embodiments, the quantity of slot 25 is not limited to, and can be one or more.
Because adopted cable 200 to connect DUT and drive plate 22, when testing, the slot 25 of adaptation board 23 can be according to DUT dimension width free adjustment position.Because cable 200 adopts concentric cable, can bear greater than the radio-frequency signal transmission of 12GHz and almost do not have signal attenuation.In addition, doing the testing apparatus timing, be concentric cable need be connected between RF connector (radio frequency (RF) coaxial connector) and the oscillograph accurately to calibrate, and need not CRO coupling.In the present embodiment, described drive plate 22 also comprises driver/comparer 221, can carry out driving voltage, reference voltage and sequential setting to each test loop, thus test signal voltage very easily.
Because high-frequency signal in the circuit transmission course decay takes place very easily and sequential is inconsistent,, need that the sequential of assurance signal is consistent to seem particularly important for example for high-frequency signal test greater than 2GHz.Please consulting Fig. 3 simultaneously, is the time sequence adjusting circuit synoptic diagram of high speed dynamic RAM test macro shown in Figure 1.The high-frequency signal that described programmable processor 30 produces outputs to delay calibration circuit 60, and delay calibration circuit 60 carries out outputing to after the delay process driver 221 and and then is transported to DUT the high-frequency signal of each passage.Calibrate by 60 pairs of signal sequences of delay calibration circuit, make the high-frequency signal that is transported to DUT have consistance preferably.Deliver to the signal of programmable processor 30 for DUT and can do same processing, make it have sequential consistance preferably.
Please consulting Fig. 4 simultaneously, is the block diagram of programmable processor 30 shown in Figure 1.Described programmable processor 30 comprises a plurality of signal generating units 31 and and string/deserializer 32.Described a plurality of signal generating unit 31 produces the signal of certain frequency respectively and outputs to parallel-to-serial converter 32, and a plurality of signals that described parallel-to-serial converter 32 will receive are as parallel input, and the high-frequency signal of exporting a serial is to postponing calibration circuit.Described programmable processor 30 adopts this structure, effectively utilize a plurality of low frequency signals to generate the required high-frequency signal of test, for example for the test of the DUT of 1.6GHz frequency of operation, the frequency test signal that programmable processor produces only needs 800MHz or 400MHz (adopting 4 400MHz signal generating units 31) etc. to get final product.In like manner can be from DUT to the programmable processor 30 reverse operation principle, the multichannel low frequency signals is gone here and there and changed and export to high-frequency signal after DUT turns back to programmable processor 30.
Described clock generator 40 is connected with described clock treatment circuit 50, directly provides high-precision DQS signal by clock treatment circuit 50.By programmable processor output DQS signal, described clock treatment circuit 50 (fan out circuit) can provide the DQS signal of low jitter (jitter) compared to prior art.
Compared to prior art, a kind of high speed dynamic RAM of the present invention test macro 10 adopts concentric cable inlet wire high-frequency signal transmission, has effectively avoided the high-frequency signal that the harmful effect of circuit board via, cabling and electromagnetic interference (EMI) causes in prior art decay.And, can freely adjust the position of slot 25, thereby satisfy the DUT testing requirement of different specification size because cable 200 is concentric cable.In addition, the present invention adopts the split design of mainboard 21, drive plate 22 and adaptation board 23, can effectively improve practicality of the present invention and reduce maintenance cost.Such as, when needs test different components, as memory chip and internal memory module, because the specification difference of DUT only needs to change adaptation board 23 and gets final product.In addition, adopt the split design,, only need to change corresponding circuit board and get final product, and do not need as needing to change whole testing apparatus in the prior art if mainboard 21, drive plate 22 and adaptation board 23 certain part break down.In addition, adopt the structure of driver and comparer, can easily obtain the state of signal voltage and sequential.Therefore, a kind of high speed dynamic RAM of the present invention test macro has lower cost and superior performance.The present invention has solved the difficult problem that the high-frequency digital test is faced from framework and test circuit.
Above content be in conjunction with concrete preferred implementation to further describing that the present invention did, can not assert that concrete enforcement of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. high speed dynamic RAM test macro, it is characterized in that: comprise testing apparatus, described testing apparatus comprises mainboard, drive plate that is connected with mainboard and the adaptation board that is connected with drive plate, connect by concentric cable between described drive plate and the adaptation board, described mainboard output high-frequency signal outputs to described adaptation board by concentric cable behind drive plate.
2. high speed dynamic RAM test macro according to claim 1 is characterized in that: described testing apparatus quantity is at least one, and described testing apparatus is connected to computing machine by USB (universal serial bus).
3. high speed dynamic RAM test macro according to claim 2, it is characterized in that: described mainboard comprises the programmable processor that is used to produce the high-frequency test signal, described programmable processor is connected with drive plate.
4. high speed dynamic RAM test macro according to claim 3, it is characterized in that: described mainboard further comprises the delay calibration circuit, described programmable processor connects described drive plate via described delay calibration circuit, and described delay calibration circuit is used for the high-frequency signal of programmable processor output is postponed to handle.
5. high speed dynamic RAM test macro according to claim 4, it is characterized in that: described programmable processor comprises a plurality of signal generating units and the also string/deserializer that is connected with described a plurality of signal generating units, and described programmable processor adopts multiple programming.
6. high speed dynamic RAM test macro according to claim 5 is characterized in that: the clock treatment circuit that described mainboard further comprises clock generator and is used for the clock signal of clock generator output is handled.
7. high speed dynamic RAM test macro according to claim 6, it is characterized in that: described drive plate comprises driver/comparer, and described concentric cable one end is connected to driver/comparer, and the other end connects described adaptation board.
8. high speed dynamic RAM test macro according to claim 7, it is characterized in that: described adaptation board comprises slot, described concentric cable is connected to slot by the RF connector, tested device also is connected to slot when test, test signal outputs to tested device by concentric cable.
9. high speed dynamic RAM test macro according to claim 8 is characterized in that: described slot position can be adjusted according to tested device dimensions difference.
10. high speed dynamic RAM test macro according to claim 8, it is characterized in that: described drive plate number is for being at least two, described at least two drive plates are erect and are arranged on the described mainboard, and described adaptation board both sides connect at least two drive plates by connector respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201010165054 CN101937720A (en) | 2010-05-07 | 2010-05-07 | Test system of high-speed dynamic random access memory |
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| CN 201010165054 CN101937720A (en) | 2010-05-07 | 2010-05-07 | Test system of high-speed dynamic random access memory |
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| CN 201010165054 Pending CN101937720A (en) | 2010-05-07 | 2010-05-07 | Test system of high-speed dynamic random access memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108140418A (en) * | 2015-10-30 | 2018-06-08 | 德州仪器公司 | For the effective parallel test data path of area of in-line memory |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1370997A (en) * | 2001-02-16 | 2002-09-25 | 株式会社爱德万测试 | Regular calibration method and device for integrated circuit testing unit |
| CN1886664A (en) * | 2003-11-26 | 2006-12-27 | 爱德万测试株式会社 | Apparatus for testing a device with a high frequency signal |
| WO2009011033A1 (en) * | 2007-07-17 | 2009-01-22 | Advantest Corporation | Testing apparatus, circuit apparatus and program |
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- 2010-05-07 CN CN 201010165054 patent/CN101937720A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1370997A (en) * | 2001-02-16 | 2002-09-25 | 株式会社爱德万测试 | Regular calibration method and device for integrated circuit testing unit |
| CN1886664A (en) * | 2003-11-26 | 2006-12-27 | 爱德万测试株式会社 | Apparatus for testing a device with a high frequency signal |
| WO2009011033A1 (en) * | 2007-07-17 | 2009-01-22 | Advantest Corporation | Testing apparatus, circuit apparatus and program |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108140418A (en) * | 2015-10-30 | 2018-06-08 | 德州仪器公司 | For the effective parallel test data path of area of in-line memory |
| CN108140418B (en) * | 2015-10-30 | 2022-03-25 | 德州仪器公司 | Area efficient parallel test data path for embedded memory |
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Application publication date: 20110105 |