CN216013584U

CN216013584U - Signal interface self-loop testing device and system based on FMC standard

Info

Publication number: CN216013584U
Application number: CN202121127824.7U
Authority: CN
Inventors: 郑国�; 王保兴; 王萌; 孙恩元
Original assignee: Hunan Econavi Technology Co Ltd
Current assignee: Hunan Econavi Technology Co Ltd
Priority date: 2021-05-24
Filing date: 2021-05-24
Publication date: 2022-03-11
Anticipated expiration: 2031-05-24

Abstract

The utility model provides a signal interface self-loop test device based on an FMC standard, which comprises an FMC loop test card, wherein an FMC connector is arranged on the FMC loop test card, a signal end and a clock end of the FMC connector are respectively connected with a tested FPGA (field programmable gate array), a sending interface and a receiving interface of the signal end are mutually connected, a sending interface and a receiving interface of the clock end are mutually connected to realize self-loop test, the tested FPGA is arranged on an FPGA test carrier plate, a power module and a clock module are arranged on the FPGA test carrier plate, and the power module and the clock module are respectively connected with the tested FPGA. The FMC loop test card adopts a passive design, reduces the complexity of schematic diagram design and PCB design, thereby reducing the design cost of a test device and the production cost of the test device, increasing the reliability of the test device and reducing the influence on the electrical performance of a carrier plate.

Description

Signal interface self-loop testing device and system based on FMC standard

Technical Field

The utility model relates to the technical field of communication, in particular to a self-loop testing device and a system of a signal interface based on an FMC standard.

Background

In recent years, the adoption of modular design in product design has become a basic standard, and the FMC standard is the most common modular design interface for processing cards with FPGAs as core chips, so that the market has a demand for developing, debugging and mass production test devices for FMC interfaces.

As shown in fig. 1, a general FMC loop test card needs to provide additional components such as a clock circuit, thereby increasing the volume of the FMC loop test card, improving the design complexity of the FMC loop test card and increasing the manufacturing cost.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the utility model is as follows: aiming at the technical problems in the prior art, the utility model provides a signal interface self-loop test device and a system based on an FMC standard.

In order to solve the technical problems, the technical scheme provided by the utility model is as follows:

a signal interface self-loop testing device based on an FMC standard comprises an FMC loop testing card, wherein an FMC connector is arranged on the FMC loop testing card, a signal end and a clock end of the FMC connector are respectively connected with a tested FPGA, a sending interface and a receiving interface of the signal end are mutually connected, a sending interface and a receiving interface of the clock end are mutually connected to achieve self-loop testing, the tested FPGA is installed on an FPGA testing carrier plate, a power module and a clock module are arranged on the FPGA testing carrier plate, and the power module and the clock module are respectively connected with the tested FPGA.

Furthermore, the receiving interface of the clock end comprises a high-speed clock receiving interface, the transmitting interface of the clock end comprises a high-speed clock transmitting interface, the high-speed clock receiving interface and the high-speed clock transmitting interface are respectively connected with corresponding interfaces on the tested FPGA, and the high-speed clock receiving interface and the high-speed clock transmitting interface are also connected with each other, so that a high-speed clock interface test loop is formed.

Furthermore, the receiving interface of the signal end comprises a high-speed serial receiving interface, the sending interface of the signal end comprises a high-speed serial sending interface, the high-speed serial receiving interface and the high-speed serial sending interface are connected with each other, and meanwhile, the high-speed serial receiving interface and the high-speed serial sending interface are respectively connected with corresponding interfaces on the tested FPGA, so that a high-speed serial interface test loop is formed.

Furthermore, the receiving interface of the signal end further comprises a universal signal receiving interface, the sending interface of the signal end further comprises a universal signal sending interface, the universal signal receiving interface and the universal signal sending interface are connected with each other, and meanwhile, the universal signal receiving interface and the universal signal sending interface are respectively connected with corresponding interfaces on the tested FPGA, so that a universal signal interface test loop is formed.

Furthermore, the receiving interface of the signal end further comprises a state signal receiving interface, the sending interface of the signal end further comprises a state signal sending interface, the state signal receiving interface and the state signal sending interface are connected with each other, and the state signal receiving interface and the state signal sending interface are respectively connected with the corresponding interface on the tested FPGA, so that a state signal interface testing loop is formed.

The receiving interface of the signal end and/or the receiving interface of the clock end are connected with the sending interface of the signal end and/or the sending interface of the clock end through corresponding first transmission lines and second transmission lines, the first transmission lines are alternately provided with first bulges and first grooves, and the second transmission lines are alternately provided with second bulges and second grooves.

Further, the first transmission line is arranged in parallel with the second transmission line.

Further, the first protrusion, the first groove, the second protrusion and the second groove are respectively rectangular or arc-shaped.

The utility model also provides a signal interface self-loop test system based on the FMC standard, which comprises a signal interface self-loop test device, an FPGA test carrier plate and an upper computer, wherein the signal interface self-loop test device and the upper computer are respectively connected with the FPGA test carrier plate, the signal interface self-loop test device is any one of the signal interface self-loop test devices based on the FMC standard, the FPGA test carrier plate is provided with a power supply module, a clock module and a tested FPGA, and the signal interface self-loop test device, the upper computer, the power supply module and the clock module are respectively connected with the tested FPGA.

Compared with the prior art, the utility model has the advantages that:

1. the FMC loop test card only comprises the FMC connector, adopts passive design, and reduces the complexity of schematic diagram design and PCB design, thereby reducing the design cost of a test device and the production cost of the test device, increasing the reliability of the test device and reducing the influence on the electrical performance of a carrier plate;

2. according to the FMC connector, the data end receiving and sending interface and the clock end receiving and sending interface of the FMC connector are in short circuit connection through the first transmission line and the second transmission line respectively, and the first transmission line and the second transmission line are provided with the protrusions and the grooves alternately, so that the situation that signal crosstalk influences result judgment in the test process is avoided;

3. the utility model provides clock signals for the FPGA to be tested and supplies power by utilizing the clock module and the power module on the FPGA test carrier plate, thereby avoiding the condition of interference on the test when the FMC loop test card provides the clock signals for the FPGA in the prior art.

Drawings

Fig. 1 is a structural block diagram of a current FMC loop test card.

Fig. 2 is a block diagram of an apparatus according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a first structure of a first transmission line and a second transmission line according to an embodiment of the present invention.

Fig. 4 is a schematic diagram of a second structure of the first transmission line and the second transmission line in the embodiment of the utility model.

Fig. 5 is a block diagram of a system according to an embodiment of the present invention.

Illustration of the drawings: the test system comprises a 1-FMC loop test card, a 2-FPGA test carrier board, a 3-upper computer, a 101-high-speed clock receiving interface, a 102-high-speed clock sending interface, a 103-high-speed serial receiving interface, a 104-universal signal receiving interface, a 105-state signal receiving interface, a 106-high-speed serial sending interface, a 107-universal signal sending interface, a 108-state signal sending interface, a 201-first transmission line, a 202-second transmission line, a 203-first bump, a 204-first groove, a 205-second bump and a 206-second groove.

Detailed Description

The utility model is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the utility model.

As shown in fig. 2, the utility model provides a FMC standard-based signal interface self-loop test device, which includes an FMC loop test card 1, where the FMC loop test card 1 includes an FMC connector, a signal end and a clock end of the FMC connector are respectively connected to an FPGA to be tested, a transmitting interface and a receiving interface of the signal end are connected to each other, and a transmitting interface and a receiving interface of the clock end are connected to each other to implement self-loop test, as shown in fig. 5, the FPGA to be tested is mounted on an FPGA test carrier board 2 outside the FMC standard test device, a power module 21 and a clock module 22 are arranged on the FPGA test carrier board 2, and the power module 21 and the clock module 22 are respectively connected to the FPGA to be tested. Through the structure, the FMC loop test card 1 in the embodiment only includes the FMC connector, and adopts a passive design, thereby reducing the complexity of schematic diagram design and PCB design, reducing the design cost of the test device and the production cost of the test device, increasing the reliability of the test device, and reducing the influence on the electrical performance of the carrier board.

The signals of the FMC standard are divided into the following: 1. a high-speed serial interface; 2. a high-speed clock interface; 3. a general signal interface; 4. a status signal interface.

As shown in fig. 2, the receiving interface of the signal terminal of this embodiment includes a high-speed serial receiving interface 103, the transmitting interface of the signal terminal includes a high-speed serial transmitting interface 106, the high-speed serial receiving interface 103 is connected to the high-speed serial transmitting interface 106, specifically, the high-speed serial receiving interface 103 includes a DP _ C2M pin, the high-speed serial transmitting interface 106 includes a DP _ M2C pin, and the DP _ C2M pin and the DP _ M2C pin are shorted to perform a self-loop test of the high-speed serial interface.

As shown in fig. 2, the receiving interface of the clock terminal of the present embodiment includes a high-speed clock receiving interface 101, the transmitting interface of the clock terminal includes a high-speed clock transmitting interface 102, specifically, the clock input terminal 101 includes LA17_ CC and HA00_ CC pins, the clock output terminal 102 includes DP _ REFCLK pin, and the DP _ REFCLK pin is shorted with the LA17_ CC and HA00_ CC pins to perform a self-loop test of the high-speed clock interface.

As shown in fig. 2, the receiving interface of the signal terminal in this embodiment includes a general signal receiving interface 104, the sending interface of the signal terminal includes a general signal sending interface 107, the general signal receiving interface 104 and the general signal sending interface 107 are connected in a bidirectional manner, specifically, the general signal receiving interface 104 includes a LA or HA or HB _ IO _ P pin, the high-speed serial sending interface 106 includes a LA or HA or HB _ IO _ N pin, and the self-loop test of the general interface can be performed after the LA pin and the LA pin, the HA pin and the HA pin, and the HB _ IO _ P pin and the HB _ IO _ N pin are short-circuited.

As shown in fig. 2, the receiving interface of the signal terminal of this embodiment includes a state signal receiving interface 105, the sending interface of the signal terminal includes a state signal sending interface 108, the state signal receiving interface 105 and the state signal sending interface 108 are connected in a bidirectional manner, specifically, the state signal receiving interface 105 includes state signal pins such as GA, the state signal sending interface 108 includes state signal pins such as GA, and the self-loop test of the state signal interface can be performed after the state signal pins such as GA are short-circuited.

With the above structure, the FMC standard-based signal interface self-loop test device of this embodiment can test a high-speed serial interface, a high-speed clock interface, a general signal interface, or a status signal interface separately, and also can test the interfaces at the same time.

For the FMC loop test card 1 of the present embodiment, when designing a PCB, crosstalk may occur due to a high routing density due to a small volume. Therefore, as shown in fig. 3 and 4, the embodiment further includes first transmission lines 201 corresponding to the receiving interfaces of the signal terminal and the clock terminal one by one, and a second transmission line 202 corresponding to the transmission interface of the signal terminal and the transmission interface of the clock terminal, wherein the receiving interface of the signal terminal and/or the receiving interface of the clock terminal are connected with the transmission interface of the signal terminal and/or the transmission interface of the clock terminal through the first transmission line 201 and the second transmission line 202, the first transmission line 201 and the second transmission line 202 are arranged in parallel, the first transmission line 201 is alternately provided with first protrusions 203 and first grooves 204, the second transmission line 202 is alternately provided with second protrusions 205 and second grooves 206, therefore, the influence of crosstalk on the signals input and output by the FMC loop test card 1 is reduced, and the situation that the judgment of a test result is influenced due to the fact that the difference between the signals output and returned by the tested FPGA is large caused by signal interference is avoided.

As shown in fig. 3, in the present embodiment, the first protrusion 203, the first groove 204, the second protrusion 205, and the second groove 206 are respectively rectangular. For the convenience of the manufacturing process, as shown in fig. 4, the first protrusion 203, the first groove 204, the second protrusion 205 and the second groove 206 may also be circular arcs.

As shown in fig. 5, this embodiment further provides a signal interface self-loop test system based on the FMC standard, which includes a signal interface self-loop test device, an FPGA test carrier board 2, and an upper computer 3, where the signal interface self-loop test device, the upper computer 3, and the FPGA test carrier board 2 are respectively, the signal interface self-loop test device is any one of the signal interface self-loop test devices based on the FMC standard, the FPGA test carrier board unit 2 includes a power module 21, a clock module 22, and an FPGA to be tested, the signal interface self-loop test device, the power module 21, the clock module 22, and the upper computer 3 are respectively connected to the FPGA to be tested, and the power module 21 is connected to the clock module 22. Through the structure, the power module 21 and the clock module 22 arranged on the FPGA test carrier plate 2 can provide clock signals for the FPGA to be tested and supply power, so that the condition of interference to the test when the clock signals are provided for the FPGA in the prior art is avoided.

The following describes the operation principle of the FMC standard-based signal interface self-loop test system of this embodiment:

when the high-speed serial interface is tested, the upper computer 3 controls the tested FPGA to send out data, the data passes through the high-speed serial receiving interface 103 and the high-speed serial sending interface 106 of the FMC connector in the FMC loop test card 1 and then is transmitted back to the FPGA, and the upper computer 3 compares the received data with the sent data to verify whether the high-speed serial interfaces of the FMC interface of the tested FPGA are communicated or not and whether the designed signal rate requirement is met or not;

when the high-speed clock interface is tested, the tested FPGA acquires a system clock of the clock module 22, the system clock is synthesized by the CMT module of the FPGA to generate a reference clock required by design, then a clock signal is sent to the clock input end 101 of the FMC connector in the FMC loop test card 1 through the ODDR module of the FPGA, and then is returned to the tested FPGA through the clock output end 102 of the FMC connector in the FMC loop test card 1, and the reference clock is subjected to frequency locking confirmation by the CMT module of the FPAG, so that whether the high-speed clock interfaces of the FMC interface of the tested FPGA are communicated or not and whether the designed clock frequency requirement is met or not is verified;

when the universal signal interface is tested, the upper computer 3 controls the tested FPGA to send out data, the data is transmitted back to the tested FPGA after passing through the universal signal receiving interface 104 and the universal signal sending interface 107 of the FMC connector in the FMC loop test card 1, and the upper computer 3 controls the received data to be compared with the sent data, so that whether the universal signal interfaces of the FMC interface of the tested FPGA are communicated or not and whether the designed signal rate requirement is met or not can be verified. Meanwhile, due to the logic programmable characteristic of the FPGA interface, the FPGA interface can simultaneously test the bidirectional interface and test the differential pair single-ended signal;

when the status signal interface is tested, the upper computer 3 controls the tested FPGA to send out data, the data passes through the status signal receiving interface 105 and the status signal sending interface 108 of the FMC connector in the FMC loop test card 1 and then is transmitted back to the tested FPGA, and the upper computer 3 compares the received data with the sent data, so that whether the status signal interfaces of the FMC connector of the tested FPGA are communicated or not and whether the designed signal rate requirement is met or not can be verified. Meanwhile, due to the logic programmable characteristic of the FPGA interface, the FPGA interface can simultaneously test the bidirectional interfaces of the part of interfaces.

The foregoing is considered as illustrative of the preferred embodiments of the utility model and is not to be construed as limiting the utility model in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims

1. The FMC standard-based signal interface self-loop testing device is characterized by comprising an FMC loop testing card (1), an FMC connector is arranged on the FMC loop testing card (1), a signal end and a clock end of the FMC connector are respectively connected with a tested FPGA, a sending interface and a receiving interface of the signal end are connected with each other, a sending interface and a receiving interface of the clock end are connected with each other to achieve self-loop testing, the tested FPGA is installed on an FPGA testing carrier plate (2), a power module (21) and a clock module (22) are arranged on the FPGA testing carrier plate (2), and the power module (21) and the clock module (22) are respectively connected with the tested FPGA.

2. The FMC-based signal interface self-loop testing device as recited in claim 1, wherein the clock-side receiving interface comprises a high-speed clock receiving interface (101), the clock-side transmitting interface comprises a high-speed clock transmitting interface (102), the high-speed clock receiving interface (101) and the high-speed clock transmitting interface (102) are respectively connected with corresponding interfaces on an FPGA to be tested, and the high-speed clock receiving interface (101) and the high-speed clock transmitting interface (102) are further connected with each other to form a high-speed clock interface testing loop.

3. The FMC-standard-based signal interface self-loop testing device as recited in claim 1, wherein the signal-side receiving interface comprises a high-speed serial receiving interface (103), the signal-side transmitting interface comprises a high-speed serial transmitting interface (106), the high-speed serial receiving interface (103) and the high-speed serial transmitting interface (106) are connected to each other, and the high-speed serial receiving interface (103) and the high-speed serial transmitting interface (106) are connected to corresponding interfaces on an FPGA to be tested, respectively, so as to form a high-speed serial interface testing loop.

4. The FMC-based signal interface self-loop testing device as recited in claim 1, wherein the signal end receiving interface further comprises a general signal receiving interface (104), the signal end transmitting interface further comprises a general signal transmitting interface (107), the general signal receiving interface (104) and the general signal transmitting interface (107) are connected to each other, and the general signal receiving interface (104) and the general signal transmitting interface (107) are respectively connected to corresponding interfaces on an FPGA to be tested, so that a general signal interface testing loop is formed.

5. The FMC-based signal interface self-loop testing device as recited in claim 1, wherein the signal end receiving interface further comprises a status signal receiving interface (105), the signal end transmitting interface further comprises a status signal transmitting interface (108), the status signal receiving interface (105) and the status signal transmitting interface (108) are connected to each other, and the status signal receiving interface (105) and the status signal transmitting interface (108) are respectively connected to corresponding interfaces on an FPGA under test, so as to form a status signal interface testing loop.

6. The FMC-based signal interface self-loop testing device as recited in claim 1, further comprising first transmission lines (201) corresponding to the receiving interfaces of the signal end and the clock end one by one, and second transmission lines (202) corresponding to the transmitting interfaces of the signal end and the clock end one by one, wherein the receiving interfaces of the signal end and/or the receiving interfaces of the clock end are connected with the transmitting interfaces of the signal end and/or the transmitting interfaces of the clock end through corresponding first transmission lines (201) and second transmission lines (202), the first transmission lines (201) are alternately provided with first protrusions (203) and first grooves (204), and the second transmission lines (202) are alternately provided with second protrusions (205) and second grooves (206).

7. An FMC-standard-based signal interface self-loop test device as in claim 6, characterised in that the first transmission line (201) is arranged in parallel with the second transmission line (202).

8. The FMC-standard-based signal interface self-loop test device as recited in claim 6, wherein the first protrusion (203), the first groove (204), the second protrusion (205), and the second groove (206) are rectangular or circular in shape.

9. A signal interface self-loop test system based on an FMC standard is characterized by comprising a signal interface self-loop test device, an FPGA test carrier plate (2) and an upper computer (3), wherein the signal interface self-loop test device and the upper computer (3) are respectively connected with the FPGA test carrier plate (2), the signal interface self-loop test device is the signal interface self-loop test device based on the FMC standard according to any one of claims 1-8, the FPGA test carrier plate (2) comprises a power supply module (21), a clock module (22) and an FPGA to be tested, and the signal interface self-loop test device, the upper computer (3), the power supply module (21) and the clock module (22) are respectively connected with the FPGA to be tested.