CN101937175B - Photoetching method - Google Patents
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- CN101937175B CN101937175B CN2009100544052A CN200910054405A CN101937175B CN 101937175 B CN101937175 B CN 101937175B CN 2009100544052 A CN2009100544052 A CN 2009100544052A CN 200910054405 A CN200910054405 A CN 200910054405A CN 101937175 B CN101937175 B CN 101937175B
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- bias voltage
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Abstract
The invention discloses a photoetching method comprising the following steps of: after developing, pruning a photoresist pattern by using a dry-method etching method; and adopting the bias voltage during dry-method etching. The photoetching method ensures that the positions for etching gas ions and carrying out an etching reaction on the photoresist pattern are more accurate and improves the quality for pruning the photoresist pattern, thereby correspondingly reducing the line-width roughness of a semiconductor formed by subsequent etching by pruning the photoresist pattern.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly photoetching method.
Background technology
Defective in the semiconductor fabrication process is a principal element that influences the yield and the device performance of semiconductor devices.Especially for semiconductor manufacturing industry of today,, particularly strict for the requirement of photoetching and etch process when device size is reduced to 100nm when following.For example, in photoetching process, line edge roughness (LER, Line Edge Roughness) and line width roughness (LWR, Line Width Roughness) are exactly the important indicator that technology is comparatively paid close attention to.Existing experimental study shows, when line edge roughness and line width roughness were higher, device performance can worsen thereupon.For example, for SRAM, high if its grid forms the line width roughness of the photoresistance figure in the technology, can cause follow-up is mask with said photoresistance figure, and the flatness of the sidewall of the grid that etching forms is very poor.The poor flatness of said gate lateral wall possibly cause situation such as element leakage, the puncture of grid local current.Therefore, reduce line edge roughness and line width roughness and have bigger effect for improving device performance.
The existing trial that reduces line edge roughness and line width roughness is started with from optimizing the photoetching process aspect usually.For example; Application number is that 200510067628.4 one Chinese patent application just provides a kind of Treatment Solution that contains surfactant; When this Treatment Solution during in developing process or afterwards as washing fluid, can reduce the defective after the development, for example pattern damages or line width roughness.And after development, in order further to reduce line width roughness, also can prune formed photoresistance figure usually.Yet find that in present process practice owing to prune the deficiency of technology, through the photoresistance figure of pruning, its line width roughness can increase on the contrary, thereby is unfavorable for follow-up etch process.
Summary of the invention
What the present invention solved is the pruning of prior art development back to the photoresistance figure, the problem that line width roughness is increased.
For addressing the above problem, the present invention provides a kind of photoetching method, comprising:
After development, use the method for dry etching to prune the photoresistance figure, when said dry etching, adopt bias voltage.
Compared with prior art, above-mentioned photoetching method has the following advantages: through bias voltage, it is more accurate to make that etching gas ion and photoresistance figure carry out the position of etching reaction, has improved the quality of pruning the photoresistance figure.Thereby through pruning the photoresistance figure, the corresponding line width roughness that has reduced the semiconductor structure of subsequent etch formation.
Description of drawings
Fig. 1 is a kind of embodiment process flow diagram of photoetching method of the present invention;
Fig. 2 a to Fig. 2 e is the synoptic diagram of photoetching method embodiment shown in Figure 1.
Embodiment
Through existing photoresistance figure is pruned discovering of technology, the pruning technology of existing photoresistance figure adopts the method for dry etching usually, yet in the dry etching process, does not control for the position of etching reaction.In other words, in said dry etching process, the photoresistance figure is placed in and carries out free responding in the etching gas atmosphere.Because the position of etching reaction is uncontrollable, so the surface of photoresistance figure possibly become smooth after reaction, also possibly after reacting, become more coarse.And, also will influence the roughness of the semiconductor structure that subsequent etch forms if the surface of photoresistance figure becomes more coarse, for example, in the process that forms grid, the photoresistance patterned surface is coarse will to make that the sidewall roughness of grid of formation is higher.
Based on this, a kind of embodiment of photoetching method of the present invention when adopting dry etching that the photoresistance figure after developing is pruned, adopts bias voltage.
Above-mentioned embodiment is controlled the response location of etching gas and photoresistance figure through adopting bias voltage, makes the coarse place of etching gas and photoresistance figure that etching reaction take place, thereby reduces the line width roughness of photoresistance figure.
In photoetching method now, so that reduce the light reflection, usually being etched on the layer and can forming bottom layer anti-reflection layer (BARC, Bottom Anti Reflective Coating) earlier, just on bottom layer anti-reflection layer, be coated with photoresistance then.And existing etching process for bottom layer anti-reflection layer also can adopt bias voltage, in view of this, combines the above-mentioned method of mentioning to the pruning employing bias voltage of photoresistance figure.Comprise the photoetching method of bottom layer anti-reflection layer for this type of; Just can for example, in same etching machines, carry out carrying out process integration to the pruning of photoresistance figure with to the etching of bottom layer anti-reflection layer; Thereby also can improve process efficiency, save the certain process cost.
For example with reference to shown in Figure 1, for the above-mentioned photoetching method that comprises bottom layer anti-reflection layer, implementation step is following: step s1, and adopt dry etching that the photoresistance figure after developing is pruned, said dry etching adopts bias voltage; Step s2 adopts dry etching that bottom layer anti-reflection layer is carried out main etching, and said dry etching adopts bias voltage; Step s3 adopts dry etching that bottom layer anti-reflection layer was carried out etching, and said dry etching adopts bias voltage.
Below further specifying for example through the photoetching process that relates in the grid manufacturing process.
Fig. 2 a is the structural drawing after developing in the grid manufacturing process, and it comprises grid layer 20, the bottom layer anti-reflection layer 30 on the grid layer 20 and the photoresistance figure 40 on the bottom layer anti-reflection layer 30 on substrate 10, the substrate 10.Fig. 2 b is the vertical view of Fig. 2 a.Can see that from Fig. 2 b the sidewall edge of the photoresistance figure 40 after the development is more coarse.
Shown in Fig. 1 and Fig. 2 c, adopt the method for plasma etching that the photoresistance figure 40 after developing is pruned, the said direction of arrow is represented etched direction.For example, Cl is adopted in said etching
2And O
2As etching gas, Cl
2And O
2Gas flow ratio be 0.5～5, the power of top voltage source is 100～500 watts (W), bias voltage is 50～200 volts (V), for example 50V, 65V, 100V, 150V, 200V etc.Wherein, said bias voltage provides through the electrode that is arranged at the wafer bottom.The said etched time need be taken all factors into consideration the characteristic dimension requirement that detects after develop back characteristic dimension requirement that detects and the etching.And the big young pathbreaker of the bias voltage that adopts during etching influences the effect of pruning.Through experiment confirm, when etching reaction, higher bias voltage can more be tending towards vertical so that etching gas ion bom bardment is etched the direction of material.
Shown in Fig. 1 and Fig. 2 d, after photoresistance figure 40 is pruned, bottom layer anti-reflection layer 30 is carried out main etching, dry etching is adopted in said main etching, and the said direction of arrow is represented etched direction.For example, Cl is adopted in said etching
2And O
2As etching gas, Cl
2And O
2Gas flow ratio be 1～5, the power of top voltage source is 100～500 watts (W), bias voltage is 200～500 volts (V).Wherein, said bias voltage provides through the electrode that is arranged at the wafer bottom.
After bottom layer anti-reflection layer 30 is carried out main etching, continue bottom layer anti-reflection layer 30 was carried out etching the said etching employing dry etching of crossing.For example, Cl is adopted in said etching
2And O
2As etching gas, Cl
2And O
2Gas flow ratio be 1～5, the power of top voltage source is 100～500 watts (W), bias voltage is 200～500 volts (V).Wherein, said bias voltage provides through the electrode that is arranged at the wafer bottom.
From to the pruning of photoresistance figure 40 and can see to the main etching of bottom layer anti-reflection layer 30, overetched explanation; Because above-mentioned each etching process all need adopt bias voltage; And the etch process parameters all similar such as etching gas that corresponding etching is adopted; Thereby above-mentioned each etching process can carry out in same etching machines, be equivalent to pruning the photoresistance figure and the etching of bottom layer anti-reflection layer is integrated, thereby corresponding process efficiency also improves.
Shown in Fig. 2 e, through after the above-mentioned steps, just formed on the grid layer 20 with the bottom layer anti-reflection layer after the etching 30 and on the mask that constitutes of photoresistance figure 40.Mask to be constituted carries out etching to grid layer 20, just can form required grid.For example, successively grid layer 20 is carried out main etching and crosses etching with said mask, and remove said mask, just can form required grid.Can adopt existing suitable engraving method according to the needs of actual etched thickness and time to the etching of grid layer 20, just no longer this process is elaborated here.
Find in the measurement after forming grid, do not adopt the scheme of bias voltage when in the prior art photoetching photoresistance figure being pruned, the above-mentioned scheme that adopts bias voltage when the photoresistance figure is pruned, its line width roughness has obvious minimizing.And, adopting different bias voltage, its degree that makes line width roughness descend is also different.Bias voltage is big more, and corresponding line width roughness is more little.Therefore, this result has also just confirmed to mention in the above-mentioned explanation: higher bias voltage can more be tending towards vertical so that etching gas ion bom bardment is etched the direction of material.The result learns thus, after taking all factors into consideration factors such as technology cost and efficient, when the photoresistance figure is pruned, can adopt higher biasing obtaining better to prune effect, thereby further reduces the roughness of the structure that subsequent etch forms.
In sum, photoetching method of the present invention adopts bias voltage when the photoresistance figure is pruned, and it is more accurate to make that etching gas ion and photoresistance figure carry out the position of etching reaction, has improved the quality of pruning photoresistance figure.Thereby through pruning photoresistance figure, the corresponding line width roughness that reduced.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (6)
1. a photoetching method is characterized in that, comprising: after development, use the method for dry etching to prune the photoresistance figure, when said dry etching, adopt bias voltage, said bias voltage provides through the electrode that is arranged at the wafer bottom.
2. photoetching method as claimed in claim 1 is characterized in that, said dry etching adopts Cl
2And O
2As etching gas, Cl
2And O
2Gas flow ratio be 0.5～5, the power of top voltage source is 100～500 watts, bias voltage is 50～200 volts.
3. photoetching method as claimed in claim 1 is characterized in that, said bias voltage is 200 volts.
4. photoetching method as claimed in claim 1 is characterized in that, also comprises: after pruning the photoresistance figure, the bottom layer anti-reflection layer under the photoresistance figure is carried out main etching successively and crosses etching.
5. photoetching method as claimed in claim 4 is characterized in that, Cl is adopted in said main etching
2And O
2As etching gas, Cl
2And O
2Gas flow ratio be 1～5, the power of top voltage source is 100～500 watts, bias voltage is 200～500 volts.
6. photoetching method as claimed in claim 4 is characterized in that, the said etching employing Cl that crosses
2And O
2As etching gas, Cl
2And O
2Gas flow ratio be 1～5, the power of top voltage source is 100～500 watts, bias voltage is 200～500 volts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100544052A CN101937175B (en) | 2009-07-03 | 2009-07-03 | Photoetching method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100544052A CN101937175B (en) | 2009-07-03 | 2009-07-03 | Photoetching method |
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| CN101937175A CN101937175A (en) | 2011-01-05 |
| CN101937175B true CN101937175B (en) | 2012-08-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102866581A (en) * | 2012-09-27 | 2013-01-09 | 无锡华润上华科技有限公司 | Method for overcoming exposure region defect caused by underexposure |
| CN104124205B (en) * | 2014-07-18 | 2018-03-16 | 华进半导体封装先导技术研发中心有限公司 | A kind of preparation method of RDL wiring layers |
| CN108010839B (en) * | 2017-12-06 | 2021-08-06 | 信利（惠州）智能显示有限公司 | Thin film transistor, manufacturing method of thin film transistor and film layer etching process |
| CN111696917A (en) * | 2020-07-15 | 2020-09-22 | 华虹半导体(无锡)有限公司 | Etching method of metal interconnection structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005522872A (en) * | 2002-04-09 | 2005-07-28 | ウナクシス ユーエスエイ、インコーポレイテッド | Improved method for etching vias |
| CN1699530A (en) * | 2004-03-19 | 2005-11-23 | 气体产品与化学公司 | Process solutions containing surfactants |
| CN101153396A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Plasma etching method and device |
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- 2009-07-03 CN CN2009100544052A patent/CN101937175B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005522872A (en) * | 2002-04-09 | 2005-07-28 | ウナクシス ユーエスエイ、インコーポレイテッド | Improved method for etching vias |
| CN1699530A (en) * | 2004-03-19 | 2005-11-23 | 气体产品与化学公司 | Process solutions containing surfactants |
| CN101153396A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Plasma etching method and device |
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Effective date of registration: 20121030 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |