CN101930937A - Packaging method of photoelectric component and packaging carrier structure thereof - Google Patents
Packaging method of photoelectric component and packaging carrier structure thereof Download PDFInfo
- Publication number
- CN101930937A CN101930937A CN201010243181.2A CN201010243181A CN101930937A CN 101930937 A CN101930937 A CN 101930937A CN 201010243181 A CN201010243181 A CN 201010243181A CN 101930937 A CN101930937 A CN 101930937A
- Authority
- CN
- China
- Prior art keywords
- metal material
- luminescence chip
- electrode metal
- electrode
- internal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Abstract
The invention discloses a packaging method of a photoelectric component and a packaging carrier structure thereof. The method comprises: constructing at least an internal electrode metal material, at least on liner metal material and at least one external electrode metal material on one side plate of a substrate so as to form a photoelectric component packaging carrier structure in which at least one double-side electrode light emitting chip is welded on the internal electrode metal material selectively and in which at least panel electrode light emitting chip is fixedly arranged on the linear metal structure selectively; and electrically connecting the double-side electrode light emitting chips and the plane electrode light emitting chips to the external electrode metal materials by using gold wires, and coating at least one packaging material on the double-side electrode light emitting chips, the plane electrode light emitting chips and the gold wires to accomplish the packaging of the photoelectric component. In the invention, the color rendering of the photoelectric component is improved, and high radiation efficiency is achieved.
Description
Technical field
The present invention relates to a kind of method for packing and package carrier structure thereof of photoelectric subassembly.
Background technology
Light-emitting diode relies on its power saving, the life-span is long, driving voltage is low, and plurality of advantages such as reaction rate is fast, gradually, become a kind of luminescence component with fastest developing speed, along with advancing by leaps and bounds of light-emitting diode (LED) technology, add the day by day ripe of relevant peripheral integrated circuit control assembly and heat dissipation technology, use photoelectric subassembly its application day by day diversification of light-emitting diode as luminescence chip.
The principle of luminosity of light-emitting diode photoelectricity assembly is the light that sends specific wavelength by electric light (Electro Luminescence) transition effects; For example, above single luminescence chip, directly be coated with the yellow fluorescence layer, covered with epoxy resin encapsulation materials such as (Epoxy) again and covered encapsulation, to constitute single light-emitting diode photoelectricity assembly, the luminescence technology that it used is luminescence chip sends single wavelength according to the electric light transition effects a blue light, fluorescence coating in the irradiation encapsulation material, make the electron energy of chemical constitution be transformed into excitation state generation yellow fluorescence from ground state, mix to two wavelength light sources near white penetrate with blue light, this kind technology is called as chemical mixed light.
The finished product of these chemical mixed light technology mades uses and seems simple, but still be the main flow of photoelectric subassembly so far, similar photoelectric subassembly is because of different demands, its employed luminescence chip also has different separately designs, for example present common high brightness luminescent chip is the area that effectively increases light-emitting area, and its light-emitting area only has single activation electrode, and grounding electrode is arranged on the opposing face of light-emitting area, and become a kind of double-face electrode luminescence chip.
Be different from the plane electrode luminescence chip that generally is provided with activation electrode and grounding electrode in light-emitting area simultaneously, the double-face electrode luminescence chip has preferable luminous efficiency really, and has improved the colourity of drilling of photoelectric subassembly relatively; But, increased the difficulty that double-face electrode luminescence chip and plane electrode luminescence chip are encapsulated in same photoelectric subassembly relatively because the circuit framework of the circuit framework of double-face electrode luminescence chip and plane electrode luminescence chip is obviously different.
Moreover, must be accompanied by high heat when the double-face electrode luminescence chip is luminous; And encapsulation material of photoelectric subassembly itself and non-refractory, so when the luminescence chip quantity in the encapsulation material increases, luminescence chip and encapsulation material can produce qualitative change fast because of high temperature, make photoelectric subassembly that so-called light decay and the look phenomenon that declines take place, and have a strong impact on the usefulness of photoelectric subassembly.
Summary of the invention
The objective of the invention is to improve the shortcoming of prior art and product, and provide a kind of photoelectric subassembly that can effectively improve to drill colourity, and the method for packing and the package carrier structure thereof of the photoelectric subassembly of good heat radiating usefulness are provided.
For achieving the above object, the invention provides a kind of method for packing of photoelectric subassembly, comprise the steps:
1) provides a substrate;
2) at least described substrate wherein the construction of side plate face at least one internal electrode metal material, at least one liner metal material and at least one outer electrode metal material are arranged;
3) will be at least a pair of face electrode light-emitting chips welding on described internal electrode metal material;
4) at least one plane electrode luminescence chip is fixedly arranged on the described liner metal material;
5) utilizing gold thread to finish described double-face electrode luminescence chip, described plane electrode luminescence chip and described outer electrode metal material electrically connects;
6) at least a encapsulation material is coated on outside described each double-face electrode luminescence chip, each plane electrode luminescence chip and all gold threads.
Further, described double-face electrode luminescence chip, all plane electrode luminescence chips and all gold thread centralized configuration are in the presumptive area of this substrate surface.
Further, described double-face electrode luminescence chip, all plane electrode luminescence chips and all gold thread centralized configuration are in the plate face center of this substrate.
A kind of package carrier structure of photoelectric subassembly comprises a substrate, at least one internal electrode metal material that is established in described substrate surface, at least one described substrate surface and the liner metal material that separates mutually with each internal electrode metal material, at least one outer electrode metal material, at least one double-face electrode luminescence chip and at least one plane electrode luminescence chip that is established in described substrate surface and separates mutually with each internal electrode metal material and each liner metal material of being established in;
Described double-face electrode luminescence chip is welded on the described internal electrode metal material, and described plane electrode luminescence chip is fixedly arranged on the described liner metal material.
Further, the package carrier structure of described photoelectric subassembly is provided with at least two outer electrode metal materials.
Further, the package carrier structure of described photoelectric subassembly is provided with at least two internal electrode metal materials.
Further, described each internal electrode metal material, each liner metal material and each outer electrode metal material surface coverage one welding resisting layer, this welding resisting layer is provided with at least one window in the zone with respect to described each internal electrode metal material; Described welding resisting layer respectively is provided with at least two windows in the zone with respect to described each outer electrode metal material.
Further, described substrate is a metal plate, is provided with an insulating barrier between described each internal electrode metal material, each liner metal material and each outer electrode metal material and this substrate.
In sum, the present invention utilizes the wherein side plate face construction of a substrate to have: internal electrode metal material, liner metal material and outer electrode metal material, make it constitute a kind of available property the double-face electrode luminescence chip is welded in individually on the internal electrode metal material, and optionally the plane electrode luminescence chip is fixedly arranged on the photoelectric subassembly package carrier structure on the liner metal material.
Finish double-face electrode luminescence chip, plane electrode luminescence chip and outer electrode metal material with gold thread again and electrically connect, at last at least a encapsulation material is coated on each double-face electrode luminescence chip, each plane electrode luminescence chip and all gold threads and promptly finishes the photoelectric subassembly encapsulation outward.
Utilize above-mentioned photoelectric subassembly method for packing, the double-face electrode luminescence chip and the plane electrode luminescence chip that quantity can not be waited are encapsulated into single photoelectric subassembly, can effectively improve the colourity of drilling of this single photoelectric subassembly; And the used heat of each double-face electrode luminescence chip can directly see through the internal electrode metal material that it welded and outwards discharge, and possesses good cooling mechanism, makes photoelectric subassembly keep due task performance.
Description of drawings
Fig. 1 is a photoelectric subassembly encapsulation flow chart of the present invention.
Fig. 2 is the photoelectric subassembly stereoscopic figure of the embodiment of the invention 1.
Fig. 3 is the package carrier STRUCTURE DECOMPOSITION figure of the embodiment of the invention 1.
Fig. 4 is the package carrier stereoscopic figure of the embodiment of the invention 1.
Fig. 5 is the photoelectric subassembly structural plan figure of the embodiment of the invention 1.
Fig. 6 is the photoelectric subassembly structural plan figure of the embodiment of the invention 2.
Fig. 7 is the photoelectric subassembly structural plan figure of the embodiment of the invention 3.
Embodiment
Below in conjunction with description of drawings the specific embodiment of the present invention.
Embodiment 1:
As shown in Figure 1, 2, the method for packing of photoelectric subassembly of the present invention comprises the steps: 1) substrate 11 is provided; 2) to be less than this substrate 11 wherein the construction of side plate face at least one internal electrode metal material 12, at least one liner metal material 13 and an outer electrode metal material 14 are arranged; 3) optionally inciting somebody to action at least, a pair of face electrode light-emitting chip 21 is welded on this at least one internal electrode metal material 12; 4) optionally at least one plane electrode luminescence chip 22 is fixedly arranged on this at least one liner metal material 13; 5) utilizing gold thread 30 to finish this at least one double-face electrode luminescence chip 21 electrically connects with this at least one plane electrode luminescence chip 22 and this outer electrode metal material 14; 6) at last at least a encapsulation material 40 is coated on outside each double-face electrode luminescence chip 21, each plane electrode luminescence chip 22 and all gold threads 30.The double-face electrode luminescence chip 21 and the plane electrode luminescence chip 22 that quantity can not be waited is encapsulated into the outer photoelectric subassembly of single module.
Utilize the method for packing of above-mentioned photoelectric subassembly, the double-face electrode luminescence chip 21 and the plane electrode luminescence chip 22 that quantity can not be waited are encapsulated into single photoelectric subassembly, can effectively improve the colourity of drilling of this single photoelectric subassembly; The used heat of each double-face electrode luminescence chip 21 and each plane electrode luminescence chip 22 can see through internal electrode metal material 12 and liner metal material 13 respectively and outwards discharge, and makes photoelectric subassembly keep due task performance.
Particularly, the package carrier structure of photoelectric subassembly includes among the present invention shown in Fig. 3,4,5: a substrate 11, at least one internal electrode metal material 12, at least one liner metal material 13, and at least one outer electrode metal material 14;
Wherein: this substrate 11 is the metal plate of aluminium or copper, and is provided with relevant use, the installation of pilot hole 111 to make things convenient for photoelectric subassembly.
Described internal electrode metal material 12 is to be established in this substrate 11 plate faces, and each internal electrode metal material 12 can be made of the thin institute of copper, if this substrate 11 is a metal plate, is provided with an insulating barrier 15 between described each internal electrode metal material 12 and this substrate 11.
Described liner metal material 13 is to be established in this substrate 11 plate faces, and separate mutually with each internal electrode metal material 12, each liner metal material 13 is made of the thin institute of copper, if this substrate 11 is a metal plate, is provided with an insulating barrier 15 between described each liner metal material 13 and this substrate 11.
Described outer electrode metal material 14 is to be established in this substrate 11 plate faces, and separate mutually with each internal electrode metal material 12 and each liner metal material 13, each outer electrode metal material 14 is made of the thin institute of copper, if this substrate 11 is a metal plate, be provided with an insulating barrier 15 between each outer electrode metal material 14 and this substrate 11.
Described each internal electrode metal material 12, each liner metal material 13, each outer electrode metal material 14 surface coverage one welding resisting layer 16, this welding resisting layer 16 is provided with a window 161 at least in the zone with respect to each internal electrode metal material 12, makes position that internal electrode metal material 12 exposes with respect to window 161 become the weld pad 121 that double-face electrode luminescence chip 21 and internal electrode metal material 12 electrically connect; This welding resisting layer 16 respectively is provided with at least two windows 163,164 in the zone with respect to each outer electrode metal material 14, make position that outer electrode metal material 14 exposes with respect to window 163 become the weld pad 141 that luminescence chip and outer electrode metal material 14 electrically connect, the position of exposing with respect to window 164 becomes the weld pad 142 that outer electrode metal material 14 and external circuit electrically connect.
Embodiment 2:
As shown in Figure 6, the difference of present embodiment and embodiment 1 is: can directly utilize this at least one internal electrode metal material 12 to electrically connect with external circuit, so this welding resisting layer 16 is provided with at least two windows 161,162 in the zone with respect to this at least one internal electrode metal material 12, make position that this internal electrode metal material 12 exposes with respect to window 161 become the weld pad 121 that double-face electrode luminescence chip 21 and internal electrode metal material 12 electrically connect, the position of exposing with respect to window 162 becomes the weld pad 122 that internal electrode metal material 12 and external circuit electrically connect.
Described substrate 11 plate faces are provided with at least two outer electrode metal materials 14, and each outer electrode metal material 14 is to separate mutually with each internal electrode metal material 12 and each liner metal material 13, and each outer electrode metal material 14 be provided with at least two weld pads 141,142 for and plane electrode luminescence chip 22 (or double-face electrode luminescence chip 21) and external circuit electrically connect, can be by these at least two outer electrodes respectively as activation electrode and the grounding electrode of photoelectric subassembly in order to electrically connect with external circuit.
Embodiment 3:
As shown in Figure 7, present embodiment is with the difference of embodiment 1 or 2: the visual purposes of overall package carrier structure different, on same substrate 11, be provided with at least two internal electrode metal materials 12, in use, at least two double-face electrode luminescence chips 21 are welded on respectively on the affiliated internal electrode metal material 12, can utilize internal electrode metal material 12 to reach thermolysis, effectively solve the problem that double-face electrode luminescence chip 21 is followed high heat luminous the time; In addition, each plane electrode luminescence chip 22 can utilize heat-conducting glue to anchor on the same liner metal material 13, can utilize this liner metal material 13 to reach thermolysis equally, therefore can effectively improve the colourity of drilling of photoelectric subassembly, and good heat dissipation is provided.
What deserves to be mentioned is, method for packing and package carrier structure Design thereof by above-mentioned photoelectric subassembly, can be with all internal electrode metal materials 12, all liner metal materials 13 and all outer electrode metal materials 14 are provided on the same plate face of substrate 11, and each internal electrode metal material 12, each liner metal material 13 and each outer electrode metal material 14 can extend towards the presumptive area of substrate 11, make with when the package application, with all double-face electrode luminescence chips 21, all plane electrode luminescence chips 22 and all gold threads 30 centralized configuration are in the presumptive area of these substrate 11 plate faces, and be good in the center of these substrate 11 plate faces with centralized configuration, so not only can increase the convenience of packaging operation, more can promote the temperature difference ratio at substrate 11 centers and edge, promote the waste heat discharge speed of double-face electrode luminescence chip 21 and plane electrode luminescence chip 22 relatively.
In sum, execution mode of the present invention only provides a kind of execution mode of the best, technology contents of the present invention and technical characterstic disclose as above, yet the personage who is familiar with this technology still may do various replacement and the modifications that do not deviate from creation spirit of the present invention based on disclosed content; Therefore, protection scope of the present invention is not limited to the technology contents that embodiment discloses, so all equivalences of doing according to shape of the present invention, structure and principle change, all is encompassed in protection scope of the present invention.
Claims (9)
1. the method for packing of a photoelectric subassembly is characterized in that, comprises the steps:
1) provides a substrate;
2) at least described substrate wherein the construction of side plate face at least one internal electrode metal material, at least one liner metal material and at least one outer electrode metal material are arranged;
3) will be at least a pair of face electrode light-emitting chips welding on described internal electrode metal material;
4) at least one plane electrode luminescence chip is fixedly arranged on the described liner metal material;
5) utilizing gold thread to finish described double-face electrode luminescence chip, described plane electrode luminescence chip and described outer electrode metal material electrically connects;
6) will encapsulate material is coated on outside described each double-face electrode luminescence chip, each plane electrode luminescence chip and all gold threads.
2. the method for packing of a kind of photoelectric subassembly according to claim 1, it is characterized in that: described double-face electrode luminescence chip, plane electrode luminescence chip and all gold thread centralized configuration are in the presumptive area of this substrate surface.
3. the method for packing of a kind of photoelectric subassembly according to claim 1, it is characterized in that: described double-face electrode luminescence chip, plane electrode luminescence chip and all gold thread centralized configuration are in the plate face center of this substrate.
4. the package carrier structure of a photoelectric subassembly is characterized in that: comprise a substrate, at least one internal electrode metal material that is established in described substrate surface, at least one described substrate surface and the liner metal material that separates mutually with each internal electrode metal material, at least one outer electrode metal material, at least one double-face electrode luminescence chip and at least one plane electrode luminescence chip that is established in described substrate surface and separates mutually with each internal electrode metal material and each liner metal material of being established in;
Described double-face electrode luminescence chip is welded on the described internal electrode metal material, and described plane electrode luminescence chip is fixedly arranged on the described liner metal material.
5. the package carrier structure of a kind of photoelectric subassembly according to claim 4, it is characterized in that: the package carrier structure of described photoelectric subassembly is provided with at least two outer electrode metal materials.
6. the package carrier structure of a kind of photoelectric subassembly according to claim 4, it is characterized in that: the package carrier structure of described photoelectric subassembly is provided with at least two internal electrode metal materials.
7. according to the package carrier structure of claim 4,5 or 6 described a kind of photoelectric subassemblys, it is characterized in that: described each internal electrode metal material, each liner metal material and each outer electrode metal material surface coverage one welding resisting layer, this welding resisting layer is provided with at least one window in the zone with respect to described each internal electrode metal material; Described welding resisting layer respectively is provided with at least two windows in the zone with respect to described each outer electrode metal material.
8. according to the package carrier structure of claim 4,5 or 6 described a kind of photoelectric subassemblys, it is characterized in that: described substrate is a metal plate, is provided with an insulating barrier between described each internal electrode metal material, each liner metal material and each outer electrode metal material and this substrate.
9. according to the package carrier structure of claim 4,5 or 6 described a kind of photoelectric subassemblys, it is characterized in that: described each internal electrode metal material, each liner metal material and each outer electrode metal material surface coverage one welding resisting layer, this welding resisting layer is provided with at least one window in the zone with respect to described each internal electrode metal material; This welding resisting layer respectively is provided with at least two windows in the zone with respect to described each outer electrode metal material; Described substrate is a metal plate, is provided with an insulating barrier between described each internal electrode metal material, each liner metal material and each outer electrode metal material and this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010243181.2A CN101930937A (en) | 2010-08-03 | 2010-08-03 | Packaging method of photoelectric component and packaging carrier structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010243181.2A CN101930937A (en) | 2010-08-03 | 2010-08-03 | Packaging method of photoelectric component and packaging carrier structure thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101930937A true CN101930937A (en) | 2010-12-29 |
Family
ID=43370015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010243181.2A Pending CN101930937A (en) | 2010-08-03 | 2010-08-03 | Packaging method of photoelectric component and packaging carrier structure thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101930937A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187514A (en) * | 2012-09-17 | 2013-07-03 | 中国科学院福建物质结构研究所 | LED (light-emitting diode) package structure |
-
2010
- 2010-08-03 CN CN201010243181.2A patent/CN101930937A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187514A (en) * | 2012-09-17 | 2013-07-03 | 中国科学院福建物质结构研究所 | LED (light-emitting diode) package structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101779303B (en) | Semiconductor light-emitting device as well as light source device and lighting system including the same | |
| US8810124B2 (en) | AC light emitting device with long-persistent phosphor and light emitting device module having the same | |
| CN100483762C (en) | LED device making method | |
| JP2007189225A (en) | Chip coating type led package, and method of manufacturing same | |
| CN203644815U (en) | LED packaging structure | |
| CN102015961A (en) | Semiconductor light emitting apparatus and light source apparatus using the same | |
| US20170025395A1 (en) | Light Emitting Device | |
| CN100539224C (en) | Light-emitting device | |
| JP6191667B2 (en) | Light emitting device | |
| JP2005223222A (en) | Solid element package | |
| JP2007258620A (en) | Light emitting device | |
| JP2007116117A (en) | Light emitting device | |
| EP3905347B1 (en) | Light-emitting substrate, and lighting device | |
| CN103325778B (en) | Light-emitting device and ligthing paraphernalia | |
| JP5697091B2 (en) | Semiconductor light emitting device | |
| JP2007288138A (en) | Light emitting device | |
| US9752764B2 (en) | Wide-angle emitting LED driven by built-in power and assembly method thereof | |
| CN103633237A (en) | LED (Light Emitting Diode) packaging structure and wafer level packaging method thereof | |
| CN101930937A (en) | Packaging method of photoelectric component and packaging carrier structure thereof | |
| KR101901890B1 (en) | Luminescence device | |
| JP2007116107A (en) | Light emitting device | |
| CN201788973U (en) | Package carrier structure of photoelectric component | |
| CN102931177B (en) | High-color-rendering LED light source based on red light chip direct sealing compensation | |
| JP2008021795A (en) | Light source device | |
| EP3905348B1 (en) | Light-emitting substrate, and lighting device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20101229 |