CN101930916A - Method for forming groove - Google Patents
Method for forming groove Download PDFInfo
- Publication number
- CN101930916A CN101930916A CN200910053372XA CN200910053372A CN101930916A CN 101930916 A CN101930916 A CN 101930916A CN 200910053372X A CN200910053372X A CN 200910053372XA CN 200910053372 A CN200910053372 A CN 200910053372A CN 101930916 A CN101930916 A CN 101930916A
- Authority
- CN
- China
- Prior art keywords
- layer
- etching
- ashing treatment
- reaction chamber
- carried out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
The invention discloses a method for forming a groove, which is used for etching an insulating layer of a semiconductor device to form the groove, wherein the insulating layer consists of an etch stop layer, a low dielectric constant (Low-K) insulating material layer and a hard mask layer which are formed on a semiconductor substrate in sequence. The method comprises the following steps: coating a photoresist layer on the hard mask layer; patterning the photoresist layer; etching the hard mask layer and the Low-K insulating material layer in turn by using the patterned photoresist layer as a mask in an etching reaction cavity, stopping etching in the etch stop layer to form the groove; and performing in-situ ashing treatment on the photoresist layer in two steps in the same reaction cavity, wherein the first step is to dilute residual etching gas in the etching reaction cavity by adopting nitrogen (N2), and the second step is to carry out ashing by adopting the carbon monoxide (CO) or carbon dioxide (CO2). By adopting the method, the defect of facet top profile can be effectively overcome.
Description
Technical field
The present invention relates to semiconductor components and devices manufacturing technology field, particularly a kind of method that forms groove.
Background technology
At present, back segment (back-end-of-line at semiconductor device, BEOL) in the technology, can be according to the different needs multiple layer metal interconnection layer of on Semiconductor substrate, growing, every layer of metal interconnecting layer comprises metal interconnecting wires and insulating barrier, and this just need make groove (trench) and connecting hole, plated metal in above-mentioned groove and connecting hole then to above-mentioned insulating barrier, the metal of deposition is metal interconnecting wires, generally selects for use copper as metal interconnected wire material.Insulating barrier is included in the etch stop layer that forms successively on the Semiconductor substrate, for example silicon carbide layer of nitrating; Low-k (Low-K) insulation material layer for example contains black diamond (black diamond, BD) material of the similar oxide (Oxide) of silicon, oxygen, carbon, protium; Also comprise the hard mask layer (hard mask) that is formed on the Low-K insulation material layer, for example the silicon oxide layer that forms by tetraethoxysilane (TEOS), i.e. TEOS layer.
To the dry etching and the original position ashing method of insulating barrier groove, may further comprise the steps in the prior art:
Step 11, on hard mask layer, be coated with photoresistance (PR, Photo Resist) layer;
Step 12, the described PR layer of patterning.
Step 13, successively hard mask layer and Low-K insulation material layer are carried out etching, stop etching, form groove at etch stop layer.This process is referred to as main etching (ME, Main Etch) process.In existing etching technics, the method for general using plasma etching forms groove.
Step 14, remove the PR layer, promptly carry out the podzolic process of photoresistance glue.
General step original position ashing (the one step in-situ ashing) method that adopts under the low pressure condition, feeds carbon dioxide (C in the prior art
O2) carry out photoresistance glue podzolic process.In-situ refers to the ashing of carrying out photoresistance after etching technics finishes at once, continuous carrying out in same etching reaction chamber.
Need to prove, owing to use the gas of fluoro-gas in the etch step 13 before ashing as etched trench, finish still to have in the etching reaction chamber in the podzolic process of back a large amount of residual fluoro-gas at etching step, these residual fluoro-gas have reduced the selection ratio of photoresistance glue to TEOS layer and Low-K insulation material layer, can continuation carry out etching to the Low-K insulation material layer below TEOS layer and the TEOS layer, and because certain source power (Source Power) and bias power (Bias Power) are used in ashing, therefore cause that the TEOS layer is subjected to certain etching in photoresistance original position podzolic process, thereby occur the defective of step-like opening (facet topprofile) at the interface of TEOS layer and Low-K insulation material layer.Wherein, Source Power is used to provide the density of plasma, and photoresistance glue is carried out ashing; Bias Power is mainly used in the directivity of control plasma ashing, and photoresistance glue is bombarded, and photoresistance glue is thoroughly removed.Fig. 1 is the effect schematic diagram of groove contour of the prior art.As shown in Figure 1, TEOS layer 101 does not form level and smooth groove madial wall with the junction of Low-K insulation material layer 102, but the ladder section appears, this forms barrier layer by physical vapor deposition (PVD) at groove 100 inner surfaces to follow-up, the deposition (BarrierDepositon) of tantalum/tantalum nitride layer (Ta/TaN) for example, and carry out electrochemistry and electroplate (Electrical Chemical Plating), the capital produces and hinders, and therefore will bring adverse influence to the electric property of semiconductor components and devices.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: behind the etching groove, step-like flaws appears in the interface of hard mask layer and low dielectric constant insulating material layer.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of method that forms groove, be used for the insulating barrier of semiconductor device is carried out etching, form groove, described insulating barrier is included in etch stop layer, low-k Low-K insulation material layer and the hard mask layer that forms successively on the Semiconductor substrate, and this method comprises:
On described hard mask layer, be coated with photoresist layer;
The described photoresist layer of patterning;
In the etching reaction chamber, be mask with the patterned light blockage layer, successively described hard mask layer and Low-K insulation material layer are carried out etching, stop etching at etch stop layer, form groove;
In same reaction chamber, in two steps photoresist layer is carried out the original position ashing treatment;
The first step of described ashing treatment is for adopting nitrogen N
2Residual etching gas in the etching reaction chamber is diluted;
Second step of described ashing treatment is for adopting carbon monoxide CO or carbon dioxide CO
2Carry out ashing.
The first step of described ashing treatment also comprises employing CO or CO
2
The first step N of described ashing treatment
2Flow is 300～600 standard cubic centimeters per minute sccm.
The first step N of described ashing treatment
2With CO or CO
2Ratio was greater than 5: 1.
Described first step original position in same etching reaction chamber of photoresist layer being carried out ashing treatment is carried out, and the pressure in the described etching reaction chamber is 15～25 millitorrs; The source power of using is 100～200 watts; The bias power that uses is zero.
The time of photoresist layer being carried out the first step of ashing treatment is 30～50 seconds.
Second step CO or the CO of described ashing treatment
2Flow is 300～800sccm.
Described to photoresist layer carry out ashing treatment second the step in same etching reaction chamber original position carry out, the pressure in the described etching reaction chamber is 50～100 millitorrs; The source power of using is 200～300 watts; The bias power that uses is 100～200 watts.
The time of photoresist layer being carried out second step of ashing treatment is 35～65 seconds.
As seen from the above technical solutions, behind the etching groove of the present invention, when removing photoresistance glue, ashing photoresistance glue original position in the reaction chamber of etching groove is carried out, and be divided into the execution of two steps, in the first step, use nitrogen as diluent gas, mainly the fluoro-gas in the etching reaction chamber is discharged the etching reaction chamber; In second step, carry out ashing photoresistance glue process then.Like this in the main podzolic process in second step, no longer include residual fluoro-gas, thereby can not produce etching action to hard mask layer, make the junction, interface of hard mask layer and Low-K insulation material layer form level and smooth groove madial wall, overcome the defective of facet top profile effectively.
Description of drawings
Fig. 1 is the effect schematic diagram of groove contour of the prior art.
Fig. 2 is to the dry etching of insulating barrier groove and the schematic flow sheet of original position ashing method among the present invention.
Fig. 3 is the effect schematic diagram of the groove contour after use two step original position ashing photoresistance glue (the two step in-situ ashing) methods of the present invention.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
Ashing photoresistance glue of the present invention original position in the reaction chamber of etching groove is carried out, and is divided into the execution of two steps, uses nitrogen (N in the first step
2) as diluent gas (Dilute gas), be mainly used in the fluoro-gas in the etching reaction chamber is discharged the etching reaction chamber; In second step, carry out ashing photoresistance glue process then.So just overcome the defective of facet top profile effectively.
Fig. 2 among the present invention to the dry etching of insulating barrier groove and the schematic flow sheet of original position ashing method, may further comprise the steps:
Step 21, on hard mask layer, be coated with photoresist layer;
Step 22, the described photoresist layer of patterning.After the photoresist layer of coating exposed and develop, just obtained patterned light blockage layer, the effect of patterning depends on existing exposure and developing technique.
Step 23, successively hard mask layer and Low-K insulation material layer are carried out etching, stop etching, form groove at etch stop layer.The method of using plasma etching forms groove as this main etching step 1, and generally adopts fluoro-gas, carries out the etching of groove in the etching reaction chamber.Insulating barrier in the last part technology comprises etch stop layer, Low-K insulation material layer and the hard mask layer that forms successively, and the K value of general Low-K insulation material layer all is less than or equal to 3, in the specific embodiment of the invention, is the BD material, and hard mask layer is the TEOS layer.
Step 24, remove photoresist layer, promptly carry out the podzolic process of original position photoresistance glue.Podzolic process original position in the reaction chamber of etching groove is carried out among the present invention, and is divided into the execution of two steps.
The first step: particularly, use N
2With CO or CO
2Combine photoresistance glue is carried out ashing, can effectively improve the selection ratio of photoresistance glue, only that is to say photoresistance glue is carried out ashing TEOS layer and Low-K insulation material layer, and not etching TEOS layer and Low-K insulation material layer.In the specific embodiment of the invention, N
2With CO or CO
2Ratio was greater than 5: 1, and this is to adopt N because mainly be in this step
2To the residual etching gas in the etching reaction chamber, for example dilution of fluoro-gas is about to fluoro-gas with N
2Discharge the etching reaction chamber together.The CO or the CO that feed
2Flow less, a small amount of CO or CO
2Both photoresistance glue being carried out ashing, also is simultaneously that the podzolic process in second step is done transition, wherein, and N
2Flow be 300～600 standard cubic centimeters per minute (sccm), be preferably 400sccm, 500sccm or 550sccm.
In this step, the pressure in the etching reaction chamber is lower, and preferably, the pressure in the reaction chamber is 15～25 millitorrs (mT), is preferably 15mT, 20mT or 22mT.In the etching reaction chamber, employed Source Power is higher for etching, but employed Bias Power is zero, does not promptly use bias power.Wherein, high source power is used to increase the density of plasma, can improve the ashing rate to photoresistance glue; Simultaneously, bias power is 0, and ion is not accelerated, thus the physical bombardment effect of plasma a little less than, thereby effectively photoresistance glue is handled, and do not produce TEOS layer under the photoresistance glue and Low-K insulation material layer are not carried out etching.In the specific embodiment of the invention, employed source power can be preferably 120W, 150W or 180W for 100～200 watts (W).The time that this step is carried out dilution process decide according to concrete processing procedure, and generally difference is 30～50 seconds (s) in the specific embodiment of the invention with the difference of photoresistance glue thickness, is preferably 30s, 40s or 50s.
Second step: feed CO or CO
2Carry out original position ashing photoresistance glue process.In the specific embodiment of the invention, CO or CO
2Flow be 300～800sccm, preferably, flow is 300sccm, 500sccm or 700sccm.In this step, the pressure in the etching reaction chamber is still lower, and preferably, the pressure in the etching reaction chamber is 50～100 millitorrs (mT), is preferably 60mT, 80mT or 100mT.In the etching reaction chamber, the employed Source Power of etching is 200～300W, is preferably 200W, 250W or 300W; Bias Power is 100～200W, is preferably 100W, 150W or 200W.Employing BiasPower mainly is the directivity for the control plasma in this step, and minimizing is to the injury of Low-K insulation material layer assurance is carried out the original position ashing to make the thorough removal of photoresistance glue to photoresistance glue when.The ashing treatment time of this step is 35～65s, is preferably 40s, 50s or 60s.
Fig. 3 is the effect schematic diagram of the groove contour after use two step original position ashing photoresistance glue (the two step in-situ ashing) methods of the present invention.As shown in Figure 3, after groove is stated processing method in the use, TEOS layer 101 has formed level and smooth groove madial wall with the junction of Low-K insulation material layer 102, and the problem of facet top profile has obtained very big improvement, and formed groove 100 has profile preferably.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. method that forms groove, be used for the insulating barrier of semiconductor device is carried out etching, form groove, described insulating barrier is included in etch stop layer, low-k Low-K insulation material layer and the hard mask layer that forms successively on the Semiconductor substrate, it is characterized in that this method comprises:
On described hard mask layer, be coated with photoresist layer;
The described photoresist layer of patterning;
In the etching reaction chamber, be mask with the patterned light blockage layer, successively described hard mask layer and Low-K insulation material layer are carried out etching, stop etching at etch stop layer, form groove;
In same reaction chamber, in two steps photoresist layer is carried out the original position ashing treatment;
The first step of described ashing treatment is for adopting nitrogen N
2Residual etching gas in the etching reaction chamber is diluted;
Second step of described ashing treatment is for adopting carbon monoxide CO or carbon dioxide CO
2Carry out ashing.
2. the method for claim 1 is characterized in that, the first step of described ashing treatment also comprises employing CO or CO
2
3. method as claimed in claim 2 is characterized in that, the first step N of described ashing treatment
2Flow is 300～600 standard cubic centimeters per minute sccm.
4. method as claimed in claim 3 is characterized in that, the first step N of described ashing treatment
2With CO or CO
2Ratio was greater than 5: 1.
5. as claim 1,2,3 or 4 described methods, it is characterized in that described first step original position in same etching reaction chamber of photoresist layer being carried out ashing treatment is carried out, the pressure in the described etching reaction chamber is 15～25 millitorrs; The source power of using is 100～200 watts; The bias power that uses is zero.
6. method as claimed in claim 5 is characterized in that, the time of photoresist layer being carried out the first step of ashing treatment is 30～50 seconds.
7. the method for claim 1 is characterized in that, second step CO or the CO of described ashing treatment
2Flow is 300～800sccm.
8. method as claimed in claim 7 is characterized in that, described to photoresist layer carry out ashing treatment second the step in same etching reaction chamber original position carry out, the pressure in the described etching reaction chamber is 50～100 millitorrs; The source power of using is 200～300 watts; The bias power that uses is 100～200 watts.
9. method as claimed in claim 8 is characterized in that, the time of photoresist layer being carried out second step of ashing treatment is 35～65 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910053372XA CN101930916B (en) | 2009-06-18 | 2009-06-18 | Method for forming groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910053372XA CN101930916B (en) | 2009-06-18 | 2009-06-18 | Method for forming groove |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101930916A true CN101930916A (en) | 2010-12-29 |
| CN101930916B CN101930916B (en) | 2012-11-28 |
Family
ID=43369998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910053372XA Active CN101930916B (en) | 2009-06-18 | 2009-06-18 | Method for forming groove |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101930916B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851779A (en) * | 2014-02-18 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacture method |
| WO2021227119A1 (en) * | 2020-05-13 | 2021-11-18 | Tcl华星光电技术有限公司 | Method for manufacturing display panel |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4911936B2 (en) * | 2005-09-09 | 2012-04-04 | 東京エレクトロン株式会社 | Plasma ashing method |
-
2009
- 2009-06-18 CN CN200910053372XA patent/CN101930916B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104851779A (en) * | 2014-02-18 | 2015-08-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacture method |
| CN104851779B (en) * | 2014-02-18 | 2017-11-14 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacture method of semiconductor devices |
| WO2021227119A1 (en) * | 2020-05-13 | 2021-11-18 | Tcl华星光电技术有限公司 | Method for manufacturing display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101930916B (en) | 2012-11-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10049891B1 (en) | Selective in situ cobalt residue removal | |
| US7361605B2 (en) | System and method for removal of photoresist and residues following contact etch with a stop layer present | |
| US7344993B2 (en) | Low-pressure removal of photoresist and etch residue | |
| US8591661B2 (en) | Low damage photoresist strip method for low-K dielectrics | |
| JP4825911B2 (en) | Plasma etching and photoresist strip process with defluorination and wafer defluorination steps in intervening chamber | |
| CN100517605C (en) | Method for manufacturing inlaid structure | |
| TW201532139A (en) | Recessing ultra-low K dielectric using remote plasma source | |
| KR20040094821A (en) | An integrated in-situ etch process performed in a multichamber substrate processing system | |
| KR20080093392A (en) | Etch process with controlled critical dimension shrink | |
| WO2006073622A2 (en) | Low-pressure removal of photoresist and etch residue | |
| KR101791685B1 (en) | High Dose Implantation Strip (HDIS) In H2 Base Chemistry | |
| US20070093069A1 (en) | Purge process after dry etching | |
| CN101930916B (en) | Method for forming groove | |
| CN106463345B (en) | Method for dry etching mask layer without oxidizing storage unit and source line | |
| KR101179111B1 (en) | Etching method and recording medium | |
| KR20200102617A (en) | Method of surface treatment of gallium oxide | |
| US20070045227A1 (en) | Method of stripping photoresist | |
| US7045464B1 (en) | Via reactive ion etching process | |
| US20210028017A1 (en) | Method for using ultra thin ruthenium metal hard mask for etching profile control | |
| CN102097360B (en) | The method of etching connection hole | |
| JP3780204B2 (en) | Barrier metal film or adhesion layer forming method and wiring forming method | |
| KR20000071322A (en) | Method of manufacturing a semiconductor device | |
| JP4380414B2 (en) | Manufacturing method of semiconductor device | |
| US10692734B2 (en) | Methods of patterning nickel silicide layers on a semiconductor device | |
| JP2005123406A (en) | Plasma etching method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121119 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121119 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |