CN101918925B - 用于处理器的高关联性高速缓存的第二次机会取代机制 - Google Patents

用于处理器的高关联性高速缓存的第二次机会取代机制 Download PDF

Info

Publication number
CN101918925B
CN101918925B CN200880111266.6A CN200880111266A CN101918925B CN 101918925 B CN101918925 B CN 101918925B CN 200880111266 A CN200880111266 A CN 200880111266A CN 101918925 B CN101918925 B CN 101918925B
Authority
CN
China
Prior art keywords
storage location
block storage
cache
suitable block
access bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200880111266.6A
Other languages
English (en)
Chinese (zh)
Other versions
CN101918925A (zh
Inventor
J·D·威廉姆斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Onasta Intellectual Property Co ltd
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN101918925A publication Critical patent/CN101918925A/zh
Application granted granted Critical
Publication of CN101918925B publication Critical patent/CN101918925B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/124—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being minimized, e.g. non MRU

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN200880111266.6A 2007-09-04 2008-09-04 用于处理器的高关联性高速缓存的第二次机会取代机制 Active CN101918925B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/849,515 US7861041B2 (en) 2007-09-04 2007-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor
US11/849,515 2007-09-04
PCT/US2008/010368 WO2009032275A1 (en) 2007-09-04 2008-09-04 Second chance replacement mechanism for a highly associative cache memory of a processor

Publications (2)

Publication Number Publication Date
CN101918925A CN101918925A (zh) 2010-12-15
CN101918925B true CN101918925B (zh) 2017-05-03

Family

ID=40002967

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200880111266.6A Active CN101918925B (zh) 2007-09-04 2008-09-04 用于处理器的高关联性高速缓存的第二次机会取代机制

Country Status (7)

Country Link
US (1) US7861041B2 (https=)
EP (1) EP2198370B1 (https=)
JP (1) JP5328792B2 (https=)
KR (1) KR101509628B1 (https=)
CN (1) CN101918925B (https=)
TW (1) TWI451330B (https=)
WO (1) WO2009032275A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5426036B2 (ja) 2010-11-25 2014-02-26 インターナショナル・ビジネス・マシーンズ・コーポレーション 複数のプロセッサのメモリ共有化のためのメモリアクセス装置、及びそのアクセス方法
US8615636B2 (en) * 2011-03-03 2013-12-24 International Business Machines Corporation Multiple-class priority-based replacement policy for cache memory
US9063945B2 (en) * 2011-06-14 2015-06-23 International Business Machines Corporation Apparatus and method to copy data
US9378153B2 (en) 2013-08-27 2016-06-28 Advanced Micro Devices, Inc. Early write-back of modified data in a cache memory
CN105938447B (zh) * 2015-03-06 2018-12-14 华为技术有限公司 数据备份装置及方法
US10402337B2 (en) * 2017-08-03 2019-09-03 Micron Technology, Inc. Cache filter
US10725782B2 (en) 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
CN108304214B (zh) * 2017-12-13 2022-05-13 超聚变数字技术有限公司 一种立即数的完整性的校验方法及装置
US10783083B2 (en) 2018-02-12 2020-09-22 Stmicroelectronics (Beijing) Research & Development Co. Ltd Cache management device, system and method
US11561895B2 (en) 2019-09-05 2023-01-24 Advanced Micro Devices, Inc. Oldest operation wait time indication input into set-dueling
US12346265B2 (en) 2019-12-16 2025-07-01 Advanced Micro Devices, Inc. Cache line re-reference interval prediction using physical page address

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1690982A (zh) * 2004-04-28 2005-11-02 惠普开发有限公司 用于交错存储器的系统和方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0222751A (ja) * 1988-07-11 1990-01-25 Mitsubishi Electric Corp 優先順位決定手段
FR2645986B1 (fr) * 1989-04-13 1994-06-17 Bull Sa Procede pour accelerer les acces memoire d'un systeme informatique et systeme pour la mise en oeuvre du procede
US5353425A (en) * 1992-04-29 1994-10-04 Sun Microsystems, Inc. Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature
JPH10198603A (ja) * 1997-01-08 1998-07-31 Canon Inc 情報処理システム及びその制御方法、情報処理装置
US6243791B1 (en) * 1998-08-13 2001-06-05 Hewlett-Packard Company Method and architecture for data coherency in set-associative caches including heterogeneous cache sets having different characteristics
US6490656B1 (en) * 2000-02-18 2002-12-03 Hewlett-Packard Company Retaining state information of an array of elements by subdividing the array into groups of elements
US6823427B1 (en) * 2001-05-16 2004-11-23 Advanced Micro Devices, Inc. Sectored least-recently-used cache replacement
US6732238B1 (en) * 2001-06-08 2004-05-04 Tensilica, Inc. Set-associative cache memory having variable time decay rewriting algorithm
JP3988485B2 (ja) * 2002-02-25 2007-10-10 セイコーエプソン株式会社 キャッシュ回路、情報処理装置及び電子機器
US7062610B2 (en) * 2002-09-30 2006-06-13 Advanced Micro Devices, Inc. Method and apparatus for reducing overhead in a data processing system with a cache
US6901483B2 (en) * 2002-10-24 2005-05-31 International Business Machines Corporation Prioritizing and locking removed and subsequently reloaded cache lines
JP4009304B2 (ja) * 2003-09-19 2007-11-14 松下電器産業株式会社 キャッシュメモリおよびキャッシュメモリ制御方法
EP1684180A4 (en) * 2003-11-12 2008-10-29 Matsushita Electric Industrial Co Ltd CACHE MEMORY AND CONTROL PROCEDURE THEREFOR
JP4036206B2 (ja) * 2004-03-31 2008-01-23 日本電気株式会社 セットアソシアティブキャッシュシステム及びキャッシュメモリの制御方法
US7516275B2 (en) * 2006-04-25 2009-04-07 International Business Machines Corporation Pseudo-LRU virtual counter for a locking cache

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1690982A (zh) * 2004-04-28 2005-11-02 惠普开发有限公司 用于交错存储器的系统和方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Replacement Algorithm for a Fully Associative Cache;Carnevale，MJ etc;《IBM Technical Disclosure Bulletin》;19980101;第41卷(第1期);123页 *

Also Published As

Publication number Publication date
TW200912742A (en) 2009-03-16
US20090063776A1 (en) 2009-03-05
JP2010538390A (ja) 2010-12-09
JP5328792B2 (ja) 2013-10-30
US7861041B2 (en) 2010-12-28
EP2198370B1 (en) 2012-07-11
CN101918925A (zh) 2010-12-15
TWI451330B (zh) 2014-09-01
KR101509628B1 (ko) 2015-04-08
WO2009032275A1 (en) 2009-03-12
KR20100054155A (ko) 2010-05-24
EP2198370A1 (en) 2010-06-23

Similar Documents

Publication Publication Date Title
CN101918925B (zh) 用于处理器的高关联性高速缓存的第二次机会取代机制
JP7553478B2 (ja) 書き込みミスエントリのドレインをサポートする犠牲キャッシュ
US8180981B2 (en) Cache coherent support for flash in a memory hierarchy
US6496902B1 (en) Vector and scalar data cache for a vector multiprocessor
US9513904B2 (en) Computer processor employing cache memory with per-byte valid bits
CN101727405B (zh) 虚拟地址高速缓冲存储器和方法以及处理器
JP5090047B2 (ja) ロックされたキャッシュ内のセットの置換を管理するための方法、コンピュータ・プログラム、キャッシング・システムおよびプロセッサ
US10579531B2 (en) Multi-line data prefetching using dynamic prefetch depth
CN108710582B (zh) 用于基于局部性的指令处理的选择性启用的系统、设备和方法
US7925865B2 (en) Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection
US20100318741A1 (en) Multiprocessor computer cache coherence protocol
US6539457B1 (en) Cache address conflict mechanism without store buffers
CN110362506A (zh) 高速缓存存储器及其中实现的方法
US6557078B1 (en) Cache chain structure to implement high bandwidth low latency cache memory subsystem
US6427189B1 (en) Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline
CN101727406B (zh) 组相联方式的高速缓存装置、高速缓存方法及处理器系统
US6507892B1 (en) L1 cache memory
US10013352B2 (en) Partner-aware virtual microsectoring for sectored cache architectures
US20030182539A1 (en) Storing execution results of mispredicted paths in a superscalar computer processor
US7454580B2 (en) Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations
US7685372B1 (en) Transparent level 2 cache controller
Kandalkar et al. High Performance Cache Architecture Using Victim Cache
Kravtsov Methods of cache memory optimization for multimedia applications

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20250414

Address after: Pennsylvania, USA

Patentee after: Onasta Intellectual Property Co.,Ltd.

Country or region after: U.S.A.

Address before: California, USA

Patentee before: ADVANCED MICRO DEVICES, Inc.

Country or region before: U.S.A.

TR01 Transfer of patent right