CN101916218B - Double-CPU redundancy control system based on analysis redundancy mechanism - Google Patents

Double-CPU redundancy control system based on analysis redundancy mechanism Download PDF

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Publication number
CN101916218B
CN101916218B CN2010102514482A CN201010251448A CN101916218B CN 101916218 B CN101916218 B CN 101916218B CN 2010102514482 A CN2010102514482 A CN 2010102514482A CN 201010251448 A CN201010251448 A CN 201010251448A CN 101916218 B CN101916218 B CN 101916218B
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submodule
cpu
cpu module
control
redundancy
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CN2010102514482A
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CN101916218A (en
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相征
徐连军
单晓明
李亚鹏
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西安电子科技大学
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Abstract

The invention discloses a double-CPU redundancy control system based on analysis redundancy mechanism, mainly solving the problems that the existing double-CPU redundancy control system has long downtime, low CPU use ration and low reliability. The control system is composed of two CPU modules, wherein each CPU module also comprises a data acquisition submodule, an eCAN bus communication submodule, an analysis redundancy mechanism submodule, a redundancy switching submodule and a redundancy control submodule; the two CPU modules adopt the redundancy strategy of 'mutual backup' and realize double CPU synchronization and data exchange by eCAN bus communication; the analysis redundancy mechanism judges the CPU module fault; if the two CPU modules both have no faults, the first CPU module A controls the first load 1, and the second CPU module B controls the second load 2; and if the first CPU module A fails, the second CPU module B takes over the first load 1, vice versa. The system shortens downtime, improves CPU use ration and system reliability, and is suitable for industrial real-time monitoring and the like.

Description

Based on two CPU redundancy control systems of resolving redundancy scheme
Technical field
The invention belongs to electronic circuit field, relate to two CPU redundancy control systems, this system is used for industrial real-time monitoring field.
Background technology
Redundancy control system increases subsequent use key equipment exactly, in case work system breaks down, control system starts stand-by equipment with prestissimo, thereby keeps the operate as normal of system.At industrial control field, the CPU module is the core of control system, in order to improve the reliability of system, the normal pair CPU redundancy control systems that adopt.
Present two CPU redundancy control systems adopt " cold standby " or " Hot Spare " redundancy strategy more.So-called " cold standby " redundancy strategy is exactly when system design; Polygamy is put a cover CPU module as backup; When in case the CPU module of moving breaks down; Can in time change, the CPU module that backs up in this redundancy scheme is not installed on the opertaing device, must quit work a period of time so that change the spare CPU module in case its drawback is the system of breaking down; So-called " Hot Spare " redundancy strategy just is meant that the spare CPU module works online, and does not just participate in control, i.e. the no-output control function; In case participating in the CPU module of control breaks down; It just can take over fault CPU module, and participates in control, and system can not receive shutdown loss.In this redundancy strategy; Two CPU modules have principal and subordinate's branch; The CPU module that is in the Hot Spare state for from, the CPU module of participating in control is main, has the input with the identical system of host CPU module from the CPU module; Unique difference is to work as the host CPU module often, does not possess system's output function from the CPU module." Hot Spare " strategy " cold standby " strategy has saved system downtime, but free of discontinuities operation during the system failure, and reliability is high; But under the normal condition; The host CPU module has been born the whole output functions of system, does not but have any output function from the CPU module, and cpu busy percentage is on the low side; And at the beginning of system's operation, must stipulate that a CPU module is main, and a CPU module is subsequent use, versatility is bad.
Summary of the invention
The objective of the invention is to overcome the shortcoming of above-mentioned prior art, propose a kind of two CPU redundancy control systems, to shorten system downtime, to improve cpu busy percentage and system reliability based on the parsing redundancy scheme.
To achieve these goals, the two CPU redundancy control systems based on the parsing redundancy scheme of the present invention comprise two CPU modules, and wherein these two CPU modules adopt " backup mutually " redundancy strategy, are respectively applied for the different load of control, and each CPU module comprises again:
Data acquisition submodule: be used for the acquisition system input signal, and the data that collect are sent to eCAN bus communication submodule and resolve the redundancy scheme submodule;
ECAN bus communication submodule: be used to realize exchanging with real time data synchronously between first CPU modules A and second the CPU module B; First CPU modules A and second CPU module B are carried out fault judgement data source is provided for resolving the redundancy scheme submodule, guarantee the redundant real-times of switching of two CPU;
Resolve the redundancy scheme submodule: be used to receive the data source that data acquisition submodule and eCAN bus communication submodule provide, and the fault of described two CPU modules is judged, the fault judgement result is sent to redundant switching submodule;
Redundant switching submodule: be used for according to the fault judgement result, to Redundant Control submodule output switch-over control signal;
Redundant Control submodule: be used for the CPU module institute control load that breaks down being taken over according to switch-over control signal; If first CPU modules A fault; Then second CPU module B takes over first load 1, blocks first CPU modules A output control function simultaneously, and vice versa;
Described data acquisition submodule and two-way connection of eCAN bus communication submodule; ECAN bus communication submodule and parsing redundancy scheme unidirectional connection of submodule; Resolve the redundancy scheme submodule and be connected with redundant switching submodule is unidirectional, redundant switching submodule is connected with the Redundant Control submodule is unidirectional.
The present invention has following advantage:
(1) owing to " backup mutually " redundancy strategy that adopts, when first CPU modules A and second equal non-fault of CPU module B, 1, the second CPU module of first CPU modules A control load B control load 2 has improved cpu busy percentage.
(2) owing to adopt the eCAN bus communication to realize that the CPU between two CPU modules is synchronous, guarantee the real-time of redundant switching, improved system reliability.
(3) owing to adopt the parsing redundancy scheme fault of described CPU module to be judged its fault detect response time is 40ms, has shortened system downtime, has improved system reliability.
Description of drawings
Fig. 1 is a general structure block diagram of the present invention;
Fig. 2 is the Redundant Control submodular circuits schematic diagram of first CPU modules A of the present invention;
The Redundant Control submodular circuits schematic diagram of second CPU module B of the present invention during Fig. 3.
Embodiment
With reference to figure 1, the present invention mainly is made up of first CPU modules A, second CPU module B, first load 1 and second load 2, second load 2 of first CPU modules A first load of control 1, the second CPU module B control.Each CPU module comprises data acquisition submodule, eCAN bus communication submodule, resolves redundancy scheme submodule, redundant switching submodule and Redundant Control submodule.Data acquisition submodule and two-way connection of eCAN bus communication submodule; ECAN bus communication submodule and parsing redundancy scheme unidirectional connection of submodule; Resolve the redundancy scheme submodule and be connected with redundant switching submodule is unidirectional, redundant switching submodule is connected with the Redundant Control submodule is unidirectional.Data acquisition submodule acquisition system input signal; And the data that collect are sent to eCAN bus communication submodule and resolve the redundancy scheme submodule; ECAN bus communication submodule is realized exchanging with real time data synchronously between first CPU modules A and second the CPU module B; First CPU modules A and second CPU module B are carried out fault judgement data source is provided for resolving the redundancy scheme submodule; Resolve the data source that redundant sub reception data acquisition submodule and eCAN bus communication submodule provide; And the fault of described two CPU modules judged that the fault judgement result is sent to redundant switching submodule, and this submodule is according to the fault judgement result; To Redundant Control submodule output switch-over control signal, the Redundant Control submodule is taken over the CPU module institute control load that breaks down according to switch-over control signal.Described Redundant Control submodule realizes that with software mode or hardware mode for example the hardware implementation mode of the Redundant Control submodule of first CPU modules A is as shown in Figure 2, and the Redundant Control submodule hardware real-time mode of second CPU module B is as shown in Figure 3.
With reference to Fig. 2; The Redundant Control submodule of first CPU modules A; Be by a logic inverter D, logic inverter E, four input or door H, a 54LS244 impact damper F and a 54LS244 impact damper G form, but are not limited to the 54LS244 impact damper; Wherein four the input or the door H respectively with logic inverter D, logic inverter E and unidirectional connection of 54LS244 impact damper F, not gate E respectively with 54LS244 impact damper F and unidirectional connection of 54LS244 impact damper G.
With reference to Fig. 3; The Redundant Control submodule of second CPU module B; Form by a logic inverter J, logic inverter K, four input or door N, a 54LS244 impact damper L and a 54LS244 impact damper M; But be not limited to the 54LS244 impact damper, wherein four the input or the door N respectively with logic inverter J, logic inverter K and unidirectional connection of 54LS244 impact damper L, not gate K respectively with 54LS244 impact damper L and unidirectional connection of 54LS244 impact damper M.
During system works of the present invention; By the eCAN bus communication submodule of two CPU modules every at a distance from 10ms through send synchronization request, reply, confirmation signal realizes that CPU is synchronous; ECAN bus communication submodule sends the data acquisition instruction to the data acquisition submodule; The data acquisition submodule is to input signal continuous sampling 8 times; 8 groups of data that obtain are found out wherein maximal value and minimum value through ordering and abandoned; 6 groups of remaining data arithmetic means as current acquired data values; And be sent to and resolve redundancy scheme submodule and eCAN bus communication submodule, the eCAN bus submodule of the eCAN bus submodule of first CPU modules A and second CPU module B exchanges acquired data values, and exchange is obtained acquired data values is sent to parsing redundancy scheme submodule; This submodule is the acquired data values of two CPU modules relatively; If acquired data values is consistent, then judges two equal non-fault of CPU module, otherwise read the one-period acquired data values as historical acquired data values; And whether continuation back three synchronizing cycles of two CPU modules acquired data values is consistent; As if inconsistent, calculate the difference of the arithmetic mean acquired data values historical of four cycle acquired data values of first CPU modules A with it, calculate the difference of the arithmetic mean acquired data values historical of four cycle acquired data values of second CPU module B simultaneously with it; Relatively the difference of two CPU modules is big or small; The CPU module that difference is big is determined to existing fault, and the fault detect response time is 40ms, and will judge that fail result is sent to the switching controls submodule; This submodule is according to fail result output switch-over control signal to Redundant Control submodule; This switch-over control signal comprise first CPU modules A to the control signal Mag1 of load 1, first CPU modules A to the control signal Mag1_2 of load 2, second CPU module B to the control signal Mag2 of load 2, second CPU module B to the control signal Mag2_1 of load 1, first CPU modules A to the control signal CON1 of second CPU module B and second CPU modules A control signal CON2 to first CPU module B, the Redundant Control submodule of first CPU modules A receives Mag1_2, Mag2 and CON1 and realizes the control to second load 2, the Redundant Control submodule of second CPU module B receives Mag2_1, Mag1 and CON2 and realizes the control to first load 1.Wherein CON1 passes through the combinational logic realization by first switching enable signal CPU1_EN1 of first CPU modules A, second switching enable signal CPU1_EN2, the 3rd switching enable signal CPU1_EN3 and the 4th switching enable signal CPU1_EN4, and CON2 passes through the combinational logic realization by first switching enable signal CPU2_EN1 of second CPU module B, second switching enable signal CPU2_EN2, the 3rd switching enable signal CPU2_EN3 and the 4th switching enable signal CPU2_EN4.
If when judging the equal non-fault of two CPU modules; It is that 1, second switching enable signal CPU1_EN2 is that 0, the 3rd switching enable signal CPU1_EN3 is that 1 and the 4th switching enable signal CPU1_EN4 is 1 that first of redundant first CPU modules A of switching submodule output of first CPU modules A switches enable signal CPU1_EN1; Logic inverter D is output as 1, four input or door H output signal is 1, and this signal inputs to 54LS244 impact damper F does not enable it; Mag1_2 does not export; Logic inverter E output signal is 0, and this signal inputs to 54LS244 impact damper G enables it, second load 2 of Mag2 output control; It is that 1, second switching enable signal CPU2_EN2 is that 0, the 3rd switching enable signal CPU2_EN3 is that 1 and the 4th switching enable signal CPU2_EN4 is 1 that first of second CPU module B of redundant switching submodule output of second CPU module B switches enable signal CPU2_EN1; Logic inverter J is output as 1; Four inputs or door N output signal are 1; This signal inputs to 54LS244 impact damper L does not enable it, and Mag2_1 does not export, and logic inverter K output signal is 0; This signal inputs to 54LS244 impact damper M enables it, first load 1 of Mag1 output control.
If judge when second CPU module B breaks down; It is that 0, second switching enable signal CPU1_EN2 is that 1, the 3rd switching enable signal CPU1_EN3 is that 0 and the 4th switching enable signal CPU1_EN4 is 0 that first of redundant first CPU modules A of switching submodule output of first CPU modules A switches enable signal CPU1_EN1; Logic inverter D is output as 0, four input or door H output signal is 0, and this signal inputs to 54LS244 impact damper F enables it; Second load 2 of Mag1_2 discharge conection; Logic inverter E output signal is 1, and this signal inputs to 54LS244 impact damper G does not enable it, and Mag2 does not export.
If judge when first CPU modules A breaks down; It is that 0, second switching enable signal CPU1_EN2 is that 1, the 3rd switching enable signal CPU1_EN3 is that 0 and the 4th switching enable signal CPU1_EN4 is 0 that first of second CPU module B of redundant switching submodule output of second CPU module B switches enable signal CPU1_EN1,, logic inverter J is output as 0; Four inputs or door N output signal are 0; This signal inputs to 54LS244 impact damper L enables it, first load 1 of Mag2_1 discharge conection, and logic inverter K output signal is 1; This signal inputs to 54LS244 impact damper M does not enable it, and Mag1 does not export.

Claims (8)

1. the two CPU redundancy control systems based on the parsing redundancy scheme comprise two CPU modules, it is characterized in that this two CPU modules adopt " backup mutually " redundancy strategy, are respectively applied for the different load of control, and each CPU module comprises again:
Data acquisition submodule: be used for the acquisition system input signal, and the data that collect are sent to eCAN bus communication submodule and resolve the redundancy scheme submodule;
ECAN bus communication submodule: be used to realize the synchronous and real time data exchange between first CPU module (A) and second the CPU module (B); First CPU module (A) and second CPU module (B) are carried out fault judgement data source is provided for resolving the redundancy scheme submodule, guarantee the redundant switching of two CPU real-times;
Resolve the redundancy scheme submodule: be used to receive the data source that data acquisition submodule and eCAN bus communication submodule provide, and the fault of described two CPU modules is judged, the fault judgement result is sent to redundant switching submodule;
Redundant switching submodule: be used for according to the fault judgement result, to Redundant Control submodule output switch-over control signal;
Redundant Control submodule: be used for the CPU module institute control load that breaks down being taken over according to switch-over control signal; If first CPU module (A) fault; Then second CPU module (B) taken over first load (1), blocks first CPU module (A) output control function simultaneously; If second CPU module (B) fault, then first CPU module (A) is taken over second load (2), blocks second CPU module (B) output control function simultaneously;
Described data acquisition submodule and two-way connection of eCAN bus communication submodule; ECAN bus communication submodule and parsing redundancy scheme unidirectional connection of submodule; Resolve the redundancy scheme submodule and be connected with redundant switching submodule is unidirectional, redundant switching submodule is connected with the Redundant Control submodule is unidirectional;
The switch-over control signal of described redundant switching submodule output; Comprise first CPU module (A) to the control signal Mag1 of first load (1), first CPU module (A) to the control signal Mag12 of second load (2), second CPU module (B) to the control signal Mag2 of second load (2), second CPU module (B) to the control signal Mag2_1 of first load (1), first CPU module (A) to the control signal CON1 of second CPU module (B) and second CPU module (A) control signal CON2 to first CPU module (B); The Redundant Control submodule of first CPU module (A) receives Mag1_2, Mag2 and CON1 and realizes the control to second load (2), and the Redundant Control submodule of second CPU module (B) receives Mag2_1, Mag1 and CON2 and realizes the control to first load (1).
2. according to claim 1 pair of CPU redundancy control system; It is characterized in that described data acquisition submodule acquisition system input signal; Be continuous sampling 8 times; 8 groups of data that obtain are found out wherein maximal value and minimum value through ordering and abandoned, do sums 6 groups of remaining data on average as current sampled value.
3. according to claim 1 pair of CPU redundancy control system; It is characterized in that described eCAN bus communication submodule; Through send synchronization request, reply, confirmation signal realizes that first CPU module (A) is synchronous with the CPU of second CPU module (B); Be 10ms its synchronizing cycle, sets up the back synchronously and send the data acquisition instruction to the data acquisition submodule.
4. according to claim 1 pair of CPU redundancy control system; It is characterized in that described parsing redundancy scheme submodule; Come the CPU module failure is judged that through first CPU module (A) of real-time contrast and the consistance of second CPU module (B) image data its fault detect response time is 40ms.
5. according to claim 1 pair of CPU redundancy control system is characterized in that described control signal CON1 is through the combinational logic realization by first switching enable signal CPU1_EN1 of first CPU module (A), second switching enable signal CPU1_EN2, the 3rd switching enable signal CPU1_EN3 and the 4th switching enable signal CPU1_EN4.
6. according to claim 1 pair of CPU redundancy control system is characterized in that described control signal CON2 is through the combinational logic realization by first switching enable signal CPU2_EN1 of second CPU module (B), second switching enable signal CPU2_EN2, the 3rd switching enable signal CPU2_EN3 and the 4th switching enable signal CPU2_EN4.
7. according to claim 1 pair of CPU redundancy control system; The Redundant Control submodule that it is characterized in that described first CPU module (A); Be by first logic inverter (D); Second logic inverter (E), the one or four input or door (H), a 54LS244 impact damper (F) and the 2nd 54LS244 impact damper (G) are formed; Wherein the one or four the input or the door (H) respectively with first logic inverter (D), second logic inverter (E) and unidirectional a connection of 54LS244 impact damper (F), second logic inverter (E) respectively with a 54LS244 impact damper (F) and the 2nd unidirectional connection of 54LS244 impact damper (G).
8. according to claim 1 pair of CPU redundancy control system; The Redundant Control submodule that it is characterized in that described second CPU module (B); Form by the 3rd logic inverter (J), the 4th logic inverter (K), the two or four input or door (N), the 3rd 54LS244 impact damper (L) and the 4th 54LS244 impact damper (M); Wherein the two or four the input or the door (N) respectively with the 3rd logic inverter (J), the 4th logic inverter (K) and the 3rd unidirectional connection of 54LS244 impact damper (L), the 4th logic inverter (K) respectively with the 3rd 54LS244 impact damper (L) and the 4th unidirectional connection of 54LS244 impact damper (M).
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CN103546427B (en) * 2012-07-11 2017-02-08 中国银联股份有限公司 Method and system for realizing high availability of encryption machine application
US9891917B2 (en) 2013-03-06 2018-02-13 Infineon Technologies Ag System and method to increase lockstep core availability
CN103198044B (en) * 2013-03-12 2015-09-09 首都师范大学 A kind of PCI dual-redundant CAN bus card
CN103197657B (en) * 2013-04-19 2015-12-02 华自科技股份有限公司 A kind of hot standby changing method of two PCC machines based on CAN
CN104669268B (en) * 2013-11-26 2016-08-03 中国科学院沈阳自动化研究所 A kind of redundancy underwater robot self-control system based on Hot Spare and method
CN103699461A (en) * 2013-11-27 2014-04-02 北京机械设备研究所 Double-host machine mutual redundancy hot backup method
CN103699462B (en) * 2014-01-08 2015-04-08 闽南师范大学 Single chip microprocessor system with reliability design
CN104111881B (en) * 2014-07-25 2016-03-30 中国航天科工集团第二研究院七〇六所 A kind of arbitration device for dual-computer redundancy Hot Spare computing machine
CN104407949A (en) * 2014-11-28 2015-03-11 中国航天科技集团公司第九研究院第七七一研究所 Spaceborne module-level redundant backup system and method
CN104700909B (en) * 2014-12-31 2017-07-28 大亚湾核电运营管理有限责任公司 Nuclear power plant's group's heap security system
US10002056B2 (en) * 2015-09-15 2018-06-19 Texas Instruments Incorporated Integrated circuit chip with cores asymmetrically oriented with respect to each other
CN106597944B (en) * 2016-12-20 2019-04-19 中国船舶重工集团公司第七一三研究所 A kind of two CSTR controller seamless switch-over system and switching method
CN109143091B (en) * 2018-10-15 2020-12-29 四川长虹电器股份有限公司 Battery management system fault FDIR system and method based on double redundancy

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000591A (en) * 2006-12-30 2007-07-18 中国船舶重工集团公司第七一一研究所 Double-machine redundancy system based on embedded CPU
CN101714109A (en) * 2009-11-24 2010-05-26 杭州华三通信技术有限公司 Method and device for controlling mainboard of double CPU system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006344119A (en) * 2005-06-10 2006-12-21 Fujitsu Ltd Storage device, and configuration information management method and program

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101000591A (en) * 2006-12-30 2007-07-18 中国船舶重工集团公司第七一一研究所 Double-machine redundancy system based on embedded CPU
CN101714109A (en) * 2009-11-24 2010-05-26 杭州华三通信技术有限公司 Method and device for controlling mainboard of double CPU system

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