CN101908759B - ESD (Electrostatic Discharge) clamp circuit - Google Patents
ESD (Electrostatic Discharge) clamp circuit Download PDFInfo
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- CN101908759B CN101908759B CN 200910147052 CN200910147052A CN101908759B CN 101908759 B CN101908759 B CN 101908759B CN 200910147052 CN200910147052 CN 200910147052 CN 200910147052 A CN200910147052 A CN 200910147052A CN 101908759 B CN101908759 B CN 101908759B
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- electrostatic discharge
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Abstract
The invention discloses an ESD (Electrostatic Discharge) clamp circuit which comprises a first resistor, a second resistor, a first transistor, a second transistor and a third transistor. The third transistor is taken as a clamp element of the ESD clamp circuit. A parasitic capacitor of the third transistor and the second resistor form a detecting mechanism used for detecting the ESD. A feedback mechanism consisting of the first resistor, the second resistor, the first transistor and the second transistor is used for dredging ESD current.
Description
Technical field
The present invention relates to a kind of protective circuit, and be particularly related to a kind of protective circuit of static discharge.
Background technology
Along with the progress of science and technology, electronic component replaces traditional mechanical organ gradually.No matter electronic component is in manufacture process, or in actual use, Chang Yinwei human body (or machine) contact and so that the static generation static discharge (electrostatic discharge, ESD) that (or in machine) accumulated in the human body.Because the voltage that static discharge produces is far above the born voltage of electronic component, thus can cause the function of electronic component impaired, even produce nonvolatil destruction.In addition, electronic component itself also can be accumulated static, so that electronic component in assembling process, because ground connection produces static discharge, causes the loss that can't expect.
Therefore, cause the element infringement for fear of static discharge, all can take corresponding measure, with the protection electronic component.Fig. 1 and Fig. 2 are known ESD (Electrostatic Discharge) clamp circuit figure.Please refer to Fig. 1, ESD (Electrostatic Discharge) clamp circuit 100 adopts the framework of resistance capacitance (RC) time delay trigger-type.Wherein, resistance R
1And capacitor C
1Form the RC circuit, for detection of static discharge.P channel mos (P-channel metal oxide semiconductor, PMOS) transistor M
P1With N channel mos (N-channel metal oxide semiconductor, NMOS) transistor M
N1Form inverter (invertor) 101, be used for control as the nmos pass transistor M of strangulation element
C1Node T wherein
3Be the output of inverter 101, be coupled to transistor M
P1Drain electrode and transistor M
N1Drain electrode.When static discharge betides power track (power rail) V
DDThe time, in resistance R
1Two-end-point between produce cross-pressure so that the input end of inverter 101 is in electronegative potential.At this moment, inverter 101 output high potentials, turn-on transistor M
C1Form a low impedance path, static discharge current is dredged to power track V
SS, with the core circuit (core circuit) 103 of protection rear end.During the conduct static discharging current, the resistance R of flowing through
1Electric current to capacitor C
1Charging.This moment, the input of inverter 101 was raised to high potential gradually, and inverter 101 outputs are reduced to electronegative potential gradually.Work as capacitor C
1When finishing charging, transistor M
C1Be closed.
Please refer to Fig. 2, ESD (Electrostatic Discharge) clamp circuit 110 adopts the framework of capacitive coupling trigger-type.When static discharge betides power track V
DDThe time, static discharge can pass through capacitor C
2Be coupled to transistor M
C2Grid, and in resistance R
2Two ends produce a cross-pressure, with the nmos pass transistor M of control as the strangulation element
C2This moment transistor M
C2Be switched on to form a low impedance path, static discharge current is dredged to power track V
SSDuring the conduct static discharging current, pass through resistance R
2Discharge, transistor M
C2Grid voltage descend gradually last transistor M
C2Because being pulled down to electronegative potential, its grid voltage closes.
The strangulation element can adopt large-sized field-effect transistor (big field effect transistor, BIGFET) to realize.Because large-sized field-effect transistor has very large channel width (channelwidth), can produce enough low conducting resistance, rapidly static discharge current is dredged to power track V
SSPlease refer to Fig. 1 and Fig. 2, for effective conduct static discharging current, resistance R
1～R
2And capacitor C
1～C
2Must adopt very large resistance value and capacitance, to keep transistor M
C1～M
C2Can keep enough passage ON time to come the conduct static discharging current, that is prolong the time constant of RC circuit.But the RC circuit that possesses excessive resistance value and capacitance in the time of will causing ESD (Electrostatic Discharge) clamp circuit 100 and 110 to be subjected to large noise, has the problem of false triggering easily.Simultaneously, possess the RC circuit of excessive resistance value and capacitance, when being applied in circuit layout (layout), also need sizable layout area.
Adopt the related example of RC time delay trigger-type framework to be published in " the A Compact; Timed-shutoff; MOSFET-based Power Clamp for On-chip ESD Protection " that EOS/ESD symp. (2004) records the 273rd～279 page with reference to people such as Junjun Li, No. the 5946177th, the people's such as James Wesley Miller United States Patent (USP), the people such as Junjun Li are published in " the Design and Characterizationof a Multi-RC-triggered MOSFET-based Power Clamp for On-chip ESDProtection " of the 179th～185 page of EOS/ESD symp. (2006) record, and the people such as Olivier Quittard is published in " the ESD Protection for High-Voltage CMOS Technologies " of the 77th～86 page of EOS/ESD symp. (2006) record.Adopt the related example of capacitive coupling trigger-type framework can be with reference to the United States Patent (USP) of Jeremy C.Smith 7027275B2 number, and the people's such as Thurman John Rodgers United States Patent (USP) 0285854A1 number.By above-mentioned paper or patent as can be known, in order to prolong the time of conducting strangulation element, can utilize the mode of the RC time constant that increases testing circuit, or the control circuit mechanism of taking resistance capacitance to discharge and recharge, the ON time that prolongs control strangulation element passage.But this mode can increase the risk of circuit false triggering when quick power initiation (fast power-on), and will occupy larger layout area.In addition, utilize the control circuit with feedback mechanism to realize clamped circuit, still have the risk because of excessive power supply noise (power noise) false triggering that causes.In addition, the ESD (Electrostatic Discharge) clamp circuit with the aforementioned manner design all needs additional element to finish the design of testing circuit, and this part also can occupy certain layout area.
Summary of the invention
The invention provides a kind of ESD (Electrostatic Discharge) clamp circuit, utilize the parasitic capacitance of strangulation element to realize testing circuit, and the ON time that prolongs the strangulation element with the control circuit with feedback mechanism, to reduce circuit layout area.
The present invention proposes a kind of ESD (Electrostatic Discharge) clamp circuit, comprises the first resistance, the second resistance, the first transistor, transistor seconds and the 3rd transistor.The first end points of the first resistance is coupled to the first path, and the second end points of the second resistance is coupled to the second path.The control end points of the first transistor is coupled to the first end points of the second resistance, and the first end points of the first transistor is coupled to the second end points of the first resistance, and the second end points of the first transistor is coupled to the second path.The control end points of transistor seconds is coupled to the second end points of the first resistance, and the first end points of transistor seconds is coupled to the first path, and the second end points of transistor seconds is coupled to the first end points of the second resistance.The 3rd transistorized control end points is coupled to the first end points of the second resistance, and the 3rd transistorized the first end points is coupled to the first path, and the 3rd transistorized the second end points is coupled to the second path.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Fig. 1～Fig. 2 is known ESD (Electrostatic Discharge) clamp circuit figure.
Fig. 3 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.
Fig. 4 A is the power track V of Fig. 3 and Fig. 1
DDSignal mode graphoid when static discharge occurs.
Fig. 4 B and Fig. 4 C are that the ESD (Electrostatic Discharge) clamp circuit 300 of Fig. 3 is at power track V
DDPart signal simulation drawing when static discharge occurs.
Fig. 4 D is that the ESD (Electrostatic Discharge) clamp circuit 100 of Fig. 1 is at power track V
DDPart signal simulation drawing when static discharge occurs.
Fig. 5 A is the power track V of Fig. 3 and Fig. 1
DDSignal mode graphoid when quick power initiation.
Fig. 5 B and Fig. 5 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 300 when quick power initiation of Fig. 3.
Fig. 5 D is the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 100 when quick power initiation of Fig. 1.
Fig. 6 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.
Fig. 7 A is the power track V of Fig. 6
DDSignal mode graphoid when static discharge occurs.
Fig. 7 B and Fig. 7 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 400 when static discharge occurs of Fig. 6.
Fig. 8 A is the power track V of Fig. 6
DDSignal mode graphoid when quick power initiation.
Fig. 8 B and Fig. 8 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 400 when power supply starts fast of Fig. 6.
Fig. 9 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.
Figure 10 A is the power track V of Fig. 9
DDSignal mode graphoid when suffering noise jamming.
Figure 10 B and Figure 10 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 301 when suffering noise jamming of Fig. 9.
Figure 11～Figure 14 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.
Figure 15 A is the circuit diagram according to first diode of one embodiment of the invention.
Figure 15 B is the circuit diagram according to second diode of another embodiment of the present invention.
[main element symbol description]
100,110: ESD (Electrostatic Discharge) clamp circuit
101: inverter
103: core circuit
300～305: ESD (Electrostatic Discharge) clamp circuit
311,313: diode
400,401: ESD (Electrostatic Discharge) clamp circuit
411,413: diode
500: ESD (Electrostatic Discharge) clamp circuit
C
1～C
2: electric capacity
C
3～C
5: parasitic capacitance
D
1～D
8: diode
R
1～R
6: resistance
M
C1～M
C3: nmos pass transistor
M
C4～M
C5: the PMOS transistor
M
N1～M
N3: nmos pass transistor
M
P1～M
P3: the PMOS transistor
Q
1, Q
2: nmos pass transistor
Q
3, Q
4: the PMOS transistor
t
1～t
13: time point
T
1～T
7: node
V
DD, V
SS: power track
V
THN: critical voltage
Embodiment
Fig. 3 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Fig. 3, ESD (Electrostatic Discharge) clamp circuit 300 comprises the first resistance R
3, the second resistance R
4, the first transistor M
N2, transistor seconds M
P2, and the 3rd transistor M
C3In the present embodiment, the first transistor M
N2Nmos pass transistor, transistor seconds M
P2The PMOS transistor, the 3rd transistor M
C3Be the large-sized field-effect transistor of n passage (n-channel) (BIGFET), yet the present invention is not defined in this.Resistance R
3The first end points (for example: power track V be coupled to the first path
DD), resistance R
4The second end points (for example: power track V be coupled to the second path
SS).Though in this embodiment ESD (Electrostatic Discharge) clamp circuit 300 is configured in power track V
DDWith V
SSBetween, yet those skilled in the art can analogize according to the teaching of present embodiment and are applied to various path.
Transistor M
N2The control end points (for example: grid) be coupled to resistance R
4The first end points, transistor M
N2The first end points (for example: drain electrode) be coupled to resistance R
3The second end points, transistor M
N2The second end points (for example: source electrode) be coupled to power track V
SSTransistor M
P2The control end points (for example: grid) be coupled to resistance R
3The second end points, transistor M
P2The first end points (for example: source electrode) be coupled to power track V
DD, transistor M
P2The second end points (for example: drain electrode) be coupled to resistance R
4The first end points.Transistor M
C3The control end points (for example: grid) be coupled to resistance R
4The first end points, transistor M
C3The first end points (for example: drain electrode) be coupled to power track V
DD, transistor M
C3The second end points (for example: source electrode) be coupled to power track V
SS
Because the transistor M as the strangulation element
C3Has larger channel width, at transistor M
C3Grid and drain electrode between have a larger parasitic capacitance C
3, so parasitic capacitance C
3And resistance R
4Form capacitive coupling trigger-type framework.Fig. 4 A is at power track V among Fig. 3 and Fig. 1
DDSignal mode graphoid when static discharge occurs.Please refer to Fig. 4 A, do not obtaining in the situation of power supply supply, at time point t in this hypothesis
1The time, static discharge betides power track V
DDAt time point t
2The time, power track V
DDVoltage be pulled up to 3 volts by static, the rise time was 5 nanoseconds.At time point t
3The time, static discharge finishes.
Fig. 4 B and Fig. 4 C are that the ESD (Electrostatic Discharge) clamp circuit 300 of Fig. 3 is at power track V
DDPart signal simulation drawing when static discharge occurs.Please be simultaneously with reference to Fig. 3 and Fig. 4 A～Fig. 4 C, when static discharge betides power track V
DDThe time (time point t
1), node T
2Voltage instantaneous also drawn high (shown in Fig. 4 C).Power track V
DDVoltage during by quick lift, static discharge voltage is via parasitic capacitance C
3Be coupled to transistor M
C3Grid, this moment node T
1Voltage also thereupon rise rapidly (shown in Fig. 4 B).Wherein, resistance R
4So that transistor M
N2Grid and the cross-pressure between the source electrode greater than its critical voltage (threshold voltage), cause transistor M
N2Be switched on.At transistor M
N2After being switched on, node T
2Voltage be pulled down to power track V
SSCurrent potential (supposing it is 0 volt), shown in Fig. 4 C.Transistor M
N2The electric current that is switched on and the produces resistance R of flowing through
3, at transistor M
P2Source electrode and grid between produce a cross-pressure.As transistor M
P2Source electrode and the cross-pressure between the grid greater than transistor M
P2Critical voltage the time, transistor M
P2Be switched on and pulled transistor M
C3Grid voltage.As transistor M
C3Source electrode and the cross-pressure between the grid greater than its critical voltage V
THNThe time, transistor M
C3Form a low impedance path, with static discharge current from power track V
DDDredge to power track V
SS
Similarly, transistor M
N2Because being drawn high, its grid voltage produces the larger electric current resistance R of flowing through
3, cause transistor M
P2Source electrode and the cross-pressure between the grid larger, pulled transistor M further
C3Grid voltage, make at power track V
DDStatic discharge current be accelerated and dredge to power track V
SSIn other words, resistance R
3, resistance R
4, transistor M
N2, and transistor M
P2Form a feedback mechanism, according to the generation of static discharge, come turn-on transistor M
C3That is the time length of static discharge generation, determine transistor M
C3ON time.
(time point t when static discharge finishes
3), node T
1Voltage along with power track V
DDVoltage and descend (shown in Fig. 4 B).Transistor M
N2Grid and the cross-pressure between the source electrode reduce so that transistor M
P2Grid and the cross-pressure between the source electrode also reduce thereupon, and close gradually transistor M
C3Passage.Last transistor M
N2, M
P2And M
C3Can't keep conducting, at this moment power track V
DDWith V
SSThe voltage level of the two reach unanimity (that is 0 volt).
Review conventional electrostatic discharge clamped circuit, its transistorized passage can't be kept the state of long-time unlatching during the static discharge generation.Fig. 4 D is that the ESD (Electrostatic Discharge) clamp circuit 100 of Fig. 1 is at power track V
DDPart signal simulation drawing when static discharge occurs.Please be simultaneously with reference to Fig. 1, Fig. 4 A and Fig. 4 D, as power track V
DDVoltage (time point t when being pulled up to 3 volts by static
1～t
2), resistance R
1So that the input of inverter 101 maintains electronegative potential, so node T
3Voltage be pulled up to high potential, namely 3 volts nearly.Afterwards along with capacitor C
1Begin charging, the voltage of inverter 101 inputs rises gradually, and node T
3Voltage descend gradually.As node T
3Voltage be lower than transistor M
C1Critical voltage V
THDuring N, transistor M
C1Passage can't keep the state of unlatching.Therefore, conventional electrostatic discharge clamped circuit 100 may be before static discharge finishes premature closure transistor M
C1, and make core circuit 103 face the impact of static discharge.In other words, the time constant of RC circuit must increase in the conventional electrostatic discharge clamped circuit 100, effectively the conduct static discharging current.
Fig. 5 A is the power track V of Fig. 3 and Fig. 1
DDSignal mode graphoid when quick power initiation.Please refer to Fig. 5 A, at time point t
4The time power supply start fast, suppose power track V
DDVoltage at time point t
5Be pulled up to 1.2 volts, the rise time was 10 nanoseconds.Fig. 5 B and Fig. 5 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 300 when quick power initiation of Fig. 3.Please refer to Fig. 3 and Fig. 5 A～Fig. 5 C, as power track V
DDThe voltage fast rise time, because of parasitic capacitance C
3Coupling effect, node T
1Voltage also rise thereupon, but still maintain transistor M
C3Critical voltage V
THNUnder (shown in Fig. 5 B).Because node T
1Undertension with driving transistors M
N2, so that transistor M
N2Still keep closed condition, so node T
2Voltage can be along with power track V
DDVoltage increase and rise (shown in Fig. 5 C).Node T
2Voltage almost keep and power track V
DDVoltage consistent so that transistor M
P2Still keep closed condition.At power track V
DDRise to after 1.2 volts of burning voltages node T
1Voltage trend towards power track V
SSVoltage level, that is 0 volt.
In comparison, please refer to Fig. 1, Fig. 5 A and Fig. 5 D, as power track V
DDThe voltage fast rise time, node T
3Voltage surpassed transistor M
C1Critical voltage V
THN, cause transistor M
C1By false triggering and conducting.In other words, the time constant of RC circuit must reduce, and could effectively avoid ESD (Electrostatic Discharge) clamp circuit 100 by false triggering.Therefore, in the situation of quick power initiation, ESD (Electrostatic Discharge) clamp circuit 300 possesses the ability of avoiding by false triggering.
Fig. 6 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Fig. 6, ESD (Electrostatic Discharge) clamp circuit 400 comprises the first resistance R
5, the second resistance R
6, the first transistor M
P3, transistor seconds M
N3, and the 3rd transistor M
C4In the present embodiment, the first transistor M
P3The PMOS transistor, transistor seconds M
N3Nmos pass transistor, the 3rd transistor M
C4Be the large-sized field-effect transistor of p passage (p-channel), yet the present invention is not defined in this.Resistance R
5The first end points (for example: power track V be coupled to the first path
SS), resistance R
6The second end points (for example: power track V be coupled to the second path
DD).Transistor M
P3The control end points (for example: grid) be coupled to resistance R
6The first end points, transistor M
P3The first end points (for example: drain electrode) be coupled to resistance R
5The second end points, transistor M
P3The second end points (for example: source electrode) be coupled to power track V
DDTransistor M
N3The control end points (for example: grid) be coupled to resistance R
5The second end points, transistor M
N3The first end points (for example: source electrode) be coupled to power track V
SS, transistor M
N3The second end points (for example: drain electrode) be coupled to resistance R
6The first end points.Transistor M
C4The control end points (for example: grid) be coupled to resistance R
6The first end points, transistor M
C4The first end points (for example: drain electrode) be coupled to power track V
SS, transistor M
C4The second end points (for example: source electrode) be coupled to power track V
DD
Wherein, as the transistor M of strangulation element
C4Has larger channel width.Therefore, at transistor M
C4Grid and drain electrode between have a larger parasitic capacitance C
4, resistance R
6With parasitic capacitance C
4Form RC time delay trigger-type framework.Fig. 7 A is the power track V of Fig. 6
DDSignal mode graphoid when static discharge occurs.Please refer to Fig. 7 A, do not obtaining in the situation of power supply supply, at time point t in this hypothesis
6The time, static discharge betides power track V
DDAt time point t
7The time, power track V
DDVoltage be pulled up to 3 volts by static, the rise time was 5 nanoseconds.At time point t
8The time, static discharge finishes.
Fig. 7 B and Fig. 7 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 400 when static discharge occurs of Fig. 6.Please be simultaneously with reference to Fig. 6 and Fig. 7 A～Fig. 7 C, when static discharge betides power track V
DDThe time (time point t
6), because of the delayed action of RC circuit, parasitic capacitance C
4So that node T
5Voltage be in electronegative potential, and so that transistor M
P3Conducting.Therefore, at time point t
6To t
6' during, node T
4With T
5Voltage all can be along with power track V
DDVoltage level and rise (shown in Fig. 7 B, Fig. 7 C).The transistor M that is switched on
P3The electric current that the produces resistance R of flowing through
5, at transistor M
N3Grid and source electrode between produce a cross-pressure.When this cross-pressure (is node T
4Voltage) surpass transistor M
N3Critical voltage V
THNThe time, namely at time point t
6', transistor M
N3Can be switched on, so that node T
5Voltage (be transistor M
C4Grid voltage) be pulled down near power track V
SSVoltage level (shown in Fig. 7 C).Therefore, transistor M
C4Form a low impedance path, with static discharge current from power track V
DDDredge to power track V
SS
Transistor M
P3Produce larger electric current because its grid is in electronegative potential, cause transistor M
N3Grid and the cross-pressure between the source electrode larger, pull-down transistor M further
C4Grid, static discharge current is accelerated dredges to power track V
SSIn other words, resistance R
5, resistance R
6, transistor M
N3, and transistor M
P3Form a feedback mechanism, according to the generation of static discharge, come turn-on transistor M
C4That is the time length that static discharge occurs determines transistor M
C4ON time.
(time point t when static discharge finishes
8), node T
4Voltage along with power track V
DDVoltage and descend (shown in Fig. 7 B).Transistor M
N3Grid and the cross-pressure between the source electrode reduce so that transistor M
P3Grid and the cross-pressure between the source electrode also reduce thereupon, and close gradually transistor M
C4Passage.Last transistor M
P3, M
N3And M
C4Can't keep conducting, at this moment power track V
DDWith V
SSThe voltage level of the two reach unanimity (that is 0 volt).
Fig. 8 A is the power track V of Fig. 6
DDSignal mode graphoid when quick power initiation.Please refer to Fig. 8 A, suppose at time point t
9The time power supply start fast power track V
DDVoltage at time point t
10Be pulled up to 1.2 volts, the rise time was 10 nanoseconds.Fig. 8 B and Fig. 8 C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 400 when quick power initiation of Fig. 6.Please be simultaneously with reference to Fig. 6, Fig. 8 A～Fig. 8 C, as power track V
DDThe voltage fast rise time (time point t
9～t
10), because node T
5Voltage can catch up with power track V
DDVoltage (shown in Fig. 8 C) so that transistor M
P3With transistor M
C4Pathway closure.At transistor M
P3Under the state that keeps closing, node T
4Voltage can keep below critical voltage V
THN, and then make transistor M
N3Maintenance is closed.Therefore, in the situation of quick power initiation, ESD (Electrostatic Discharge) clamp circuit 400 possesses the ability of avoiding by false triggering.
Under normal use, namely at power track V
DDObtain in the situation of power supply supply, above-mentioned ESD (Electrostatic Discharge) clamp circuit 300 and 400 all has the noise jamming tolerance of certain degree, can't false triggering transistor M
C3With M
C4And generation power track V
DDWith V
SSThe two is the phenomenon of short circuit each other.Yet, when ESD (Electrostatic Discharge) clamp circuit suffers from very large noise jamming (or static discharge) and when triggering, after noise jamming disappeared, breech lock (latch-on) phenomenon may occur ESD (Electrostatic Discharge) clamp circuit.Please refer to Fig. 6, suppose at power track V
DDObtain in the situation of power supply supply, when ESD (Electrostatic Discharge) clamp circuit 400 runs into noise, in resistance R
6Two ends produce a cross-pressure and turn-on transistor M
P3, this moment transistor M
N3Be switched on transistor M according to the feedback mechanism of ESD (Electrostatic Discharge) clamp circuit 400
C4Driven and conducting.After noise disappears, because power track V
DDVoltage can support feedback mechanism to continue running, cause transistor M
C4Continue to be in conducting state, this is latch phenomenon.
Fig. 9 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Fig. 3 and Fig. 9, ESD (Electrostatic Discharge) clamp circuit 301 is similar with ESD (Electrostatic Discharge) clamp circuit 300, therefore below only just both different parts describe.Please refer to Fig. 9, ESD (Electrostatic Discharge) clamp circuit 301 also comprises the first diode 311.In the present embodiment, diode 311 is two diode D
1And D
2Be connected in series mutually the diode string that forms, but the present invention is defined in this.Diode D
1The anode end points be coupled to resistance R
3The second end points, diode D
1The negative electrode end points be coupled to diode D
2The anode end points, diode D
2The negative electrode end points be coupled to transistor M
N2Drain electrode.Those skilled in the art can according to the explanation of present embodiment, revise the quantity of diode in actual applications accordingly.For example, suppose diode D
1And D
2Unlatching (turn-on) voltage be 0.6 volt, then the cut-in voltage of diode 311 is 1.2 (0.6 * 2) volts.When applying one during greater than two ends at diode 311 of 1.2 volts forward bias voltage drop (forward bias), diode 311 will be switched on.In the present embodiment, the cut-in voltage of diode 311 is more than or equal to power track V
DDOperating voltage.Below will illustrate how to utilize this physical characteristic to avoid latch phenomenon.
Figure 10 A is the power track V of Fig. 9
DDSignal mode graphoid when suffering noise jamming.Suppose in time point t at this
11The time, power track V
DDMeet with noise jamming, power track V
DDVoltage be pulled up to 3 volts of (time point t from 1.2 volts
12), voltage rising time was 3 nanoseconds.Figure 10 B and 10C are the part signal simulation drawing of ESD (Electrostatic Discharge) clamp circuit 301 when suffering noise jamming of Fig. 9.When being triggered running when ESD (Electrostatic Discharge) clamp circuit 301 experience noise jamming, because capacitor C
3Coupling effect start the feedback mechanism of ESD (Electrostatic Discharge) clamp circuit 301.At time point t
11～t
12During this time, as node T
7Voltage during greater than the cut-in voltage of diode 311 (shown in Figure 10 C), cause node T
6Voltage also increase (shown in Figure 10 B) with driving transistors M
C3At time point t
12To t
13During this time, utilize the forward bias voltage drop physical characteristic of diode 311, node T
7Voltage can roughly be maintained near 1.5 volts.
(time point t after noise disappears
13), power track V
DDVoltage return back to 1.2 volts, this moment the characteristic by diode 311, node T
7Voltage can roughly equal power track V
DDVoltage.Because at power track V
DDVoltage return back to 1.2 volts after, transistor M
P2Source electrode and the cross-pressure between the grid be lower than its critical voltage so that transistor M
P2Can be closed, and then make node T
6Voltage by drop-down (shown in Figure 10 B).Therefore, after noise disappears, transistor M
C3Passage also close thereupon.
According to above-mentioned explanation, ESD (Electrostatic Discharge) clamp circuit of the present invention can otherwise be realized.Figure 11 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Fig. 3 and Figure 11, the running of ESD (Electrostatic Discharge) clamp circuit 303 is similar with ESD (Electrostatic Discharge) clamp circuit 300.Please refer to Figure 11, ESD (Electrostatic Discharge) clamp circuit 303 also comprises the second diode 313.Diode 313 is two diode D
3And D
4Be connected in series mutually the diode string that forms, but the present invention is not defined in this.Diode D
3The anode end points be coupled to transistor M
P2Drain electrode, diode D
3The negative electrode end points be coupled to diode D
4The anode end points, diode D
4The negative electrode end points be coupled to resistance R
4The first end points.When ESD (Electrostatic Discharge) clamp circuit 303 suffers noise jamming and when running of being triggered, transistor M
C3Driven and conducting.When noise disappears, because the pressure drop of diode 313 causes transistor M
N2Grid voltage descend and be lower than its critical voltage.Transistor M
N2Because its grid voltage is closed less than critical voltage, so that the feedback mechanism of ESD (Electrostatic Discharge) clamp circuit 303 can't be kept running and close transistor M
C3Therefore, the state before ESD (Electrostatic Discharge) clamp circuit 303 can be returned to and not be triggered.
Figure 12 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Fig. 3 and Figure 12, the running of ESD (Electrostatic Discharge) clamp circuit 305 is similar with ESD (Electrostatic Discharge) clamp circuit 300.Please refer to Figure 12, wherein ESD (Electrostatic Discharge) clamp circuit 305 also comprises the first diode 311 and the second diode 313.When ESD (Electrostatic Discharge) clamp circuit 305 suffers noise jamming and when running of being triggered, transistor M
C3Driven and conducting.When noise disappears, by the characteristic of diode 311 and 313, transistor M
P2Grid voltage can be close to power track V
DDVoltage, and transistor M
N2Grid voltage can be close to power track V
SSVoltage.Transistor M
N2With M
P2Because the cross-pressure between its grid and the source electrode is closed less than critical voltage, so the feedback mechanism of ESD (Electrostatic Discharge) clamp circuit 305 can't be kept running, transistor M
C3Passage also close thereupon.
Figure 13 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Fig. 6 and Figure 13, the running of ESD (Electrostatic Discharge) clamp circuit 401 is similar with ESD (Electrostatic Discharge) clamp circuit 400.Please refer to Figure 13, wherein ESD (Electrostatic Discharge) clamp circuit 401 also comprises the first diode 411 and the second diode 413.Diode 411 is two diode D
5And D
6Be connected in series mutually the diode string that forms, and diode 413 is two diode D
7And D
8Be connected in series mutually the diode string that forms, but the present invention is non-limiting in this.Diode D
5The anode end points be coupled to transistor M
P3Drain electrode, diode D
5The negative electrode end points be coupled to diode D
6The anode end points, diode D
6The negative electrode end points be coupled to resistance R
5The second end points.Diode D
7The anode end points be coupled to resistance R
6The first end points, diode D
7The negative electrode end points be coupled to diode D
8The anode end points, diode D
8The negative electrode end points be coupled to transistor M
N3Drain electrode.
Be subject to noise jamming and after being triggered at ESD (Electrostatic Discharge) clamp circuit 401, transistor M
C4Be switched on to dredge noise.When noise disappears, by the characteristic of diode 411 and 413, transistor M
P3Grid voltage can be close to power track V
DDVoltage, and transistor M
N3Grid voltage can be close to power track V
SSVoltage.Transistor M
N3With M
P3Because the cross-pressure between its grid and the source electrode is closed less than critical voltage, so the feedback mechanism of ESD (Electrostatic Discharge) clamp circuit 401 can't be kept running, transistor M
C4Passage also close thereupon.
In other embodiments, the diode 411 and 413 in the ESD (Electrostatic Discharge) clamp circuit 401 can be selected an omission.Number of diodes in the diode 411 and 413 can determine according to design requirement.
Figure 14 is the ESD (Electrostatic Discharge) clamp circuit figure according to one embodiment of the invention.Please refer to Figure 12 and Figure 14, the running of ESD (Electrostatic Discharge) clamp circuit 500 is similar with ESD (Electrostatic Discharge) clamp circuit 305.Please refer to Figure 14, wherein ESD (Electrostatic Discharge) clamp circuit 500 also comprises the 4th transistor M
C5In the present embodiment, the 4th transistor M
C5Be the large-sized field-effect transistor of p passage, yet the present invention is not defined in this.Transistor M
C5The first end points (for example: source electrode) be coupled to power track V
DD, transistor M
C5The second end points (for example: drain electrode) be coupled to power track V
SS, transistor M
C5The control end points (for example: grid) be coupled to resistance R
3The second end points.Wherein, as the transistor M of strangulation element
C5Has larger channel width, therefore at transistor M
C5Grid and drain electrode between have a larger parasitic capacitance C
5Resistance R
3With parasitic capacitance C
5Form RC time delay trigger-type framework, can strengthen detecting the generation of static discharge, and the conduct static discharging current is to power track V
SSFor example, when electrostatic discharge event occured, ESD (Electrostatic Discharge) clamp circuit 500 action that can be triggered was by resistance R
3, resistance R
4, transistor M
N2, and transistor M
P2The feedback mechanism that forms comes into operation, so that transistor M
C3With transistor M
C5But conducting is with the conduct static discharging current.
Be subject to that excessive noise is disturbed and after by false triggering, by resistance R at ESD (Electrostatic Discharge) clamp circuit 500
3, resistance R
4, transistor M
N2, and transistor M
P2The feedback mechanism that forms comes into operation, so that transistor M
C3With transistor M
C5Driven and conducting.When noise disappears, by the characteristic of diode 311 and diode 313, transistor M
P2Grid voltage can be close to power track V
DDVoltage, and transistor M
N2Grid voltage can be close to power track V
SSVoltage.Transistor M
N2With M
P2Because the cross-pressure between its grid and the source electrode is closed less than critical voltage, therefore can stop the feedback mechanism of ESD (Electrostatic Discharge) clamp circuit 500, transistor M
C3With transistor M
C5Passage also close thereupon.
In other embodiments, the diode 311 and 313 in the ESD (Electrostatic Discharge) clamp circuit 500 can be selected an omission.Perhaps, diode 311 and 313 all can be omitted.
In addition, in certain embodiments, Fig. 9, Figure 11, Figure 12, Figure 13 and diode shown in Figure 14 can other mode be implemented.For example, be connected into diode connection structure with transistor and implement Fig. 9, Figure 11, Figure 12, Figure 13 or diode shown in Figure 14.Below with diode among Figure 12 311 example as an illustration, and diode 313 or other graphic shown in diode all can implement with reference to the explanation of diode 311.
Figure 15 A is the circuit diagram according to the diode 311 of one embodiment of the invention explanation Figure 12.Please refer to Figure 15 A, diode 311 comprises diode D
1And D
2In the present embodiment, use nmos pass transistor Q
1With Q
2Be connected into diode connection structure to realize respectively diode D
1And D
2That is to say transistor Q
1The first end points (for example: drain electrode) as diode D
1The first end points (for example: anode), transistor Q
1The second end points (for example: source electrode) as diode D
1The second end points (for example: negative electrode), and transistor Q
1The control end points (for example: grid) be coupled to transistor Q
1Drain electrode.Similar ground, transistor Q
2The first end points (for example: drain electrode) as diode D
2The first end points (for example: anode), transistor Q
2The second end points (for example: source electrode) as diode D
2The second end points (negative electrode), and transistor Q
2The control end points (for example: grid) be coupled to transistor Q
2Drain electrode.
Figure 15 B is the circuit diagram according to the diode 311 of another embodiment of the present invention.Please refer to Figure 15 B, diode 311 comprises diode D
3And D
4In the present embodiment, with PMOS transistor Q
3With Q
4Be connected into diode connection structure to realize respectively diode D
1And D
2That is to say transistor Q
3The first end points (for example: drain electrode) as diode D
1The first end points (for example: negative electrode), transistor Q
3The second end points (for example: source electrode) as diode D
1The second end points (for example: anode), and transistor Q
3The control end points (for example: grid) be coupled to transistor Q
3Drain electrode.In addition, transistor Q
4The first end points (for example: drain electrode) as diode D
2The first end points (for example: negative electrode), transistor Q
4The second end points (for example: source electrode) as diode D
2The second end points (anode), and transistor Q
4The control end points (for example: grid) be coupled to transistor Q
4Drain electrode.
Therefore, those skilled in the art can according to the explanation of Figure 15 A or Figure 15 B, revise the first diode 311, the second diode 313, the first diode 411 or the second diode 413 of Fig. 9 and Figure 11～Figure 14 accordingly.
In sum, in one embodiment of this invention, above-mentioned ESD (Electrostatic Discharge) clamp circuit also comprises the first diode.The first diode is coupled between the first end points of the second end points of the first resistance and the first transistor.
In one embodiment of this invention, above-mentioned the first diode comprises that a plurality of diodes are connected in series mutually and forms the first diode string that wherein two ends of the first diode string are coupled to respectively the first end points of the first transistor and the second end points of the first resistance.
In one embodiment of this invention, above-mentioned ESD (Electrostatic Discharge) clamp circuit also comprises the second diode.The second diode is coupled between the first end points of the second end points of transistor seconds and the second resistance.
In one embodiment of this invention, above-mentioned the second diode comprises that a plurality of diodes are connected in series mutually and forms the second diode string that wherein two ends of the second diode string are coupled to respectively the second end points of transistor seconds and the first end points of the second resistance.
In one embodiment of this invention, above-mentioned ESD (Electrostatic Discharge) clamp circuit also comprises the 4th transistor.The 4th transistorized control end points is coupled to the second end points of the first resistance, and the 4th transistorized the first end points is coupled to the first path, and the 4th transistorized the second end points is coupled to the second path.
With the 3rd transistorized parasitic capacitance and the second resistance as testing mechanism, when detecting static discharge and betide the first path, the feedback mechanism that triggering forms with the first resistance, the second resistance, the first transistor and transistor seconds, come conducting as the 3rd transistor of strangulation element, static discharge current on the first path is dredged to the second path, destroyed core circuit to prevent static discharge current.Simultaneously, this feedback mechanism has the ability of opposing false triggering when quick power initiation.The 4th transistorized parasitic capacitance and the first resistance also can be used as testing mechanism, and can accelerate the conduct static discharging current.When ESD (Electrostatic Discharge) clamp circuit suffers noise jamming, can pass through the first diode and the second diode, avoid feedback mechanism generation latch phenomenon.In addition, ESD (Electrostatic Discharge) clamp circuit in the present embodiment only needs the minority element to implement, and can reduce the area of circuit layout.
Although the present invention with embodiment openly as above; so it is not to limit the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the appended claims person of defining.
Claims (26)
1. ESD (Electrostatic Discharge) clamp circuit is characterized in that this ESD (Electrostatic Discharge) clamp circuit comprises:
The first resistance, the first end points of this first resistance is coupled to the first path;
The second resistance, the second end points of this second resistance is coupled to the second path;
The first transistor, the control end points of this first transistor is coupled to the first end points of this second resistance, and the second end points of this first transistor is coupled to this second path;
The first diode is coupled between the first end points of the second end points of this first resistance and this first transistor;
Transistor seconds, the control end points of this transistor seconds is coupled to the second end points of this first resistance, and the first end points of this transistor seconds is coupled to this first path, and the second end points of this transistor seconds is coupled to the first end points of this second resistance; And
The 3rd transistor, the 3rd transistorized control end points is coupled to the first end points of this second resistance, and the 3rd transistorized the first end points is coupled to this first path, and the 3rd transistorized the second end points is coupled to this second path.
2. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1 is characterized in that this first transistor is nmos pass transistor, and this transistor seconds is the PMOS transistor, and the 3rd transistor is nmos pass transistor.
3. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1 is characterized in that this first transistor is the PMOS transistor, and this transistor seconds is nmos pass transistor, and the 3rd transistor is the PMOS transistor.
4. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1 is characterized in that the 3rd transistor is large-sized field-effect transistor.
5. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1 is characterized in that this ESD (Electrostatic Discharge) clamp circuit also comprises:
The 4th transistor, the 4th transistorized control end points is coupled to the second end points of this first resistance, and the 4th transistorized the first end points is coupled to this first path, and the 4th transistorized the second end points is coupled to this second path.
6. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 5 is characterized in that this first transistor is nmos pass transistor, and this transistor seconds is the PMOS transistor, and the 3rd transistor is nmos pass transistor, and the 4th transistor is the PMOS transistor.
7. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 5 is characterized in that the 3rd transistor AND gate the 4th transistor is large-sized field-effect transistor.
8. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 5 is characterized in that this ESD (Electrostatic Discharge) clamp circuit also comprises:
The second diode is coupled between the first end points of the second end points of this transistor seconds and this second resistance.
9. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 8, it is characterized in that this second diode comprises that a plurality of diodes are connected in series mutually and forms the second diode string, wherein two ends of this second diode string are coupled to respectively the second end points of this transistor seconds and the first end points of this second resistance.
10. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 9 is characterized in that these diodes are to realize with transistor.
11. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1, it is characterized in that this first diode comprises that a plurality of diodes are connected in series mutually and forms the first diode string, wherein two ends of this first diode string are coupled to respectively the first end points of this first transistor and the second end points of this first resistance.
12. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 11 is characterized in that these diodes are to realize with transistor.
13. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1 is characterized in that this ESD (Electrostatic Discharge) clamp circuit also comprises:
The second diode is coupled between the first end points of the second end points of this transistor seconds and this second resistance.
14. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 13, it is characterized in that this second diode comprises that a plurality of diodes are connected in series mutually and forms the second diode string, wherein two ends of this second diode string are coupled to respectively the second end points of this transistor seconds and the first end points of this second resistance.
15. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 14 is characterized in that these diodes are to realize with transistor.
16. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 1 is characterized in that this first path and this second path are power track.
17. an ESD (Electrostatic Discharge) clamp circuit is characterized in that this ESD (Electrostatic Discharge) clamp circuit comprises:
The first resistance, the first end points of this first resistance is coupled to the first path;
The second resistance, the second end points of this second resistance is coupled to the second path;
The first transistor, the control end points of this first transistor is coupled to the first end points of this second resistance, and the second end points of this first transistor is coupled to this second path, and the first end points of this first transistor is coupled to the second end points of this first resistance;
Transistor seconds, the control end points of this transistor seconds is coupled to the second end points of this first resistance, and the first end points of this transistor seconds is coupled to this first path;
The second diode is coupled between the first end points of the second end points of this transistor seconds and this second resistance; And
The 3rd transistor, the 3rd transistorized control end points is coupled to the first end points of this second resistance, and the 3rd transistorized the first end points is coupled to this first path, and the 3rd transistorized the second end points is coupled to this second path.
18. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 17, it is characterized in that this second diode comprises that a plurality of diodes are connected in series mutually and forms the second diode string, wherein two ends of this second diode string are coupled to respectively the second end points of this transistor seconds and the first end points of this second resistance.
19. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 18 is characterized in that these diodes are to realize with transistor.
20. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 17 is characterized in that this first transistor is nmos pass transistor, this transistor seconds is the PMOS transistor, and the 3rd transistor is nmos pass transistor.
21. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 17 is characterized in that this first transistor is the PMOS transistor, this transistor seconds is nmos pass transistor, and the 3rd transistor is the PMOS transistor.
22. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 17 is characterized in that the 3rd transistor is large-sized field-effect transistor.
23. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 17 is characterized in that this ESD (Electrostatic Discharge) clamp circuit also comprises:
The 4th transistor, the 4th transistorized control end points is coupled to the second end points of this first resistance, and the 4th transistorized the first end points is coupled to this first path, and the 4th transistorized the second end points is coupled to this second path.
24. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 23 is characterized in that this first transistor is nmos pass transistor, this transistor seconds is the PMOS transistor, and the 3rd transistor is nmos pass transistor, and the 4th transistor is the PMOS transistor.
25. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 23 is characterized in that the 3rd transistor AND gate the 4th transistor is large-sized field-effect transistor.
26. ESD (Electrostatic Discharge) clamp circuit as claimed in claim 17 is characterized in that this first path and this second path are power track.
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|---|---|---|---|
| CN 200910147052 CN101908759B (en) | 2009-06-08 | 2009-06-08 | ESD (Electrostatic Discharge) clamp circuit |
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| CN102739164A (en) * | 2011-04-15 | 2012-10-17 | 奇景光电股份有限公司 | Noise filtering circuit and integrated circuit |
| US8854103B2 (en) * | 2012-03-28 | 2014-10-07 | Infineon Technologies Ag | Clamping circuit |
| CN104242275A (en) * | 2013-06-06 | 2014-12-24 | 普诚科技股份有限公司 | Electrostatic discharge protection circuit capable of bearing excess electric property stress and avoiding latching |
| CN103515944B (en) * | 2013-10-14 | 2017-03-29 | 辽宁大学 | Using the Power Clamp for ESD protections between power supply and ground of dual-channel technology |
| US9214806B1 (en) * | 2014-08-05 | 2015-12-15 | Mediatek Inc. | ESD protecting circuit |
| CN104362605B (en) * | 2014-11-06 | 2017-05-24 | 北京大学 | Transient trigger static electricity discharge protection circuit |
| GB2537916B (en) * | 2015-04-30 | 2017-08-30 | Advanced Risc Mach Ltd | Power supply clamp |
| CN107887376A (en) * | 2016-09-29 | 2018-04-06 | 扬智科技股份有限公司 | Integrated circuit and its operating method |
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|---|---|---|---|---|
| US6249410B1 (en) * | 1999-08-23 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | ESD protection circuit without overstress gate-driven effect |
| US6768616B2 (en) * | 2001-03-16 | 2004-07-27 | Sarnoff Corporation | Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies |
| US7405915B2 (en) * | 2006-03-03 | 2008-07-29 | Hynix Semiconductor Inc. | Protection circuit against electrostatic discharge in semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6249410B1 (en) * | 1999-08-23 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | ESD protection circuit without overstress gate-driven effect |
| US6768616B2 (en) * | 2001-03-16 | 2004-07-27 | Sarnoff Corporation | Electrostatic discharge protection structures for high speed technologies with mixed and ultra-low voltage supplies |
| US7405915B2 (en) * | 2006-03-03 | 2008-07-29 | Hynix Semiconductor Inc. | Protection circuit against electrostatic discharge in semiconductor device |
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