CN101908714B - All-digital programmable rapid large-current pulse array drive circuit and control method thereof - Google Patents
All-digital programmable rapid large-current pulse array drive circuit and control method thereof Download PDFInfo
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- CN101908714B CN101908714B CN2010102356154A CN201010235615A CN101908714B CN 101908714 B CN101908714 B CN 101908714B CN 2010102356154 A CN2010102356154 A CN 2010102356154A CN 201010235615 A CN201010235615 A CN 201010235615A CN 101908714 B CN101908714 B CN 101908714B
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Abstract
The invention discloses an all-digital programmable rapid large-current pulse array drive circuit and a control method thereof, belonging to the field of conductor laser control and high-precision drive circuits. The drive circuit comprises at least one pulse current generating circuit, at least one power expansion adapter plate circuit, a pulse current signal detection circuit and at least one group of connectors, wherein the input end of the pulse current generating circuit is connected with a pulse voltage signal, and the output end thereof is connected with the input end of the power expansion adapter plate circuit through the connectors; the output end of the power expansion adapter plate circuit is connected with a load; the power expansion adapter plate circuit is connected with the input end of the pulse current signal detection circuit through a positive signal (PS) sampling end and a negative signal (NS) sampling end; and the first output end of the pulse current signal detection circuit is connected with a 12V power supply, the second output end thereof is grounded, the third output end thereof is grounded, and the fourth output end thereof is connected with a CVS (Concurrent Version System) system. The invention realizes the better balance among the pulse amplitude, the pulse change edge and the pulse width.
Description
Technical field
The present invention relates to semiconductor laser control and high accuracy drive circuit field, particularly all-digital programmable rapid large-current pulse array drive circuit and control method thereof.
Background technology
Along with development of electronic technology; The demand of people's paired pulses N-type semiconductor N laser is more and more vigorous; Because this type of high power laser diode or diode laser matrix are operated in the controlled heavy current pulse pattern of duty ratio, therefore more careful and diversified requirement has been proposed the heavy current pulse drive circuit.Along with the development of modern industrial technology, fields such as some particular device detections, technical process control also can need rapid large-current pulse array drive circuit, and digitized programmable operations is carried out in the current impulse of high power density have proposed active demand.
Large-current pulse array drive circuit of the prior art can be difficult to balance usually between pulse amplitude, pulse change edge and pulse duration three; Usually take the open loop circuit structure; Utilize the energy storage characteristic of electric capacity or inductance; Guarantee pulse amplitude and pulse change edge, but will be difficult to satisfy the pulse duration of millisecond magnitude; Even if perhaps guaranteed the pulse duration of millisecond magnitude by force, but pulse amplitude is difficult to again guarantee, in general, when exporting than long pulse, pulse amplitude has obviously falling in various degree.
In order between pulse amplitude, pulse change edge and pulse duration three, to realize balance; Adopted again in the prior art and possessed the close-loop feedback circuit structure that error is amplified; This circuit structure can guarantee the amplitude flatness than long pulse, but often is difficult to satisfy the demand to the pulse change edge of microsecond magnitude; Even if satisfied the demand of pulse amplitude, pulse change edge and pulse duration, all be difficult to meet the demands for the synthetic of the adjusting of pulse duration and complicated impulse waveform.
Summary of the invention
For under prerequisite cheaply, realize balance preferably between pulse amplitude, pulse change edge and the pulse duration three, the invention provides a kind of all-digital programmable rapid large-current pulse array drive circuit and control method thereof,
Said circuit comprises: at least one pulse current generating circuit, at least one power expansion keyset circuit, a pulsed current signal testing circuit and at least one group of connector;
The input of said pulse current generating circuit links to each other with pulse voltage signal; The output of said pulse current generating circuit links to each other through the input of said connector with said power expansion keyset circuit; The output termination load of said power expansion keyset circuit; Said power expansion keyset circuit links to each other through the input of positive sample of signal end PS and negative sample of signal end NS and said pulsed current signal testing circuit; The first output termination 12V power supply of said pulsed current signal testing circuit, second output head grounding, the 3rd output head grounding, the 4th output link to each other with the CVS system.
Said pulse current generating circuit comprises: high speed MOSFET drive circuit, 2 N-channel MOS FET pipes, power tubes move back lotus root electric capacity, pulse damped resistor, the first two-way TVS, the first differential mode filter capacitor, the second differential mode filter capacitor, the first common mode filtering electric capacity, the second common mode filtering electric capacity, the 3rd common mode filtering electric capacity, the 4th common mode filtering electric capacity and big electric current common mode filtering inductance;
Said high speed MOSFET drive circuit links to each other with the grid that the said N-channel MOS FET of grid, downside of the said N-channel MOS FET pipe of high side manages respectively; The drain electrode of the said N-channel MOS FET pipe of high side links to each other with the end that said power tube moves back lotus root electric capacity; Said power tube moves back another termination equipotential of lotus root electric capacity; The drain electrode of the said N-channel MOS FET pipe of source electrode, downside of the said N-channel MOS FET pipe of high side links to each other with an end of the end of an end of said pulse damped resistor, the said first two-way TVS, the said first differential mode filter capacitor, an end of the said first common mode filtering electric capacity respectively; The source electrode of the said N-channel MOS FET pipe of downside, the other end of said pulse damped resistor, the other end of the said first two-way TVS, the other end of the said first differential mode filter capacitor, the other end of the said second common mode filtering electric capacity connect equipotential respectively; The said first differential mode filter capacitor, the said second differential mode filter capacitor, the said first common mode filtering electric capacity, the said second common mode filtering electric capacity, said the 3rd common mode filtering electric capacity, said the 4th common mode filtering electric capacity and said big electric current common mode filtering inductance are formed pi type filter; The middle docking point of said first common mode filtering electric capacity and the said second common mode filtering electric capacity links to each other with casing, and ground connection; The middle docking point of said the 3rd common mode filtering electric capacity and said the 4th common mode filtering electric capacity links to each other with casing, and ground connection.
Said pulse current generating circuit is the N road; After the said pulse current generating circuit in N road is incited somebody to action pulse current process Power Conversion and compensation separately; Through said big electric current common mode filtering inductance; Be delivered to the said power expansion keyset circuit of laser diode one side respectively by said connector independently, wherein, N is a positive integer.
Said power expansion keyset circuit comprises: pulse damped resistor, the first two-way TVS, the second two-way TVS, the second differential mode filter capacitor, the 3rd common mode filtering electric capacity, the 4th common mode filtering electric capacity, big electric current common mode filtering inductance, building-out capacitor, compensating resistance, the noninductive sample resistance of pulse current and pulse edge building-out capacitor;
The said first two-way TVS, said pulse damped resistor link to each other with the filter that the said second differential mode filter capacitor, said the 3rd common mode filtering electric capacity, said the 4th common mode filtering electric capacity, said big electric current common mode filtering inductance are formed; Series arm that said building-out capacitor and said compensating resistance are formed and said pulse damped resistor parallel connection; One end of the noninductive sample resistance of said pulse current, an end of said pulse edge building-out capacitor link to each other with the other end of said compensating resistance respectively, the other end of the other end of said noninductive sample resistance, said pulse edge building-out capacitor links to each other with the other end of the said second two-way TVS respectively, the end of the said second two-way TVS and the other end of said building-out capacitor link to each other.
Said power expansion keyset circuit is the N road; The pulse current that each connector passes over is behind the said big electric current common mode filtering inductance through passage separately; Tandem is to EXT_P end and EXT_N end respectively, and the output pulses after synthesizing outputs to the load wiring end from sub-OUTP of power take-off and OUTN.
Said pulsed current signal testing circuit comprises: first gain resistor; Second gain resistor; First input resistance; Second input resistance; Operational amplifier; Amplifier is moved back lotus root electric capacity; The first small-signal differential mode filter capacitor; The second small-signal differential mode filter capacitor; The first small-signal common mode filtering electric capacity; The second small-signal common mode filtering electric capacity; The 3rd small-signal common mode filtering electric capacity; The 4th small-signal common mode filtering electric capacity; First common mode inductance; Second common mode inductance; Current-limiting resistance and amplifier output current limiting resistance;
Said operational amplifier, said first gain resistor, said second gain resistor, said first input resistance and said second input resistance constitute the differential amplifier of symmetrical structure; The branch road that the said first small-signal common mode filtering electric capacity, the said second small-signal common mode filtering electric capacity, said the 3rd small-signal common mode filtering electric capacity, said the 4th small-signal common mode filtering electric capacity, the said first small-signal differential mode filter capacitor and the said second small-signal differential mode filter capacitor are formed is accomplished the charging to said operational amplifier; The branch road that said first common mode inductance and said second common mode inductance are formed is accomplished the filtering to the amplifying signal of said operational amplifier output; Said current-limiting resistance and said amplifier are moved back branch road that lotus root electric capacity forms and are accomplished the power supply of said operational amplifier and move back lotus root; The characteristic impedance of said amplifier output current limiting resistance and transmission cable is complementary.
Electric current on the said pulse damped resistor is 2-5mA; The value of the said first differential mode filter capacitor, the said second differential mode filter capacitor, the said first common mode filtering electric capacity, the said second common mode filtering electric capacity, said the 3rd common mode filtering electric capacity and said the 4th common mode filtering electric capacity is 100pF-2200pF.
The value of said building-out capacitor is 1000pF-0.1 μ F, and the value of said compensating resistance is 220 Ω-3600 Ω; The noninductive sample resistance of said pulse current is high-power low temperature drift noninductive resistance, and fin is installed, and the value of the noninductive sample resistance of said pulse current need guarantee that peak value detects voltage less than 300mV; Said pulse edge building-out capacitor is high-quality patch capacitor, and takes the structure of a plurality of parallel connections; The magnitude of voltage of the said first two-way TVS, the said second two-way TVS is higher than pulse voltage amplitude.
Said first gain resistor, said second gain resistor, said first input resistance and said second input resistance are precision more than or equal to 1%, temperature is floated the Chip-R less than 200ppm; Said operational amplifier is the high speed amplifier, and common-mode rejection ratio is greater than 100dB.
Said method comprising the steps of:
(1) main control chip FPGA produces the TTL signal; Between high period; The conducting of high side N-channel MOS FET pipe, the pulse voltage of formation and VDR constant amplitude, said pulse voltage forms pulse current in the closed-loop path; The electric charge that power tube moves back in the lotus root electric capacity is managed through said high side N-channel MOS FET, flows into back level element and load;
(2) damping resistance weakens fast-pulse along the ringing pulse that causes; The first two-way TVS suppressor pulse amplitude; Stop pulse energy to the late-class circuit transmission; The pi type filter of effective impulse electric current through constituting by the first differential mode filter capacitor, the first common mode filtering electric capacity, the second common mode filtering electric capacity, the 3rd common mode filtering electric capacity, the 4th common mode filtering electric capacity, the second differential mode filter capacitor, big electric current common mode filtering inductance, and stop electromagnetism spike that the quick conducting of said high side N-channel MOS FET causes and the electromagnetic interference in the level cable induced environment of back to get into the pulse current combiner circuit;
(3) the pulse current connector ingoing power expansion keyset circuit of flowing through; The said first two-way TVS suppresses too high pulse current amplitude; Pulse current passes the effective impulse electric current to load behind said big electric current common mode filtering inductance, said the 3rd common mode filtering electric capacity, said the 4th common mode filtering electric capacity, the said second differential mode filter capacitor, said damping resistance, building-out capacitor, compensating resistance, the noninductive sample resistance of pulse current, pulse edge building-out capacitor and the second two-way TVS;
(4) said effective impulse electric current after the pulse current signal detection circuit is handled, is accomplished the sampling and the control of pulse current amplitude forming positive sample of signal end PS near load one side, forming negative sample of signal end NS away from load end by governor circuit;
(5) after the width of pulse current reaches the setting width; Said TTL signal is between low period; Said high side N-channel MOS FET pipe ends, and downside N-channel MOS FET manages conducting, and pulse current is flowed into by the source electrode of said downside N-channel MOS FET pipe; Flow out from drain electrode, remaining pulse current is released.
The beneficial effect of technical scheme provided by the invention is:
Realized under condition cheaply through circuit provided by the invention and control method, realized balance preferably between pulse amplitude, pulse change edge and the pulse duration three, satisfied the needs in the practical application; And according to the needs in the practical application, can select a plurality of current impulse generation circuit, a plurality of power expansion keyset circuit and a plurality of connector, flexible and convenient to use.
Description of drawings
Fig. 1 is the connection sketch map of binary channels expanding system provided by the invention;
Fig. 2 is the circuit theory diagrams of single channel pulse current generating circuit provided by the invention;
Fig. 3 is the circuit source reason figure of multichannel pulse current generating circuit provided by the invention
Fig. 4 is the circuit theory diagrams of laser diode one side power expansion keyset circuit provided by the invention;
Fig. 5 is the circuit theory diagrams of the multi-channel power expansion keyset circuit of laser diode one side provided by the invention;
Fig. 6 is the circuit theory diagrams of laser diode one lateral vein provided by the invention towards current signal detection circuit;
Fig. 7 is the flow chart of control method provided by the invention.
In the accompanying drawing, the list of parts of each label representative is following:
1: high speed MOSFET drive circuit; The 2:N channel mosfet;
3: power tube moves back lotus root electric capacity; 4: pulse damped resistor;
8: big electric current common mode filtering inductance; 9: building-out capacitor;
10: compensating resistance; 11: the noninductive sample resistance of pulse current;
12: the pulse edge building-out capacitor; 15: current-limiting resistance;
16: amplifier is moved back lotus root electric capacity; 17: amplifier output current limiting resistance;
20: operational amplifier; 21: connector;
22: pulse current generating circuit; 23: power expansion keyset circuit;
24: the pulsed current signal testing circuit; 51: the first two-way TVS (Transient Voltage Suppressor); 52: the second two-way TVS;
61: the first differential mode filter capacitors; 62: the second differential mode filter capacitors;
71: the first common mode filtering electric capacity; 72: the second common mode filtering electric capacity;
73: the three common mode filtering electric capacity; 74: the four common mode filtering electric capacity;
121: the first common mode inductances; 122: the second common mode inductances;
131: the first small-signal common mode filtering electric capacity; 132: the second small-signal common mode filtering electric capacity;
133: the three small-signal common mode filtering electric capacity; 134: the four small-signal common mode filtering electric capacity;
141: the first small-signal differential mode filter capacitors; 142: the second small-signal differential mode filter capacitors;
181: the first gain resistors; 182: the second gain resistors;
191: the first input resistances; 192: the second input resistances.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that embodiment of the present invention is done to describe in detail further below.
For under prerequisite cheaply, realize balance preferably between pulse amplitude, pulse change edge and the pulse duration three, the embodiment of the invention provides a kind of all-digital programmable rapid large-current pulse array drive circuit, referring to Fig. 1, sees hereinafter for details and describes:
This all-digital programmable rapid large-current pulse array drive circuit comprises: at least one pulse current generating circuit 22, at least one power expansion keyset circuit 23, a pulsed current signal testing circuit 24 and an at least one group of connector 21;
The input of pulse current generating circuit 22 links to each other with pulse voltage signal; The output of pulse current generating circuit 22 links to each other with the input of power expansion keyset circuit 23 through Cable_P end, the Cable_N end of connector 21; The output OUTP and the OUTN of power expansion keyset circuit 23 connect load; Power expansion keyset circuit 23 is through positive sample of signal end PS, negative sample of signal end N
SLink to each other with the input of pulsed current signal testing circuit 24; The first output termination 12V power supply, second output head grounding, the 3rd output head grounding, the 4th output and the CVS (Concurrent Versions System, concurrent edition system) of pulsed current signal testing circuit 24 link to each other.
Provide modulation signal TTL_1 to TTL_n by main control chip FPGA, can carry out trickle phase adjusted, finally in the load end synthetic optimized rectangular pulse waveform of index, the perhaps stepped impulse waveform of special shape according to the parameter difference of each passage.Through selecting suitable electronic device and cable, can realize that pulse current intensity is not higher than the rectangular pulse of 80A.
Referring to Fig. 2; This pulse current generating circuit 22 comprises: 1,2 N-channel MOS FET of high speed MOSFET drive circuit pipe 2, power tubes move back lotus root electric capacity 3, pulse damped resistor 4, the first two-way TVS51 (Transient Voltage Suppressor, Transient Voltage Suppressor), the first differential mode filter capacitor 61, the second differential mode filter capacitor 62, the first common mode filtering electric capacity 71, the second common mode filtering electric capacity 72, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74 and big electric current common mode filtering inductance 8;
High speed MOSFET drive circuit 1 links to each other with the grid of high side N-channel MOS FET pipe 2, the grid of downside N-channel MOS FET pipe 2 respectively; The drain electrode of high side N-channel MOS FET pipe 2 links to each other with the end that power tube moves back lotus root electric capacity 3; Power tube moves back another termination equipotential of lotus root electric capacity 3; The source electrode of high side N-channel MOS FET pipe 2 links to each other with the end of an end of pulse damped resistor 4, two-way TVS5, an end of the first differential mode filter capacitor 61, an end of the first common mode filtering electric capacity 71 respectively with the drain electrode of downside N-channel MOS FET pipe 2; The source electrode of downside N-channel MOS FET pipe 2, the other end of pulse damped resistor 4, the other end of the first two-way TVS51, the other end of the first differential mode filter capacitor 61, the other end of the second common mode filtering electric capacity 72 connect equipotential respectively; The first differential mode filter capacitor 61, the second differential mode filter capacitor 62, the first common mode filtering electric capacity 71, the second common mode filtering electric capacity 72, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74 and big electric current common mode filtering inductance 8 are formed pi type filters; The first common mode filtering electric capacity 71 links to each other with casing with the middle docking point of the second common mode filtering electric capacity 72, and reliable ground, the 3rd common mode filtering electric capacity 73 and the middle docking point of the 4th common mode filtering electric capacity 74 link to each other with casing, and reliable ground.
Wherein, 1,2 MOSFET of high speed MOSFET drive circuit pipe 2 produces the high speed potential pulses, and when voltage amplitude during less than 15V, pulse change is along being optimized near the 30nS, and pulse duration and phase place are provided by main control chip FPGA.High speed MOSFET drive circuit 1 can adopt general mosfet driver, perhaps adopts custom circuit structures such as pulse transformer coupling, realizes the driving to symmetrical N-channel MOS FET pipe 2.When the pulse voltage signal of input is in high level; The 2 rapid conductings of high side N-channel MOS FET pipe; Downside N-channel MOS FET pipe 2 is closed simultaneously; Produce pulse voltage at the source electrode of high side N-channel MOS FET pipe 2 and the drain junction chalaza place of downside N-channel MOS FET pipe 2, pulse damped resistor 4 is responsible for absorbing the overshoot energy in the pulse voltages, and various intrinsic or circuit time constants that parasitic capacitance causes in the reduction pulse current generating circuit 22; Can also be at bleed-off circuit residual charge and charge inducing under the off-position, guarantee that pulse current generating circuit 22 sets up physical connection with state of minimum energy and power expansion keyset circuit 23.The first two-way TVS51 can suppress the overshoot voltage that parasitic oscillation causes; And absorb transient state bidirectional strength impulse current among the first two-way TVS51; Local semiconductor device such as MOSFET had both been protected; Excessive overshoot voltage can not occur in the pulse voltage that can guarantee again from pulse current generating circuit 22, to export, protect the connector 21 and power expansion keyset circuit 23 of back segment to greatest extent.The first differential mode filter capacitor 61, the second differential mode filter capacitor 62 are responsible for the pace of change of suppressor pulse voltages, make circuit can get into the pulse meadow faster, and the unnecessary DM EMI of filtering; The common mode disturbances that the first common mode filtering electric capacity 71, the second common mode filtering electric capacity 72, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74 and big electric current common mode filtering inductance 8 are responsible in the filtering circuits; The first differential mode filter capacitor 61, the second differential mode filter capacitor 62, the first common mode filtering electric capacity 71, the second common mode filtering electric capacity 72, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74 and big electric current common mode filtering inductance 8 can stop digit chips such as 2 N-channel MOS FET pipes 2 and FPGA to produce switching noise ingoing powers expansion keyset circuit 23, also can avoid internal control circuit to be upset the operate as normal sequential by the strong electromagnetic in the external world.This pulse current generating circuit 22 produces the Large-power High-Speed pulse voltage gets into connector 21 behind foregoing circuit Cable_P end and Cable_N end.
Further; Pulse current generating circuit 22 can be formed the N road; Referring to Fig. 3, after N road pulse current generating circuit 22 is incited somebody to action pulse current process Power Conversion and compensation separately, through big electric current common mode filtering inductance 8; Be delivered to the power expansion keyset circuit 23 of laser diode one side by connector 21 " Cable_1_P, Cable_1_N " independently, the value of N is a positive integer.
Referring to Fig. 4, this power expansion keyset circuit 23 comprises: pulse damped resistor 4, the first two-way TVS51, the second two-way TVS52, the second differential mode filter capacitor 62, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74, big electric current common mode filtering inductance 8, building-out capacitor 9, compensating resistance 10, pulse current is noninductive sample resistance 11 and pulse edge building-out capacitor 12;
The filter that the first two-way TVS51, pulse damped resistor 4 and the second differential mode filter capacitor 62, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74, big electric current common mode filtering inductance 8 are formed links to each other; Series arm and 4 parallel connections of pulse damped resistor that building-out capacitor 9, compensating resistance 10 are formed; One end of pulse current is noninductive sample resistance 11, an end of pulse edge building-out capacitor 12 link to each other with the other end of compensating resistance 10 respectively, the other end of the other end of noninductive sample resistance 11, pulse edge building-out capacitor 12 links to each other with the other end of the second two-way TVS52 respectively, the end of the second two-way TVS52 and the other end of building-out capacitor 9 link to each other.
Power expansion keyset circuit 23 is responsible for accomplishing the synthetic of single channel or multichannel pulse voltage, and in load, forms pulse current, finally realizes the synthetic of high-speed pulse electric current.The pulse voltage that each group provides through connector 21 merges circuit through big electric current common mode filtering inductance 8 ingoing powers independently.The first two-way TVS51 in power expansion keyset circuit 23 and connector 21 porch is responsible for being suppressed at 21 access moments of connector because impulse current or the voltage that the electric field imbalance causes can stop electrostatic discharge pulses to get into pulsed current signal testing circuit 24 simultaneously.Building-out capacitor 9, compensating resistance 10 constitute phase compensating circuit, and the pulse ripple when inhibition leggy heavy current pulse is synthetic, and appropriate inhibition pulse change edge prevent to occur in the loop too much parasitic oscillation.The second two-way TVS52 is responsible for near carrying out the inhibition of unexpected pulse energy in the position of load, farthest protects the safety of load to drive.Among Fig. 2, the amplitude of pulse current is noninductive sample resistance 11 is used for detecting pulse current can reduce the accumulated error that signal transformation causes according to the Ohm's law current strength that converts; Pulse edge building-out capacitor 12 is used for compensating because the high frequency loss that the access of the noninductive sample resistance 11 of pulse current causes; Simultaneously also a filtering part can be so that the faster and better entering stable state of pulsed current signal testing circuit 24 because load characteristic changes the current fluctuation that causes.
Wherein, the function of the second differential mode filter capacitor 62, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74, big electric current common mode filtering inductance 8 and pulse damped resistor 4 is the same with the function in the pulse current generating circuit 22, repeats no more at this.
Further; Power expansion keyset circuit 23 can be formed the N road; Referring to Fig. 5; The pulse current that passes in each connector 21 " Cable_1_P, Cable_1_N " is behind the big electric current common mode filtering inductance 8 through passage separately, and tandem is to EXT_P end and EXT_N end respectively, and the output pulses after synthesizing outputs to the load wiring end from sub-OUTP of power take-off and OUTN.Pulse current is noninductive, and sample resistance 11 can reduce resistance along with the increase of peak pulse electric current, and in order between power consumption and signal to noise ratio, to obtain balance preferably, peak sample voltage is usually in 300mV.
Referring to Fig. 6, this pulsed current signal testing circuit 24 comprises: first gain resistor 181, second gain resistor 182, first input resistance 191, second input resistance 192, operational amplifier 20, amplifier are moved back lotus root electric capacity 16, the first small-signal differential mode filter capacitor 141, the second small-signal differential mode filter capacitor 142, the first small-signal common mode filtering electric capacity 131, the second small-signal common mode filtering electric capacity 132, the 3rd small-signal common mode filtering electric capacity 133, the 4th small-signal common mode filtering electric capacity 134, first common mode inductance 121, second common mode inductance 122, current-limiting resistance 15 and amplifier output current limiting resistance 17;
The resistance value of first gain resistor 181, second gain resistor 182, first input resistance 191, second input resistance 192 is taken as tens kilohms usually; Its ratio has determined the multiple that signal is exaggerated; Therefore can adopt simple circuit configuration; Need not positive sample of signal end PS, negative sample of signal end NS are cushioned, can directly amplify, reduce the phase delay and the distortion of high-speed pulse current signal waveform.For the characteristic impedance with signal-transmitting cable is complementary, protection operational amplifier 20, prevent that unexpected cable short circuit from causing the serious overload of operational amplifier 20 and damage, it is near 120 ohm that amplifier output current limiting resistance 17 is selected resistances usually.The branch road that the first small-signal common mode filtering electric capacity 131, the second small-signal common mode filtering electric capacity 132, the 3rd small-signal common mode filtering electric capacity 133, the 4th small-signal common mode filtering electric capacity 134, the first small-signal differential mode filter capacitor 141 and the second small-signal differential mode filter capacitor 142 are formed is accomplished the branch road that charging to operational amplifier 20, first common mode inductance 121, second common mode inductance 122 form and is accomplished the filtering to the amplifying signal of operational amplifier 20 outputs; The electromagnetism spike FD feed that stops the high-power electric current pulse of load end to cause is simultaneously handled and control circuit, during the random digit noise that equally also prevents control circuit is added to loop of power circuit along the small-signal path.
In circuit structure, can design according to physical circuit; The concrete assembling mode of corresponding device among the adjustment foregoing circuit figure; The mode that loads in mixture that parallel connection and series connection can occur; And concrete parameter value can see hereinafter for details and describe along with the adjustment in power grade and the layout generation to a certain degree of device on PCB:
According to design requirement, select N-channel MOS FET pipe 2 and high speed MOSFET driving circuit drives device 1, also can select for use general driving IC to replace high speed MOSFET drive circuit 1.
According to pulse duration; The design power pipe moves back the capacity and the organizational form of lotus root electric capacity 3; Capacity and organizational form that power tube moves back lotus root electric capacity 3 are preferably employing low capacity patch capacitor and big capacity electrolysis compound mode; The big more impulse waveform of capacity is good more, but can increase the volume and the cost of circuit, need compromise according to the applicable cases of reality and choose.
Need guarantee to flow through on the pulse damped resistor 4 electric current of about 2-5mA during according to the amplitude strobe pulse damped resistor 4 of pulse voltage; During concrete work; Can weaken the ringing pulse energy in the circuit; And the electromagnetic energy of rapid consume residual or induction under powering-off state, guarantee to be in the safety of the LD module of connection status; When pulse voltage amplitude is big, can select the mode of a plurality of pulse damped resistor 4 parallel connections, prevent that individual pulse damped resistor 4 is overheated, a plurality of resistance parallel connections can also reduce the influence of the stray inductance of resistance lead to waveform, improve damping.
The magnitude of voltage of Transient Voltage Suppressor TVS should be a little more than pulse voltage amplitude, otherwise causes the chain damage of power circuit device easily.
The parameter of the first differential mode filter capacitor 61, the second differential mode filter capacitor 62, the first common mode filtering electric capacity 71, the second common mode filtering electric capacity 72, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74 should connect according to concrete circuit regulate; General value is between 100pF-2200pF; Guaranteed that in the signal bandwidth of design what promptly can the filtering electromagnetic interference can exceed again influences the impulse waveform quality.
Big electric current common mode filtering inductance 8 mainly by the peak strength decision of pulse current, selects suitable core material and winding structure to get final product.
For fear of the influence of a large amount of uncertain stray parameters, pulse current generating circuit 22 is preferably and adopts modern power electronic circuit method for designing to design.
Building-out capacitor 9 can be adjusted according to the demand on pulse change edge with compensating resistance 10, and the value of general indemnity electric capacity 9 can adopt the mode of a plurality of building-out capacitor 9 parallel connections between 1000pF-0.1 μ F; The value of compensating resistance 10 between 3600 Ω, also can adopt the mode of a plurality of compensating resistance 10 parallel connections at 220 Ω, reduces the influence of the series inductance of resistance itself.
Pulse current is noninductive, and sample resistance 11 will be selected high-power low temperature drift noninductive resistance for use; And fin to be installed; The value of pulse current is noninductive sample resistance 11 need guarantee that generally peak value detects voltage＜300mV; For example for the pulse current of 100A, the resistance of its pulse current is noninductive sample resistance 11 is chosen as 2.5m Ω and gets final product.
Pulse edge building-out capacitor 12; Be used for compensating because the high frequency response decay that the intrinsic parasitic electricity of the great current lead wire of sample resistance 11 is caused; This pulse edge building-out capacitor 12 should be selected high-quality patch capacitor for use; And to take the structure of a plurality of parallel connections, and its bank capability is according to the side circuit selection of parameter, and general span is in 4700pF; The lead-in wire of pulse edge building-out capacitor 12 will be attempted by the two ends of the noninductive sample resistance 11 of pulse current with the shortest mode, otherwise stray inductance can cause the ringing of pulse current.
Positive sample of signal end PS, negative sample of signal end NS will have independently, and wiring is connected with two lead ends of the noninductive sample resistance 11 of pulse current; And guarantee not have on the signal path feed-in of heavy current pulse; Prevent that big current signal from causing interference to sampled signal, causes excessive measure error.
During practical application, can require to select single power supply or dual power supply according to concrete circuit design.
Pulse current testing circuit 22 directly is integrated in power expansion keyset circuit 23 inside; All adopt pi type filters on the power supply of pulse current testing circuit 22 and the signaling path and be that the control core circuit is isolated with power expansion keyset circuit 23 with FPGA, prevent that output pulses from disturbing the back level to control and the operate as normal of data acquisition circuit.
In sum; The embodiment of the invention provides a kind of all-digital programmable rapid large-current pulse array drive circuit; Realized under condition cheaply through this circuit; Realize balance preferably between pulse amplitude, pulse change edge and the pulse duration three, satisfied the needs in the practical application; And according to the needs in the practical application, can select a plurality of current impulse generation circuit, a plurality of power expansion keyset circuit and a plurality of connector, flexible and convenient to use; And solved emerging semiconductor device such as industrial semiconductor laser, medical semiconductor laser, or special test occasion need satisfy the requirement of precise current amplitude and microsecond magnitude pulse edge simultaneously.
For under prerequisite cheaply; Realize balance preferably between pulse amplitude, pulse change edge and the pulse duration three; The embodiment of the invention provides a kind of control method of all-digital programmable rapid large-current pulse array drive circuit, referring to Fig. 7, sees hereinafter for details and describes:
101: main control chip FPGA produces the TTL signal; Between high period; High side N-channel MOS FET manages 2 conductings, the pulse voltage of formation and VDR constant amplitude, and this voltage forms pulse current in the closed-loop path; Power tube moves back the N-channel MOS FET pipe 2 of electric charge through high side in the lotus root electric capacity 3, flows into back level element and load;
Wherein, The N-channel MOS FET of high side manages the time of 2 conductings generally in 20ns; In practical application; As long as the formation that power tube moves back lotus root electric capacity 3 meets the requirement in the practical application, just can manage for 2 conducting moments at high side N-channel MOS FET is that late-class circuit provides enough energy, and the steep of assurance pulse and pulse amplitude do not have significantly and fall.
102: damping resistance 4 weakens fast-pulse along the ringing pulse that causes; The first two-way TVS51 suppressor pulse amplitude; Stop pulse energy to the late-class circuit transmission; The pi type filter of effective impulse electric current through constituting by the first differential mode filter capacitor 61, the first common mode filtering electric capacity 71, the second common mode filtering electric capacity 72, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74, the second differential mode filter capacitor 62, big electric current common mode filtering inductance 8, and stop electromagnetism spike that the quick conducting of high side N-channel MOS FET2 causes and the electromagnetic interference in the level cable induced environment of back to get into the pulse current combiner circuit;
103: the pulse current connector 21 ingoing powers expansions keyset circuit 23 of flowing through; The first two-way TVS51 suppresses too high pulse current amplitude; Pulse current passes the effective impulse electric current to load behind big electric current common mode filtering inductance 8, the 3rd common mode filtering electric capacity 73, the 4th common mode filtering electric capacity 74, the second differential mode filter capacitor 62, damping resistance 4, building-out capacitor 9, compensating resistance 10, pulse current is noninductive sample resistance 11, pulse edge building-out capacitor 12 and the second two-way TVS52;
104: the effective impulse electric current after pulse current signal detection circuit 24 is handled, is accomplished the sampling and the control of pulse current amplitude forming positive sample of signal end PS near load one side, forming negative sample of signal end NS away from load end by governor circuit;
105: after the width of pulse current reached the setting width, the TTL signal was between low period, and high side N-channel MOS FET pipe 2 ends; Downside N-channel MOS FET manages 2 conductings; Pulse current is flowed into by the source electrode of downside N-channel MOS FET pipe 2, flows out from drain electrode, and remaining pulse current will be released.
Further; This step is specially: the energy of storing in the stray inductance in the pulse current bang path can form self induction electromotive force in the loop, it is constant to keep the pulse current direction, and pulse current is flowed into by the source electrode of downside N-channel MOS FET pipe 2; Flow out from drain electrode; Remaining pulse current will be released, thereby has guaranteed that the pulse current in the load reduces rapidly, can not produce reverse current.
Wherein, If downside N-channel MOS FET pipe 2 conducting rapidly in time; The self induction electromotive force of the stray inductance initiation in the pulse current bang path can be ended and increase fast owing to the rapid of high side N-channel MOS FET pipe 2; Can the negative pole of a large amount of positive charges in load be gathered, thereby load is formed reverse drive voltages, this will produce serious damage to the LD module.
Further, when heterogeneous operation, FPGA can also regulate the high level width and the relative phase relation of the TTL signal of each phase, thereby in load, synthesize programmable pulse current waveform according to actual needs flexibly.
In sum; The embodiment of the invention provides a kind of control method of all-digital programmable rapid large-current pulse array drive circuit; Realized under condition cheaply through this method; Realize balance preferably between pulse amplitude, pulse change edge and the pulse duration three, satisfied the needs in the practical application.
It will be appreciated by those skilled in the art that accompanying drawing is the sketch map of a preferred embodiment, the invention described above embodiment sequence number is not represented the quality of embodiment just to description.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. all-digital programmable rapid large-current pulse array drive circuit; It is characterized in that said circuit comprises: at least one pulse current generating circuit, at least one power expansion keyset circuit, a pulsed current signal testing circuit and at least one group of connector;
The input of said pulse current generating circuit links to each other with pulse voltage signal; The output of said pulse current generating circuit links to each other through the input of said connector with said power expansion keyset circuit; The output termination load of said power expansion keyset circuit; Said power expansion keyset circuit links to each other through the input of positive sample of signal end PS and negative sample of signal end NS and said pulsed current signal testing circuit; The first output termination 12V power supply of said pulsed current signal testing circuit, second output head grounding, the 3rd output head grounding, the 4th output link to each other with the CVS system;
Wherein, said pulse current generating circuit comprises: high speed MOSFET drive circuit, 2 N-channel MOS FET pipes, power tubes move back lotus root electric capacity, pulse damped resistor, the first two-way TVS, the first differential mode filter capacitor, the second differential mode filter capacitor, the first common mode filtering electric capacity, the second common mode filtering electric capacity, the 3rd common mode filtering electric capacity, the 4th common mode filtering electric capacity and big electric current common mode filtering inductance;
Said high speed MOSFET drive circuit links to each other with the grid that the said N-channel MOS FET of grid, downside of the said N-channel MOS FET pipe of high side manages respectively; The drain electrode of the said N-channel MOS FET pipe of high side links to each other with the end that said power tube moves back lotus root electric capacity; Said power tube moves back another termination equipotential of lotus root electric capacity; The drain electrode of the said N-channel MOS FET pipe of source electrode, downside of the said N-channel MOS FET pipe of high side links to each other with an end of the end of an end of said pulse damped resistor, the said first two-way TVS, the said first differential mode filter capacitor, an end of the said first common mode filtering electric capacity respectively; The source electrode of the said N-channel MOS FET pipe of downside, the other end of said pulse damped resistor, the other end of the said first two-way TVS, the other end of the said first differential mode filter capacitor, the other end of the said second common mode filtering electric capacity connect equipotential respectively; The said first differential mode filter capacitor, the said second differential mode filter capacitor, the said first common mode filtering electric capacity, the said second common mode filtering electric capacity, said the 3rd common mode filtering electric capacity, said the 4th common mode filtering electric capacity and said big electric current common mode filtering inductance are formed pi type filter; The middle docking point of said first common mode filtering electric capacity and the said second common mode filtering electric capacity links to each other with casing, and ground connection; The middle docking point of said the 3rd common mode filtering electric capacity and said the 4th common mode filtering electric capacity links to each other with casing, and ground connection;
Wherein, said power expansion keyset circuit comprises: pulse damped resistor, the first two-way TVS, the second two-way TVS, the second differential mode filter capacitor, the 3rd common mode filtering electric capacity, the 4th common mode filtering electric capacity, big electric current common mode filtering inductance, building-out capacitor, compensating resistance, the noninductive sample resistance of pulse current and pulse edge building-out capacitor;
The said first two-way TVS, said pulse damped resistor link to each other with the filter that the said second differential mode filter capacitor, said the 3rd common mode filtering electric capacity, said the 4th common mode filtering electric capacity, said big electric current common mode filtering inductance are formed; Series arm that said building-out capacitor and said compensating resistance are formed and said pulse damped resistor parallel connection; One end of the noninductive sample resistance of said pulse current, an end of said pulse edge building-out capacitor link to each other with the other end of said compensating resistance respectively, the other end of the other end of said noninductive sample resistance, said pulse edge building-out capacitor links to each other with the other end of the said second two-way TVS respectively, the end of the said second two-way TVS and the other end of said building-out capacitor link to each other;
Wherein, said pulsed current signal testing circuit comprises: first gain resistor, second gain resistor, first input resistance, second input resistance, operational amplifier, amplifier are moved back lotus root electric capacity, the first small-signal differential mode filter capacitor, the second small-signal differential mode filter capacitor, the first small-signal common mode filtering electric capacity, the second small-signal common mode filtering electric capacity, the 3rd small-signal common mode filtering electric capacity, the 4th small-signal common mode filtering electric capacity, first common mode inductance, second common mode inductance, current-limiting resistance and amplifier output current limiting resistance;
Said operational amplifier, said first gain resistor, said second gain resistor, said first input resistance and said second input resistance constitute the differential amplifier of symmetrical structure; The branch road that the said first small-signal common mode filtering electric capacity, the said second small-signal common mode filtering electric capacity, said the 3rd small-signal common mode filtering electric capacity, said the 4th small-signal common mode filtering electric capacity, the said first small-signal differential mode filter capacitor and the said second small-signal differential mode filter capacitor are formed is accomplished the charging to said operational amplifier; The branch road that said first common mode inductance and said second common mode inductance are formed is accomplished the filtering to the amplifying signal of said operational amplifier output; Said current-limiting resistance and said amplifier are moved back branch road that lotus root electric capacity forms and are accomplished the power supply of said operational amplifier and move back lotus root; The characteristic impedance of said amplifier output current limiting resistance and transmission cable is complementary.
2. all-digital programmable rapid large-current pulse array drive circuit according to claim 1; It is characterized in that said pulse current generating circuit is the N road, after the said pulse current generating circuit in N road is incited somebody to action pulse current process Power Conversion and compensation separately; Through said big electric current common mode filtering inductance; Be delivered to the said power expansion keyset circuit of laser diode one side respectively by said connector independently, wherein, N is a positive integer.
3. all-digital programmable rapid large-current pulse array drive circuit according to claim 1; It is characterized in that; Said power expansion keyset circuit is the N road; The pulse current that each connector passes over is behind the said big electric current common mode filtering inductance through passage separately, and tandem is to EXT P end and EXT N end respectively, and the output pulses after synthesizing outputs to the load wiring end from sub-OUTP of power take-off and OUTN.
4. all-digital programmable rapid large-current pulse array drive circuit according to claim 1 is characterized in that, the electric current on the said pulse damped resistor is 2-5mA; The value of the said first differential mode filter capacitor, the said second differential mode filter capacitor, the said first common mode filtering electric capacity, the said second common mode filtering electric capacity, said the 3rd common mode filtering electric capacity and said the 4th common mode filtering electric capacity is 100pF-2200pF.
5. all-digital programmable rapid large-current pulse array drive circuit according to claim 1 is characterized in that, the value of said building-out capacitor is 1000pF-0.1 μ F; The value of said compensating resistance is 220 Ω-3600 Ω; The noninductive sample resistance of said pulse current is high-power low temperature drift noninductive resistance, and fin is installed, and the value of the noninductive sample resistance of said pulse current need guarantee that peak value detects voltage less than 300mV; Said pulse edge building-out capacitor is high-quality patch capacitor, and takes the structure of a plurality of parallel connections; The magnitude of voltage of the said first two-way TVS, the said second two-way TVS is higher than pulse voltage amplitude.
6. all-digital programmable rapid large-current pulse array drive circuit according to claim 1; It is characterized in that said first gain resistor, said second gain resistor, said first input resistance and said second input resistance are precision more than or equal to 1%, temperature is floated the Chip-R less than 200ppm; Said operational amplifier is the high speed amplifier, and common-mode rejection ratio is greater than 100dB.
7. a control method that is used for the described all-digital programmable rapid large-current pulse array drive circuit of claim 1 is characterized in that, said method comprising the steps of:
(1) main control chip FPGA produces the TTL signal; Between high period; The conducting of high side N-channel MOS FET pipe, the pulse voltage of formation and VDR constant amplitude, said pulse voltage forms pulse current in the closed-loop path; The electric charge that power tube moves back in the lotus root electric capacity is managed through said high side N-channel MOS FET, flows into back level element and load;
(2) damping resistance weakens fast-pulse along the ringing pulse that causes; The first two-way TVS suppressor pulse amplitude; Stop pulse energy to the late-class circuit transmission; The pi type filter of effective impulse electric current through constituting by the first differential mode filter capacitor, the first common mode filtering electric capacity, the second common mode filtering electric capacity, the 3rd common mode filtering electric capacity, the 4th common mode filtering electric capacity, the second differential mode filter capacitor, big electric current common mode filtering inductance, and stop electromagnetism spike that the quick conducting of said high side N-channel MOS FET causes and the electromagnetic interference in the level cable induced environment of back to get into the pulse current combiner circuit;
(3) the pulse current connector ingoing power expansion keyset circuit of flowing through; The said first two-way TVS suppresses too high pulse current amplitude; Pulse current passes the effective impulse electric current to load behind said big electric current common mode filtering inductance, said the 3rd common mode filtering electric capacity, said the 4th common mode filtering electric capacity, the said second differential mode filter capacitor, said damping resistance, building-out capacitor, compensating resistance, the noninductive sample resistance of pulse current, pulse edge building-out capacitor and the second two-way TVS;
(4) said effective impulse electric current after the pulse current signal detection circuit is handled, is accomplished the sampling and the control of pulse current amplitude forming positive sample of signal end PS near load one side, forming negative sample of signal end NS away from load end by governor circuit;
(5) after the width of pulse current reaches the setting width; Said TTL signal is between low period; Said high side N-channel MOS FET pipe ends, and downside N-channel MOS FET manages conducting, and pulse current is flowed into by the source electrode of said downside N-channel MOS FET pipe; Flow out from drain electrode, remaining pulse current is released.
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| US10574026B2 (en) * | 2017-03-23 | 2020-02-25 | Infineon Technologies Ag | Circuit and method for driving a laser diode |
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| JP4732243B2 (en) * | 2006-05-31 | 2011-07-27 | パナソニック株式会社 | Laser drive circuit, optical pickup and recording / reproducing apparatus |
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