CN103853078A - Integrated circuit of terminal resistance in programmable logic chip in-out circuit wafer - Google Patents
Integrated circuit of terminal resistance in programmable logic chip in-out circuit wafer Download PDFInfo
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- CN103853078A CN103853078A CN201210510302.4A CN201210510302A CN103853078A CN 103853078 A CN103853078 A CN 103853078A CN 201210510302 A CN201210510302 A CN 201210510302A CN 103853078 A CN103853078 A CN 103853078A
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Abstract
The invention provides an integrated circuit of terminal resistance in a programmable logic chip in-out circuit wafer. The integrated circuit is connected with a chip external circuit which comprises a first pin and a second pin; the integrated circuit comprises a signal selection circuit, a first resistor, a second resistor, a first single-ended input amplifier, a second single-ended input amplifier and a differential input amplifier; the input end of the signal selection circuit receives a selection signal and the output end of the signal selection circuit is connected with one end of the first resistor and one end of the second resistor; the input end of the first single-ended input amplifier is respectively connected with the other end of the first pin and the other end of the first resistor; the input end of the second single-ended input amplifier is respectively connected with the other end of the second pin and the other end of the second resistor; the positive input end of the differential input amplifier is connected with the other end of the first resistor and the negative input end of the differential input amplifier is connected with the other end of the second resistor. The integrated circuit can reduce on-chip resistance, reduce cost and improve chip performance.
Description
Technical field
The present invention relates to digital circuit technique field, especially relate to FPGA technical field, specifically the integrated circuit of terminal resistance in a kind of programmable logic chip imput output circuit sheet.
Background technology
Along with the raising of digital circuit clock speed, signal integrity (SI) has become the problem of being more and more concerned about.In the time that signal in circuit can arrive load IC with the sequential, duration and the voltage amplitude that require, this circuit just has good signal integrity.In the time that signal can not normal response, just there is problems of Signal Integrity.For example, false triggering, damped oscillation, overshoot, owe the problems of Signal Integrity such as punching and can cause clock interrupted oscillation and data to make mistakes.Wire on actual pcb board has the electrical specifications such as resistance, electric capacity and inductance, and the output impedance of driver is less than the characteristic impedance of the interconnected signal wire of PCB conventionally, and in general the characteristic impedance of the interconnected signal wire of PCB is also less than the input impedance of receiver.The uncontinuity of this impedance will cause the appearance of signal reflex in design system.In High-speed Digital Circuit Design, the electric capacity on pcb board circuit and inductance can make wire be equivalent to a transmission lines.Impedance meeting on transmission line makes signal not reach the voltage amplitude of regulation, and line impedance is not mated and can be produced signal reflection phenomenon with external load, and these all can cause problems of Signal Integrity.
In general the common method that reduces problems of Signal Integrity is on transmission line, to increase termination components.Termination components is some passive elements, as resistance and electric capacity.Thereby terminal Matching Technology is utilized exactly these elements between transmission line and load, to realize impedance matching and is prevented signal integrity (SI) problem.Resistance can be used for the impedance of matched transmission line impedance and receiver, weakens the energy of antihunt signal thereby electric capacity can be used for the variation of deboost.Modal passive termination matching technique comprises the terminal Matching Technology, Dai Weinan terminal Matching Technology of parallel join, terminal Matching Technology and AC terminal Matching Technology etc. connected in series.Therefore, a lot of IO standards, especially new transmission standard has all stipulated the method for terminal build-out resistor.
An important feature of the I/O of FPGA can be supported unlike signal standard by option and installment mode exactly.In order to reduce resistance shared area on PCB, further improve signal integrity, fpga chip is integrated these resistance, are called terminal resistance in sheet.
List of references (High-Speed Board Layout Guidelines, Altera Corp., Pub.SII52012-1.4) has been listed the standard mode that the several frequently seen terminal resistance that is used in input end uses.Be illustrated in figure 1 a kind of circuit diagram of simple single-ended input parallel terminal resistance, Figure 2 shows that the circuit diagram of Dai Weinan (Thevenin) parallel terminal resistance, Figure 3 shows that the initiatively circuit diagram of (Active) parallel terminal resistance, Figure 4 shows that the circuit diagram of series connection RC parallel terminal resistance, Figure 5 shows that the circuit diagram of difference entry terminal resistance (LVDS/LVPECL), Figure 6 shows that the circuit diagram of difference entry terminal resistance (PCML).
In order to reduce resistance shared area on PCB, further improve signal integrity, user friendly PCB design, a lot of chips start integrated these resistance, become terminal resistance in sheet.Because the input and output able to programme of fpga chip can be supported multiple standards, many than general chip complexity that this makes that integrated these resistance become.Figure 7 shows that the patent No. number is US6, a kind of terminal resistance scheme that 924,659 the U.S. provides.But in order to meet difference entry terminal resistance and single-ended entry terminal resistance simultaneously, it is very complicated that the whole resistor network shown in Fig. 7 becomes.
In summary, the interior terminal resistance that prior art provides takies too much chip area, thereby has increased chip cost.Meanwhile, too much resistance can make the electric capacity of pin increase, thereby signal speed is lowered.
Therefore, how can propose a kind of number that can either reduce resistance on sheet to reduce chip cost, can reduce again the integrated circuit of the terminal resistance of pin electric capacity raising chip performance, become the problem of needing in the industry solution badly.
Summary of the invention
In view of the defect of prior art, the invention provides the integrated circuit of terminal resistance in a kind of programmable logic chip imput output circuit sheet.
Described integrated circuit is connected with off-chip circuitry, and wherein said off-chip circuitry comprises the first pin and the second pin;
Described integrated circuit comprises: signal selecting circuit, the first resistance, the second resistance, the first single-ended input amplifier, the second single-ended input amplifier, difference input amplifier;
Wherein, the input end of described signal selecting circuit receives one and selects signal, and the output terminal of described signal selecting circuit is all connected with one end of described the first resistance, one end of described the second resistance;
The input end of described the first single-ended input amplifier is connected with the other end of described the first pin, described the first resistance respectively;
The input end of described the second single-ended input amplifier is connected with the other end of described the second pin, described the second resistance respectively;
The positive input terminal of described difference input amplifier is connected with the other end of described the first resistance;
The negative input end of described difference input amplifier is connected with the other end of described the second resistance.
Preferably, described signal selecting circuit is multiselect one on-off circuit.
Preferably, described signal selecting circuit is to comprise four to select four of port to select an on-off circuit;
Select port to be respectively for described four:
The first port, is connected in bus termination voltage VTT;
The second port, is connected in a high resistant;
The 3rd port, ground connection;
The 4th port, is connected in an electric capacity;
Described signal selecting circuit, according to received described selection signal, is connected described four of selecting in port.
Beneficial effect of the present invention is: technical solution of the present invention will facilitate FPGA user's PCB design.Reduce resistance shared area on PCB, further improved signal integrity.And to chip design Shi Eryan, the technology of the present invention has reduced the number of resistance on sheet, thereby reduce chip cost; Meanwhile, also can reduce pin electric capacity, improve chip performance.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those skilled in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the circuit diagram of existing a kind of simple single-ended input parallel terminal resistance;
Fig. 2 is the circuit diagram of existing Dai Weinan (Thevenin) parallel terminal resistance;
Fig. 3 is the circuit diagram of existing active (Active) parallel terminal resistance;
Fig. 4 is the circuit diagram of existing series connection RC parallel terminal resistance;
Fig. 5 is the circuit diagram of existing difference entry terminal resistance (LVDS/LVPECL);
Fig. 6 is the circuit diagram of existing difference entry terminal resistance (PCML);
Fig. 7 is the circuit diagram of existing a kind of terminal resistance;
Fig. 8 is a kind of integrated circuit of interior terminal resistance;
The integrated circuit of terminal resistance in the programmable logic chip imput output circuit sheet that Fig. 9 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Based on the embodiment in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Consider the deficiencies in the prior art, Fig. 8 provides a kind of integrated circuit of interior terminal resistance.Fig. 8 has shown that the terminal resistance of part from Fig. 1 to Fig. 6 is integrated into the situation of two input and output (D1, D2 in Fig. 8, D3, D4, D5, the D6 circuit diagram shown in presentation graphs 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 respectively).The object that we will reach is the standard that each pin can be supported various single-ended terminal resistances; And in the time that two pins are inputted as difference together, can support various differential termination resistance standards.Fig. 8 has illustrated, if realize this target, not only needs a lot of resistance, also needs resistance to be linked to the switch of pin line.Because those skilled in the art all know, simply all resistance is joined up, due to connection in series-parallel effect, resistance value can change, and can not reach the effect of coupling.What so, whole circuit can become is very complicated, huge.
Based on above-mentioned consideration, the embodiment of the present invention is intended to propose a kind of number that can either reduce resistance on sheet to reduce chip cost, can reduce again the integrated circuit of the terminal resistance of pin electric capacity raising chip performance.
As shown in Figure 9, the integrated circuit in chip is connected with off-chip circuitry, and wherein said off-chip circuitry comprises the first pin A and the second pin B;
Integrated circuit comprises: signal selecting circuit W, the first resistance R 1, the second resistance R 2, the first single-ended input amplifier Q1, the second single-ended input amplifier L1 and difference input amplifier T;
In specific implementation, the resistance of resistance R 1, resistance R 2 does not limit, and those skilled in the art can arrange according to actual needs.
Wherein, the input end S1 of described signal selecting circuit W receives one and selects signal, and the output terminal S2 of described signal selecting circuit is all connected with one end M of one end M of described the first resistance, described the second resistance;
The input end Q1 of the first single-ended input amplifier Q is connected with the first pin A of off-chip circuitry, the other end N of the first resistance R 1 respectively;
The input end L1 of the second single-ended input amplifier L is connected with the second pin B outside chip, the other end P of the second resistance R 2 respectively;
The positive input terminal T1 of difference input amplifier T is connected with the other end N of the first resistance R 1, and the negative input end T2 of difference input amplifier T is connected with the other end P of the second resistance R 2.
As shown in Figure 9, described signal selecting circuit W is multiselect one on-off circuit, and particularly, described signal selecting circuit is to comprise four to select four of port to select an on-off circuit.Select port to be respectively for four: the first port " 0 ", is connected in bus termination voltage VTT; The second port " 1 ", is connected in a high resistant; The 3rd port " 2 ", ground connection; The 4th port " 3 ", is connected in a capacitor C; Signal selecting circuit W, according to received described selection signal, connects described four of selecting in port.So, can realize and substitute the multiple circuit diagram that prior art provides with circuit provided by the present invention.
Particularly, in the time that signal selecting circuit W " 0 " port is connected, the in the situation that of single-ended input, (the pin A from chip or pin B input signal), can realize active parallel terminal resistance as shown in Figure 3;
In the time that signal selecting circuit W " 0 " port is connected, in the situation that difference is inputted, (the pin A from chip and pin B be input differential signal simultaneously), can realize difference entry terminal resistance (PCML) as shown in Figure 6;
In the time that signal selecting circuit W " 1 " port is connected, the in the situation that of single-ended input, (the pin A from chip or pin B input signal), can realize endless resistance;
In the time that signal selecting circuit W " 1 " port is connected, in the situation that difference is inputted, (the pin A from chip and pin B be input differential signal simultaneously), can realize difference entry terminal resistance (LVDS/LVPECL) as shown in Figure 5;
In the time that signal selecting circuit W " 2 " port is connected, the in the situation that of single-ended input, (the pin A from chip or pin B input signal), can realize simple single-ended parallel terminal resistance as shown in Figure 1;
In the time that signal selecting circuit W " 2 " port is connected, in the situation that difference is inputted, (the pin A from chip and pin B be input differential signal simultaneously), can realize difference entry terminal resistance;
In the time that signal selecting circuit W " 3 " port is connected, the in the situation that of single-ended input (the pin A from chip or pin B input signal), can realize series connection RC parallel terminal resistance as shown in Figure 4;
In the time that signal selecting circuit W " 3 " port is connected, in the situation that difference is inputted, (the pin A from chip and pin B be input differential signal simultaneously), can realize difference entry terminal resistance (LVDS/LVPECL mutation).
It should be noted that, those skilled in the art are after having understood the circuit diagram shown in technology contents and Fig. 9 of this area, the problem that technical scheme provided by the invention can solve prior art can be known, and the circuit of the various terminal resistances shown in existing Fig. 1 to Fig. 6 can be substituted with circuit provided by the present invention.
Beneficial effect of the present invention is: technical solution of the present invention will facilitate FPGA user's PCB design.Reduce resistance shared area on PCB, further improved signal integrity.And to chip design Shi Eryan, the technology of the present invention has reduced the number of resistance on sheet, thereby reduce chip cost; Meanwhile, also can reduce pin electric capacity, improve chip performance.
In the present invention, applied specific embodiment principle of the present invention and embodiment are set forth, the explanation of above embodiment is just for helping to understand method of the present invention and core concept thereof; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (3)
1. an integrated circuit for terminal resistance in programmable logic chip imput output circuit sheet, is characterized in that, described integrated circuit is connected with off-chip circuitry, and wherein said off-chip circuitry comprises the first pin and the second pin;
Described integrated circuit comprises: signal selecting circuit, the first resistance, the second resistance, the first single-ended input amplifier, the second single-ended input amplifier, difference input amplifier;
Wherein, the input end of described signal selecting circuit receives one and selects signal, and the output terminal of described signal selecting circuit is all connected with one end of described the first resistance, one end of described the second resistance;
The input end of described the first single-ended input amplifier is connected with the other end of described the first pin, described the first resistance respectively;
The input end of described the second single-ended input amplifier is connected with the other end of described the second pin, described the second resistance respectively;
The positive input terminal of described difference input amplifier is connected with the other end of described the first resistance;
The negative input end of described difference input amplifier is connected with the other end of described the second resistance.
2. the integrated circuit of terminal resistance in programmable logic chip imput output circuit sheet as claimed in claim 1, is characterized in that, described signal selecting circuit is multiselect one on-off circuit.
3. the integrated circuit of terminal resistance in programmable logic chip imput output circuit sheet as claimed in claim 2, is characterized in that, described signal selecting circuit is to comprise four to select four of port to select an on-off circuit;
Select port to be respectively for described four:
The first port, is connected in bus termination voltage VTT;
The second port, is connected in a high resistant;
The 3rd port, ground connection;
The 4th port, is connected in an electric capacity;
Described signal selecting circuit, according to received described selection signal, is connected described four of selecting in port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210510302.4A CN103853078A (en) | 2012-12-03 | 2012-12-03 | Integrated circuit of terminal resistance in programmable logic chip in-out circuit wafer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210510302.4A CN103853078A (en) | 2012-12-03 | 2012-12-03 | Integrated circuit of terminal resistance in programmable logic chip in-out circuit wafer |
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| CN103853078A true CN103853078A (en) | 2014-06-11 |
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| CN201210510302.4A Pending CN103853078A (en) | 2012-12-03 | 2012-12-03 | Integrated circuit of terminal resistance in programmable logic chip in-out circuit wafer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105846800A (en) * | 2016-03-21 | 2016-08-10 | 深圳市紫光同创电子有限公司 | FPGA chip and terminating resistor multiplexing method thereof, and terminating resistor multiplexing circuit thereof |
| CN112731828A (en) * | 2020-12-09 | 2021-04-30 | 深圳市紫光同创电子有限公司 | Terminal resistor circuit, chip and chip communication device |
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| WO2010014802A1 (en) * | 2008-07-30 | 2010-02-04 | Qualcomm Incorporated | Driver amplifier having a programmable output impedance adjustment circuit |
| CN101908714A (en) * | 2010-07-23 | 2010-12-08 | 天津市鼎曦光学科技有限公司 | All-digital programmable rapid large-current pulse array drive circuit and control method thereof |
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| CN1511315A (en) * | 2001-05-25 | 2004-07-07 | �����ɷ� | Write output driver with internal programmable pull-up resistors |
| US6720805B1 (en) * | 2003-04-28 | 2004-04-13 | National Semiconductor Corporation | Output load resistor biased LVDS output driver |
| CN1953331A (en) * | 2005-10-18 | 2007-04-25 | Nec液晶技术株式会社 | Interface idle pin processing method and interface device using same |
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| CN105846800A (en) * | 2016-03-21 | 2016-08-10 | 深圳市紫光同创电子有限公司 | FPGA chip and terminating resistor multiplexing method thereof, and terminating resistor multiplexing circuit thereof |
| CN112731828A (en) * | 2020-12-09 | 2021-04-30 | 深圳市紫光同创电子有限公司 | Terminal resistor circuit, chip and chip communication device |
| WO2022121134A1 (en) * | 2020-12-09 | 2022-06-16 | 深圳市紫光同创电子有限公司 | Terminal resistance circuit, chip, and chip communication apparatus |
| US11909388B2 (en) | 2020-12-09 | 2024-02-20 | Shenzhen Pango Microsystems Co., Ltd | Terminal resistance circuit, chip and chip communication device |
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