CN101894008A - Interrupt enabling and disabling device and method - Google Patents
Interrupt enabling and disabling device and method Download PDFInfo
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Abstract
The invention provides an interrupt enabling and disabling device and a method thereof. Concretely, the device comprises an interrupt shielding register, a virtual register which has digits in one-to-one correspondence with those of the interrupt shielding register and comprises an interrupt disabling register in charge of write operation on each digit thereof, an interrupt enabling register in charge of write operation on each digit thereof as well as a register converter which sets the state of the digit corresponding to the digit in the interrupt shielding register according to the state of the digit indicating interrupt shielding in the interrupt disabling interrupt and sets the state of the digit corresponding to the digit in the interrupt shielding register according to the state of the digit indicating interrupt enabling in the interrupt enabling register. The invention is used for improving work efficiency of operating system.
Description
Technical field
The present invention relates to the interrupt control technique field, particularly relate to a kind of apparatus and method of switch interrupts.
Background technology
Usually have interrupt mask register (IMR, Interrupt Mask Register) in the interruptable controller of SOC (system on a chip) (SOC, System on Chip) chip, it is an eight bit register normally, is used for being provided with the mask information of interrupt request.When among the IMR during i position conductively-closed (mask) (the Bit value of i position is 1 among the IMR), forbid IR
iThe interrupt request singal that (Interrupt Request i) pin sends makes it and can not interrupt to the CPU application by interruptable controller, wherein, and IR
iLink to each other with interrupt source, be used to produce interrupt request singal, i=0～7; Otherwise when i position among the IMR during by opening (unmask) (the Bit value of i position is 0 among the IMR), the interrupt request singal that then allows the IRi pin to send makes it to interrupt to the CPU application by interruptable controller.
The i position is being shielded or during open operation,, needing read the value of IMR earlier in order not influence other position among the IMR.Fig. 1 shows the example of a kind of IMR register of prior art, if want the 4th Bit value is put 1, just need read original value, and then write a value, obtains result shown in Figure 2.
Therefore, in shielding or open process of interrupting, need twice IMR register of operation, write-after-read still, in the process of the operating system of reality, interrupts all might taking place at any time, promptly interrupt inserting in every instruction, and read-write is two instructions.Therefore these two instructions are probably carried out in different threads, and different threads might carry out different Interrupt Process, different Interrupt Process is being read the IMR register and is writing the value of IMR register probably different, thereby causes different Interrupt Process to produce each other in to the IMR operation registers easily disturbing.
At said circumstances, traditional way is at present, guarantees that the read-write of IMR register is an atomic operation; also promptly in this process, can not be switched by other threads; but atomic operation can bring the loaded down with trivial details problem of read-write protection, and then reduces the work efficiency of operating system.
In a word, need the urgent technical matters that solves of those skilled in the art to be exactly: the work efficiency that how can improve operating system.
Summary of the invention
Technical matters to be solved by this invention provides a kind of apparatus and method of switch interrupts, in order to improve the work efficiency of operating system.
In order to address the above problem, the invention discloses a kind of device of switch interrupts, comprising:
Interrupt mask register;
Figure place and described interrupt mask register be virtual register one to one, comprising:
Close to interrupt register, accept its each write operation; And
Drive interrupt register, accept its each write operation;
The register converter according to closing the state that interrupts the position that the expression shielding is interrupted in the register, is provided with the state of this pairing position in interrupt mask register; And, according to the state of opening the open position of interrupting of expression in the interrupt register, the state of this pairing position in interrupt mask register is set.
On the other hand, the invention also discloses a kind of method of switch interrupts, comprising:
Set up figure place and interrupt mask register virtual register one to one, wherein, described virtual register comprises and close to interrupt register and drive interrupt register, and described pass interrupts register, drive interrupt register accepts its each write operation;
According to closing the state that interrupts the position of expression shielding interrupt request in the register, the state of this pairing position in described interrupt mask register is set;
According to the state of opening the position of expression shielding interrupt request in the interrupt register, the state of this pairing position in described interrupt mask register is set;
The switch that interrupts according to the State Control of the position of interrupt mask register.
Compared with prior art, the present invention has the following advantages:
The present invention adopts virtual register, this virtual register comprises pass interruption register and drives interrupt register, wherein, described pass is interrupted the register register and is used to accept to its each write operation, and open register is used to accept to its each write operation; And the register converter can be automatically at " 1 " position of described virtual register, in the interrupt mask register with should operate corresponding position, " 1 " position; Like this, for operating systems such as MCU or CPU, in the time of closing certain interruption, only need described pass is interrupted the position execution write operation corresponding to this interruption of register, when opening certain interruption, only need write operation is carried out in described position corresponding to this interruption of driving interrupt register; And operate a register is atomic operation, promptly writes in the process of a register and can not interrupted, and so just can avoid the frequent read-write protection of operating system.
Description of drawings
Fig. 1 is the example of a kind of IMR register of prior art;
Fig. 2 puts example as a result after 1 to Bit4 among Fig. 1;
Fig. 3 is the structural drawing of device one embodiment of a kind of switch interrupts of the present invention;
Fig. 4 is a kind of application example of the present invention in the MCU controller;
Fig. 5 is the structural drawing of another embodiment of device of a kind of switch interrupts of the present invention;
Fig. 6 is the process flow diagram of the method embodiment of a kind of switch interrupts of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
One of core idea of the present invention is, under the prerequisite of original interrupt mask register storage mask information, adopts the operating system of virtual register chip for driving; Particularly, for guaranteeing the uniqueness of interrupt mask register intermediate value, the device of switch interrupts of the present invention adopts two virtual registers, comprises closing interrupting register and driving interrupt register.Wherein, close to interrupt register and accept, drive interrupt register and accept its each write operation to its each write operation.Like this, desire to close the interruption of interrupt mask register i position, the corresponding positions that only needs described pass to be interrupted register writes " 1 "; The interruption of the open interrupt mask register i of desire position only needs the described corresponding positions of driving interrupt register is write " 1 "; So, the shielding of interruption or open only the need are carried out a register write operation, thereby can avoid CPU or the MCU frequent read-write protections of operating system such as (single-chip microcomputer, Single Chip Microcomputer).
Fig. 3 shows the structural drawing of the device embodiment 1 of a kind of switch interrupts of the present invention.The device of switch interrupts is used for shielding or open interrupt request, specifically can comprise:
An operating system just has n interrupt request trigger if there is the n level to interrupt in CPU, be generically and collectively referred to as interrupt request register; Corresponding with it have a n interrupt mask flip-flop, is generically and collectively referred to as interrupt mask register, and wherein, n is a natural number.
Described enabling interrupted mainly can comprising shielding or opened interruption; For example, when shielding is interrupted,, can not respond this signal even interrupt request register sends look-at-me yet; And when open the interruption, can interrupt to the CPU application according to this look-at-me.
Figure place and described interrupt mask register 301 be virtual register 302 one to one, and virtual register 302 specifically can comprise:
Close to interrupt register 321,, accept request that this shielding is interrupted and closing the write operation of interrupting corresponding of institute in the register 321 according to the request that a certain shielding is interrupted;
Drive interrupt register 322,, accept this is opened the write operation of corresponding of request institute in driving interrupt register 322 of interruption according to a certain open request of interrupting;
Register converter 303 is used for according to the state that closes the position of interrupting register 321 expression shielding interruptions the state of this pairing position in interrupt mask register 301 being set; And, according to the state of opening the open position of interrupting of expression in the interrupt register 322, the state of this pairing position in interrupt mask register 301 is set.
The present invention can be applied in the various chips such as SOC, in order to improve the work efficiency of operating system; Wherein, the position of described virtual register 302 is corresponding one by one with the position of described interrupt mask register 301, all represents a certain interrupt source.
For example, value is the position of binary code " 1 " in the pass interruption register 321, promptly closes " 1 " position of interrupting register 321, represents to open a certain interrupt request of this interrupt source, also promptly closes and interrupts; Open that value is the position of binary code " 1 " in the interrupt register 322, promptly open " 1 " position of interrupt register 322, the interrupt request of open this interrupt source of expression is also promptly opened interruption; And value is the position of binary code " 0 " in the interrupt mask register 301, it is " 0 " position of interrupt mask register 301, the interrupt request of open this interrupt source of expression, also promptly open interruption, value is " 1 " position in the interrupt mask register 301, be " 1 " position of interrupt mask register 301, the interrupt request of this interrupt source of expression shielding is also promptly closed and is interrupted.
That is to say, register converter 303 closes pairing position in interrupt mask register 301, " 1 " position of interrupting register 321 and is set to " 1 ", and pairing position in interrupt mask register 301, " 1 " position of driving interrupt register 322 is set to " 0 " with reference to Fig. 4, in a kind of application example of the present invention, after the MCU of chip controller powers on, can be described interrupt mask register 301 and virtual register 302 distribution address spaces (operating system is only operated at described virtual register 302), for example, the address of described interrupt mask register 301 is 0x60002000, the address that register 321 is interrupted in described pass is 0x60002000, and the described interrupt register 322 of opening is 0x60002004; Like this, the MCU controller can be according to closing interruption or opening the demand of interruption, to writing or read operation with the corresponding bit address execution of described demand in the described virtual register 302.
Just operate with the corresponding position, " 1 " position of driving interrupt register 322 at interrupting register 321 with described pass in the interrupt mask register 301 " 0 " position that register converter 303 is ignored described pass interruption register 321 and driven interrupt register 322.
In specific implementation, can realize the function of register converter 303 by trigger, at this moment, described register converter 303 specifically can comprise:
The first trigger A1 specifically can comprise:
First input end A11, it connects the position that register 321 is interrupted in described pass;
First output terminals A 12, it links to each other with the position of described interrupt mask register 301, is used for when described first input end A11 becomes high level by low level the output high level;
The second trigger A2 specifically can comprise:
The second input end A21, it connects described position of driving interrupt register 322;
Second output terminals A 22, it links to each other with the position of described interrupt mask register 301, is used for when the described second input end A21 becomes high level by low level output low level;
Nulling circuit A3 is used at described first output terminals A 12 output high level, perhaps, and during described second output terminals A, 22 output low levels, with the described first input end A11 and the second input end A21 zero setting.
Be well known that because digital circuit is only opened (" 1 ") and (" 0 ") two states of closing, and factors such as voltage of opening and power supply have relation, so, be referred to as high level, on the contrary low level, wherein, voltage can be with respect to certain reference point (for example, potential difference (PD) of 0～0.5V).Also promptly, output low level of the present invention is equal to " 0 " position state, and the output high level is equal to " 1 " position state.
Because interrupt mask register 301 is corresponding one by one with the position of closing interruption register 321, so, the position that the position that described first input end A11 is connected is connected with first output terminals A 12 also has one-to-one relationship, for example, described first input end A11 connects and closes the i position of interrupting register 321, and then described first output terminals A 12 also links to each other with the i position of interrupt mask register 301; In like manner, the described second input end A21 connected the position also be connected with second output terminals A 22 the position also be one to one.
Described two triggers are in the rising edge (↑) of input end arrives separately, and its output terminal carries out the upset or the maintenance of level state.
For guaranteeing the operate as normal of described two triggers, at described first output terminals A, 12 output high level, perhaps, during described second output terminals A, 22 output low levels, described nulling circuit A3 can be with its input end zero setting separately; In practice, the input end of described nulling circuit A3 can connect first output terminals A 12 and second output terminals A 22, and output terminal then links to each other with the second input end A21 with first input end A11.
For example, at clock period T, the MCU controller interrupts the 1st of register 321 to described pass and writes " 1 ", also be, the rising edge of first input end A11 arrives, first output terminals A 12 is delivered to interrupt mask register 301 with high level, and then, nulling circuit A3 is with the first input end A11 and the second input end A21 zero setting;
At clock period T+2, the MCU controller writes " 1 " to described the 1st of driving interrupt register 322, also be, the rising edge of the second input end A21 arrives, second output terminals A 22 is delivered to interrupt mask register 301 with low level, then, nulling circuit A3 is with the first input end A11 and the second input end A21 zero setting; Wherein, described T is a natural number.
For MCU or CPU, close certain when interrupting, only need to carry out write operation to closing the position corresponding to this interruption of interrupting register 321, in the time of opening certain and interrupt, only need split the position corresponding to this interruption of interrupt register 322 and carry out write operation; And operate a register is atomic operation, and promptly the write operation process of a register can not interrupted, and so just can avoid the frequent read-write protection of operating system.
Fig. 5 shows the structural drawing of another embodiment of device of a kind of switch interrupts of the present invention, specifically can comprise:
Figure place and described interrupt mask register 501 be virtual register 502 one to one, and this virtual register 502 specifically can comprise:
Close to interrupt register 521,, accept the write operation of corresponding of request institute in mask register 521 that this shielding is interrupted according to the request that a certain shielding is interrupted;
Drive interrupt register 522,, accept write operation this open request of interrupting corresponding of institute in open register 522 according to a certain open request of interrupting;
In the present embodiment, described status register 523 can provide the user each current state; For example, the MCU controller is that described status register 323 addresses distributed are 0x60002008 among Fig. 4, by visiting the value of these address read status register 523 a certain positions, can know that promptly this position is in out interruption status and still closes the interruption state.
Each current state of described status register 523 can be used as to write closes the foundation of interrupting register 521 and/or driving interrupt register 522, but, regardless of the current state of status register 523, the user can be interrupted register 521 and open interrupt register 522 execution write operations closing; Also promptly, those skilled in the art can carry out above-mentioned write operation in any clock period, perhaps, know the current state of described corresponding positions in clock period arbitrarily, and the present invention is not limited this.
The described interrupt mask register 501 of present embodiment, close to interrupt register 521, open interrupt register 522 and register converter 503 with interrupt mask register 301 shown in Figure 3, close that interruption register 321 is opened, interrupt register 322 and register converter 303 be similar, relevant part can be with reference to aforementioned explanation to Fig. 3.
Embodiment is corresponding with aforementioned means, the invention also discloses a kind of method embodiment of switch interrupts, with reference to Fig. 6, specifically can comprise step 601～step 603.
Step 601, set up figure place and interrupt mask register virtual register one to one, wherein, described virtual register can comprise and close to interrupt register, drive interrupt register, and described pass interrupts register, drive interrupt register can accept its each write operation;
In practice, described virtual register can directly be accepted operating systems such as MCU controller, cpu controller to its each write operation.
Step 602, according to the state that close to interrupt the position of expression shielding interrupt request in the register, the state of this pairing position in described interrupt mask register is set.
For instance, value is the position of " 1 " in the pass interruption register, and promptly state is the position of " 1 ", a certain interrupt request of expression shielding interrupt source.Similarly, value is " 1 " position in the interrupt mask register 301, i.e. " 1 " of interrupt mask register 301 position, and the interrupt request of this interrupt source of expression shielding is also promptly closed and is interrupted.So, the value of interrupting register with described pass in the just described interrupt mask register of step 602 is that corresponding position, binary code " 1 " position is set to " 1 ".
In practice, can utilize trigger to realize the function of this step, for example, the first input end of first trigger connects the position of described mask register, and first output terminal links to each other with the corresponding positions of described interrupt mask register; In rising edge (↑) arrival of its first input end, its first output terminal carries out the upset or the maintenance of level state;
Correspondingly, the implementation of this step can for, when the position of interrupting register in described pass becomes high level by low level, corresponding position output high level in described interrupt mask register; And, when high level is exported in corresponding position in described interrupt mask register, register and the corresponding positions zero setting of opening in the interrupt register are interrupted in described pass.
Step 603, basis are opened the state of the position of expression shielding interrupt request in the interrupt register, and the state of this pairing position in described interrupt mask register is set.
For instance, open the position for " 1 " of value in the interrupt register, promptly state be the position of " 1 ", represents to shield a certain interrupt request of interrupt source.And value is " 0 " position in the interrupt mask register, i.e. " 0 " of interrupt mask register position, and the interrupt request of open this interrupt source of expression is also promptly opened interruption.So, be that corresponding position, binary code " 1 " position is set to " 0 " with the described value of driving interrupt register in the just described interrupt mask register of step 603.
In like manner, can utilize the trigger principle to realize this step: when becoming high level by low level in described position of driving interrupt register, corresponding position output low level in described interrupt mask register; And, when corresponding position output low level in described interrupt mask register, register and the corresponding positions zero setting of opening in the interrupt register are interrupted in described pass.
The purpose of zero-setting operation described in the present invention is the validity that guarantees rising edge (low level becomes high level).For example, at clock period T, controller interrupts the 1st of register to described pass and writes " 1 ", and also, the rising edge of first input end arrives, and first output terminal is delivered to interrupt mask register with high level, then, and with the first input end and the second input end zero setting;
At clock period T+2, controller writes " 1 " to described the 1st of driving interrupt register, also is, when the rising edge of the 1st in open register arrives, low level is delivered to interrupt mask register, then, with the 1st position zero of first input end and open register; Wherein, described T is a natural number.
In another embodiment of the invention, can also provide each current state, at this moment, described virtual register can also comprise: status register, accept its each read operation;
Described method can also comprise:
Step 604, the position information of described interrupt mask register is sent into described status register;
Step 605, the switch that interrupts according to the State Control of the position of interrupt mask register.
The a certain interrupt source of a certain position representative of interrupt mask register.The interrupt request of the interrupt source of open this correspondence can be represented in a certain " 0 " of interrupt mask register position, also promptly opens interruption; The interrupt request of the interrupt source of this correspondence can be represented to shield in a certain " 1 " of interrupt mask register position, also promptly closes and interrupts.So, promptly can control the switch of interruption according to the state of the position of interrupt mask register.
Need to prove, those skilled in the art can be according to actual needs, register is interrupted in described pass or open interrupt register execution write operation in any clock period, perhaps, read described status register and know each current state of described interrupt mask register in any clock period, perhaps, the switch that interrupts according to the State Control of the position of interrupt mask register in any clock period; Promptly, the present invention is not limited the run time of described step 602, step 603, step 604 and step 605 yet.
For method embodiment, because it is similar substantially to device embodiment shown in Figure 3, so description is fairly simple, relevant part gets final product referring to the part explanation of Fig. 3.
More than to the apparatus and method of a kind of switch interrupts provided by the present invention, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. the device of a switch interrupts is characterized in that, comprising:
Interrupt mask register;
Figure place and described interrupt mask register be virtual register one to one, comprising:
Close to interrupt register, accept its each write operation; And
Drive interrupt register, accept its each write operation;
The register converter according to closing the state that interrupts the position that the expression shielding is interrupted in the register, is provided with the state of this pairing position in interrupt mask register; And, according to the state of opening the open position of interrupting of expression in the interrupt register, the state of this pairing position in interrupt mask register is set.
2. device as claimed in claim 1, it is characterized in that, interrupt with described pass in the described register converter interrupt mask register that value is set to " 1 " for corresponding position, the position of " 1 " in the register, and, open value in the interrupt register and be set to " 0 " with described in the interrupt mask register for corresponding position, the position of " 1 ".
3. device as claimed in claim 2 is characterized in that, described register converter comprises:
First trigger comprises:
First input end, it connects described mask register; And
First output terminal, it links to each other with described interrupt mask register, is used for when described first input end becomes high level by low level the output high level;
Second trigger comprises:
Second input end, it connects described open register; And
Second output terminal, it links to each other with described interrupt mask register, is used for when described second input end becomes high level by low level output low level; And
Nulling circuit is used at described first output terminal output high level, perhaps, and during the described second output terminal output low level, with the described first input end and the second input end zero setting.
4. device as claimed in claim 1 is characterized in that, also comprises:
Status register is accepted its each read operation;
Described register converter is sent the position information of described interrupt mask register into described status register.
5. the method for a switch interrupts is characterized in that, comprising:
Set up figure place and interrupt mask register virtual register one to one, wherein, described virtual register comprises and close to interrupt register and drive interrupt register, and described pass interrupts register, drive interrupt register accepts its each write operation;
According to closing the state that interrupts the position of expression shielding interrupt request in the register, the state of this pairing position in described interrupt mask register is set;
According to the state of opening the position of expression shielding interrupt request in the interrupt register, the state of this pairing position in described interrupt mask register is set;
The switch that interrupts according to the State Control of the position of interrupt mask register.
6. method as claimed in claim 5, it is characterized in that, according to closing the state that interrupts the position of expression shielding interrupt request in the register, the step of this state of pairing position in described interrupt mask register is set, that is, the corresponding position, " 1 " position of interrupting register with described pass in the described interrupt mask register is set to " 1 ".
7. method as claimed in claim 5, it is characterized in that, according to the state of opening the position of expression shielding interrupt request in the interrupt register, the step of this state of pairing position in described interrupt mask register is set, that is, be set to " 0 " with described corresponding position, " 1 " position of driving interrupt register in the described interrupt mask register.
8. method as claimed in claim 6 is characterized in that, interrupts corresponding step that is set to " 1 " in " 1 " position of register in the described interrupt mask register with described pass, comprising:
When the position of described pass interruption register becomes high level by low level, corresponding position output high level in described interrupt mask register;
When high level is exported in corresponding position in described interrupt mask register, register and the corresponding positions zero setting of opening in the interrupt register are interrupted in described pass.
9. method as claimed in claim 7 is characterized in that, is set to the step of " 0 " in the described interrupt mask register with described corresponding position, " 1 " position of driving interrupt register, comprising:
When described position of driving interrupt register becomes high level by low level, corresponding position output low level in described interrupt mask register;
When corresponding position output low level in described interrupt mask register, register and the corresponding positions zero setting of opening in the interrupt register are interrupted in described pass.
10. the method for claim 1 is characterized in that, described virtual register also comprises: status register, accept its each read operation;
Described method also comprises:
The position information of described interrupt mask register is sent into described status register.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103631649A (en) * | 2012-08-24 | 2014-03-12 | 深圳市中兴微电子技术有限公司 | Interrupt processing method and device and interrupt controller |
| CN112181877A (en) * | 2020-10-28 | 2021-01-05 | 瑞芯微电子股份有限公司 | Display frequency conversion method and system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050228923A1 (en) * | 2004-03-30 | 2005-10-13 | Zimmer Vincent J | Efficiently supporting interrupts |
| CN101135997A (en) * | 2006-08-29 | 2008-03-05 | 联想(北京)有限公司 | Virtual machine system and hardware equipment interrupt handling method thereof |
| CN101299206A (en) * | 2008-06-24 | 2008-11-05 | 中兴通讯股份有限公司 | Method and apparatus for realizing interrupt acquisition |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050228923A1 (en) * | 2004-03-30 | 2005-10-13 | Zimmer Vincent J | Efficiently supporting interrupts |
| CN101135997A (en) * | 2006-08-29 | 2008-03-05 | 联想(北京)有限公司 | Virtual machine system and hardware equipment interrupt handling method thereof |
| CN101299206A (en) * | 2008-06-24 | 2008-11-05 | 中兴通讯股份有限公司 | Method and apparatus for realizing interrupt acquisition |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103631649A (en) * | 2012-08-24 | 2014-03-12 | 深圳市中兴微电子技术有限公司 | Interrupt processing method and device and interrupt controller |
| CN112181877A (en) * | 2020-10-28 | 2021-01-05 | 瑞芯微电子股份有限公司 | Display frequency conversion method and system |
| CN112181877B (en) * | 2020-10-28 | 2022-06-21 | 瑞芯微电子股份有限公司 | Display frequency conversion method and system |
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