CN101893998A - Main board and access control method for memories - Google Patents
Main board and access control method for memories Download PDFInfo
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- CN101893998A CN101893998A CN2009101384756A CN200910138475A CN101893998A CN 101893998 A CN101893998 A CN 101893998A CN 2009101384756 A CN2009101384756 A CN 2009101384756A CN 200910138475 A CN200910138475 A CN 200910138475A CN 101893998 A CN101893998 A CN 101893998A
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Abstract
The invention provides a main board and an access control method for memories. The main board comprises a first memory, a second memory, a voltage generator, an embedded controller and a chip set. The second memory stores a basic input/output system and a plurality of memory type data. The voltage generator generates a first voltage. The embedded controller is connected with the voltage generator, receives the first voltage and generates a control signal according to the first voltage. The chip set is connected with the first memory, the second memory and the embedded controller, and selects a memory type data corresponding to the first memory from the plurality of memory type data according to the control signal to store the first memory.
Description
Technical field
The present invention relates to a kind of motherboard, particularly a kind of circuit use cost and the motherboard that increases the debug convenience and access control method of storer saved.
Background technology
Storer is one of indispensable member in the computer system, and along with the increase day by day of memory span, the data management of memory inside also will influence the usefulness of memory data access.
In general, the legacy hosts plate is except configuration machine carried memory (on-board memory), also can additionally increase an electrically erasable programmable ROM (Electrically Erasable Programmable Read-Only Memory, hereinafter to be referred as EEPROM) write down the parameters of above-mentioned machine carried memory, so that behind the computer system power-on and when carrying out initialization, (Basic Input Output System BIOS) can come machine carried memory is carried out access Basic Input or Output System (BIOS) according to the data that EEPROM stored.
Though above-mentioned way relatively saves trouble, program is also relatively more simple, but when mistake appears in the content of EEPROM, the user can't make mode with the naked eye directly find mistake, and also is not easy to detect, and whether necessary use specific instrument or program stoning be wrong to the content of EEPROM.Thus, make that the test of EEPROM is quite inconvenient, also increased the difficulty in the debug.
Summary of the invention
The invention provides the access control method of a kind of motherboard and storer, can save the circuit use cost effectively, and increase the convenience on the memory stores.
The present invention proposes a kind of motherboard, comprises first memory, second memory, voltage generator, embedded controller and chipset.Second memory storage BIOS and a plurality of type of memory data.Voltage generator produces first voltage.Embedded controller is connected with voltage generator, receives first voltage, and produces control signal according to first voltage.Chipset connects first memory, second memory and embedded controller, and chipset is selected type of memory data corresponding to first memory with the access first memory according to control signal from a plurality of type of memory data.
In one embodiment of this invention, above-mentioned voltage generator comprises first resistance and second resistance.First termination of first resistance is received second voltage, and its second end produces first voltage.First end of second resistance is connected with second end of first resistance, and its second end connects earth terminal.
In one embodiment of this invention, the said chip group comprises north bridge wafer and south bridge wafer.The north bridge wafer is connected with first memory.The south bridge wafer connects north bridge wafer, second memory and embedded controller.
In one embodiment of this invention, above-mentioned motherboard also comprises central processing unit, and it is connected with the north bridge wafer.
In an embodiment of the present invention, above-mentioned first memory is machine carried memory (on board memory).
In one embodiment of this invention, above-mentioned machine carried memory is a random access memory.
In one embodiment of this invention, above-mentioned second memory is a ROM of BIOS.
In one embodiment of this invention, above-mentioned type of memory data are that sequence exists the detection data.
The present invention proposes a kind of access control method of storer, comprises the following steps: at first, receives first voltage.Then, according to above-mentioned first voltage, produce control signal.Afterwards, according to above-mentioned control signal, from a plurality of type of memory data, select type of memory data corresponding to storer with the described storer of access.
In sum, the present invention produces first voltage (that is utilizing first resistance and second resistance to produce first voltage in the mode of dividing potential drop) by voltage generator, and embedded controller produces control signal according to first voltage again, so that from a plurality of type of memory data that second memory is stored, select the type of memory data of corresponding first memory, with the access first memory.Thus, the circuit use cost can be saved effectively, and the convenience in the debug can be increased.
For above-mentioned feature and advantage of the present invention can be become apparent,, and elaborate in conjunction with the accompanying drawings below especially exemplified by embodiment.
Description of drawings
Fig. 1 is the synoptic diagram of the motherboard of one embodiment of the invention;
Fig. 2 is the access control method process flow diagram of the storer of one embodiment of the invention.
The main element symbol description:
Motherboard-100; Central processing unit-110;
First memory-120; Second memory-130;
Voltage generator-140; Embedded controller-150;
Chipset-160; North bridge wafer-161;
South bridge wafer-162; First resistance-R1;
Second resistance-R2; First voltage-V1;
Second voltage-V2; Control signal-CS;
Earth terminal-GND;
Each step-S210 of the access control method of the storer of embodiments of the invention～S230.
Embodiment
Fig. 1 is the synoptic diagram of the motherboard of one embodiment of the invention.Please refer to Fig. 1, motherboard 100 comprises central processing unit (Central Processor Unit, CPU) 110, first memory 120, second memory 130, voltage generator 140, embedded controller (Embedded controller, EC) 150 with chipset (Chipset) 160.
In the present embodiment, first memory 120 is machine carried memory (on-board memory), and can be random access memory (Random Access Memory, RAM), dynamic RAM (Dynamic Random Access Memory for example, DRAM), (Static Random Access Memory SRAM), DDR-I storer, DDR-II storer etc., but does not limit its scope to static RAM.
(Basic Input Output System is BIOS) with a plurality of type of memory data for second memory 130 storage Basic Input or Output System (BIOS)s.In the present embodiment, second memory 130 is ROM of BIOS (Only-read Memory).In addition, above-mentioned type of memory data recording the related data of first memory 120, and can be that sequence exists detection (Serial Presence Detect, SPD) data.
Voltage generator 140 is in order to produce the first voltage V1, and wherein voltage generator 140 comprises first resistance R 1 and second resistance R 2.First termination of first resistance R 1 is received the second voltage V2 (for example being operating voltage), and second end of first resistance R 1 produces the first voltage V1.First end of second resistance R 2 connects second end of first resistance R 1, and second end of second resistance R 2 connects earth terminal GND.
In the present embodiment, the pass of the first voltage V1 and the second voltage V2 is V1=V2*R2/ (R1+R2), so the user can be by adjusting the first voltage V1 that first resistance R 1 and the resistance value of second resistance R 2 produce different magnitudes of voltage.In addition, the first voltage V1 of different magnitudes of voltage can correspond to different type of memory data.For instance, when the magnitude of voltage 1/5*V2 of the first voltage V1, for example Dui Ying type of memory data are the type of memory data of DRAM, and when the magnitude of voltage of the first voltage V1 was 2/5*V2, for example Dui Ying type of memory data were the type of memory data of SRAM.
Embedded controller 150 is connected with voltage generator 140, receives the first voltage V1, and produces control signal CS according to the first voltage V1.That is to say that embedded controller 150 can be changed the magnitude of voltage of the first voltage V1 after receiving the first voltage V1, and corresponding generation control signal CS.In the present embodiment, control signal CS for example is a digital signal, and the transformational relation between the magnitude of voltage of the first voltage V1 and the control signal CS for example can be as described below: when V1=1/5*V2, control signal CS is [0001], when V1=2/5*V2, control signal CS is [0010], and when V1=3/5*V2, control signal CS is [0011].And above-mentioned transformational relation only is a kind of form of the present invention, those skilled in the art can push away by above-mentioned explanation other transformational relation, so do not repeat them here.
In the present embodiment, 160 of chipsets include interconnected north bridge wafer 161 and south bridge wafer 162.North bridge wafer 161 connects central processing unit 110 and first memory 120, and south bridge wafer 162 connects second memory 130 and embedded controller 150.And chipset 160 can be according to control signal CS, make that central processing unit 110 can be by chipset 160 from the stored a plurality of type of memory data of second memory 130, select type of memory data, so that first memory 120 is carried out access corresponding to first memory 120.
In the present embodiment, above-mentioned control signal CS for example can utilize the mode of tabling look-up to obtain with the corresponding relation of the type of memory data of corresponding first memory 120.For instance, when control signal CS is [0001], the type of memory data of then corresponding first memory 120 are the type of memory data of DRAM, when control signal CS is [0010], the type of memory data of then corresponding first memory 120 are the type of memory data of SRAM, when control signal CS was [0011], the type of memory data of then corresponding first memory 120 were the type of memory data of DDR-I storer.
Therefore, the motherboard 100 of present embodiment does not need to dispose in addition electrically erasable programmable ROM (Electrically Erasable Programmable Read-Only Memory, hereinafter to be referred as EEPROM) write down the type of memory data of first memory 120, therefore can save the circuit use cost effectively, and the problem of eeprom content mistake also can not take place.In addition, the user can directly detect the combination of first resistance R 1 and second resistance R 2 and check whether first memory 120 type of memory data pairing with it are wrong, therefore can increase the convenience in the debug.
By the explanation of the foregoing description, can summarize a kind of access control method of storer.Fig. 2 is the access control method process flow diagram of the storer of one embodiment of the invention.Please refer to Fig. 2, in step S210, receive first voltage.In step S220,, produce control signal according to first voltage.In step S230,, from a plurality of type of memory data, select and come access memory corresponding to the type of memory data of storer according to control signal.
In sum, the present invention produces first voltage (that is utilizing first resistance and second resistance to produce first voltage in the mode of dividing potential drop) by voltage generator, and embedded controller produces control signal according to first voltage again, so that from the stored a plurality of type of memory data of second memory, select the type of memory data of corresponding first memory, with the access first memory.Thus, circuit use cost (that is EEPROM) can be saved effectively, and the convenience in the debug can be increased.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (12)
1. motherboard comprises:
One first memory;
One second memory is stored a Basic Input or Output System (BIOS) and a plurality of type of memory data;
One voltage generator produces one first voltage;
One embedded controller is connected with described voltage generator, receives described first voltage, and produces a control signal according to described first voltage; And
One chipset, connect described first memory, described second memory and described embedded controller, described chipset is selected type of memory data corresponding to described first memory with the described first memory of access according to described control signal from described a plurality of type of memory data.
2. motherboard according to claim 1, wherein said voltage generator comprises:
One first resistance, its first termination is received one second voltage, and its second end produces described first voltage; And
One second resistance, its first end connects second end of described first resistance, and its second end connects earth terminal.
3. motherboard according to claim 1, wherein said chipset comprises:
One north bridge wafer is connected with described first memory; And
One south bridge wafer connects described north bridge wafer, described second memory and described embedded controller.
4. motherboard according to claim 3 also comprises:
One central processing unit is connected with described north bridge wafer.
5. motherboard according to claim 1, wherein said first memory are machine carried memory.
6. motherboard according to claim 5, wherein said machine carried memory are random access memory.
7. motherboard according to claim 1, wherein said second memory are ROM of BIOS.
8. motherboard according to claim 1, wherein said type of memory data are that sequence exists the detection data.
9. the access control method of a storer comprises:
Receive one first voltage;
According to described first voltage, produce a control signal; And
According to described control signal, from a plurality of type of memory data, select type of memory data corresponding to storer with the described storer of access.
10. the access control method of storer according to claim 9, wherein said storer is a machine carried memory.
11. the access control method of storer according to claim 10, wherein said machine carried memory are random access memory.
12. being sequence, the access control method of storer according to claim 9, wherein said type of memory data have the detection data.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2009101384756A CN101893998A (en) | 2009-05-18 | 2009-05-18 | Main board and access control method for memories |
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| CN2009101384756A CN101893998A (en) | 2009-05-18 | 2009-05-18 | Main board and access control method for memories |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890640A (en) * | 2011-07-18 | 2013-01-23 | 鸿富锦精密工业（深圳）有限公司 | System and method for managing virtual machine |
| CN102915076A (en) * | 2011-08-03 | 2013-02-06 | 鸿富锦精密工业（深圳）有限公司 | Computer mainboard and voltage regulation circuit thereof |
-
2009
- 2009-05-18 CN CN2009101384756A patent/CN101893998A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890640A (en) * | 2011-07-18 | 2013-01-23 | 鸿富锦精密工业（深圳）有限公司 | System and method for managing virtual machine |
| CN102915076A (en) * | 2011-08-03 | 2013-02-06 | 鸿富锦精密工业（深圳）有限公司 | Computer mainboard and voltage regulation circuit thereof |
| CN102915076B (en) * | 2011-08-03 | 2016-06-29 | 鸿富锦精密工业（深圳）有限公司 | Computer motherboard and voltage regulator circuit thereof |
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Open date: 20101124 |