CN101887892A - Pixel structure and display panel comprising same - Google Patents
Pixel structure and display panel comprising same Download PDFInfo
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- CN101887892A CN101887892A CN 201010198439 CN201010198439A CN101887892A CN 101887892 A CN101887892 A CN 101887892A CN 201010198439 CN201010198439 CN 201010198439 CN 201010198439 A CN201010198439 A CN 201010198439A CN 101887892 A CN101887892 A CN 101887892A
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Abstract
The invention discloses a pixel structure and a display panel comprising the same. The pixel structure comprises a first scanning line, a second scanning line, a data line, a first insulating layer, a second insulating layer, a capacitance electrode wire, a third insulating layer, a first active component, a second active component, a first pixel electrode and a second pixel electrode, wherein the data line is not parallel to the first scanning line and the second scanning line, and parts of the data line, the first scanning line and the second scanning line are positioned on the same film; the first insulating layer covers the first scanning line, the second scanning line and parts of the data line and is provided with a first dent positioned on two sides of parts of the data line; the second insulating layer covers the first insulating layer; the capacitance electrode wire is positioned on the second insulating layer and covers the data line and the first dent; the third insulating layer is positioned on the capacitance electrode wire; the first active component is electrically connected with the second scanning line and the data line; the second active component is electrically connected with the first scanning line and the first active component; and the first pixel electrode and the second pixel electrode are positioned on the third insulating layer and are respectively and electrically connected with the first active component and the second active component. The invention can alleviate the problem that the charge or the signal of the pixel electrode is affected because of overlarge parasitic capacitance between the pixel electrode and the data line.
Description
Technical field
The present invention is about a kind of dot structure, and especially in regard to a kind of liquid crystal display panel pixel structure.
Background technology
Generally speaking, display panels is made of the liquid crystal layer that an active component array base board, a subtend substrate and are sandwiched between active component array base board and the subtend substrate, wherein active component array base board can be divided into viewing area (display region) and non-display area (non-display region), wherein on the viewing area, dispose a plurality of pixel cells, and each pixel cell comprises thin-film transistor (TFT) and the pixel electrode (pixel electrode) that is connected with thin-film transistor with arrayed.In addition, dispose multi-strip scanning line (scan line) and data wire (data line) in the viewing area, the thin-film transistor of each pixel cell is to be electrically connected with data wire with corresponding scanning line.In non-display area, then dispose holding wire, source electrode driver (source driver) and gate drivers (gate driver).
Resolution lifting along with display panels, LCD just must be by increasing gate drivers cooperate resolution with the use number of source electrode driver lifting, and because of the use number increase of gate drivers and source electrode driver can allow non-display area (or being called frame) the area change greatly.For the foregoing reasons, the production cost of LCD just increases along with the usage quantity of gate drivers, source electrode driver, and frame is also increasing simultaneously.If can be with the use decreased number of gate drivers and/or source electrode driver, just the workout cost problem that can't reduce and make narrow frame, the i.e. less product of non-display area area easily.
Summary of the invention
The display floater that the invention provides a kind of dot structure and have this kind dot structure, it can solve because of the excessive problem that the electric charge or the signal of pixel electrode are exerted an influence of the parasitic capacitance between pixel electrode and the data wire.
The present invention proposes a kind of dot structure, and this dot structure comprises scan line, data wire, first insulating barrier, second insulating barrier, capacitance electrode line, the 3rd insulating barrier, active member, pixel electrode.Scan line and another scan line are positioned on the substrate.Data wire is arranged on the substrate and is not parallel to scan line and another scan line, and wherein Yi Bufen data wire and scan line and another scan line are positioned at same rete.First insulating barrier covers first scan line, second scan line and described partial data line, and wherein first insulating barrier has first depression, and it is positioned at the both sides of described partial data line.Second insulating barrier covers first insulating barrier.Capacitance electrode line is positioned on second insulating barrier and the cover data line, and wherein capacitance electrode line more covers first depression of first insulating barrier.The 3rd insulating barrier is positioned on the capacitance electrode line.Active member is electrically connected with data wire.Pixel electrode is positioned on the 3rd insulating barrier and with the active member of another pixel and is electrically connected.
The present invention proposes a kind of display floater in addition, and it comprises first substrate, second substrate and display medium.First substrate has a plurality of dot structures, and each dot structure as mentioned above.Second substrate is positioned at the subtend of first substrate.Display medium is between first substrate and second substrate.
Based on above-mentioned, because first insulating barrier of dot structure has the both sides that first depression and first depression are positioned at the partial data line, and capacitance electrode line covers first depression of first insulating barrier.Therefore, capacitance electrode line can cover data wire, to reduce the parasitic capacitance between data wire and the pixel electrode.Thus, just can reduce the excessive and problem that the electric charge or the signal of pixel electrode exerted an influence of parasitic capacitance between pixel electrode and the data wire.
Description of drawings
Fig. 1 is the vertical view of the dot structure of one embodiment of the invention.
Fig. 2 is the vertical view that the dot structure of Fig. 1 omits capacitance electrode line.
Fig. 3 is the generalized section of Fig. 1 along hatching A-A ', B-B ', C-C ' and D-D '.
Fig. 4 is the partial cutaway schematic of the dot structure of another embodiment of the present invention, the generalized section that its corresponding diagram 1 is located along hatching B-B '.
Fig. 5 is the vertical view of the dot structure of another embodiment of the present invention.
Fig. 6 is the generalized section of Fig. 5 along hatching A-A ', B-B ', C-C ' and D-D '.
Fig. 7 is the partial cutaway schematic of the dot structure of an embodiment more of the present invention, the generalized section that its corresponding diagram 5 is located along hatching B-B '.
Fig. 8 is the schematic diagram of the display floater of one embodiment of the invention.
Drawing reference numeral
SL1, SL2: scan line
DL: data wire
DL-1, DL-2: data line segment
GP: sweep signal transmission line
GP-1, GP-2: sweep signal transmission line section
T1, T2: active member
G1, G2: grid
CH1, CH2: passage
S1, S2: source electrode
D1, D2: drain electrode
CL: capacitance electrode line
C1, C2, C3, C4, C5: contact hole
OP: opening
PE1, PE2: pixel electrode
R1, R2: depression
100,200: substrate
102,104,106: insulating barrier
300: display medium
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended accompanying drawing to be described in detail below.
The display panels of present narrow preset, having a kind of is in pixel upper edge gate line (TrackingGate-line in Pixel, TGP) Wiring architecture its objective is the use number that reduces gate drivers, and correlation technique can be with reference to No. the 098100467th, Taiwan patent application case application number.But, this kind TGP framework has a shortcoming to be, when the scanning-line signal of sweep signal transmission line at commentaries on classics line place is opening (turn-on), parasitic capacitance between pixel electrode and the data wire can be excessive, and the electric charge or the signal of pixel electrode exerted an influence, and then influence the display quality of display panels.
Fig. 1 is the vertical view of dot structure according to an embodiment of the invention.Fig. 2 is the vertical view that the dot structure of Fig. 1 omits capacitance electrode line.Fig. 3 is the generalized section of Fig. 1 along hatching A-A ', B-B ', C-C ' and D-D '.Please refer to Fig. 1, Fig. 2 and Fig. 3, the dot structure of present embodiment comprises the first scan line SL1, the second scan line SL2, data wire DL, first insulating barrier 102, second insulating barrier 104, capacitance electrode line CL, the 3rd insulating barrier 106, the first active member T1, the first pixel electrode PE1, the second active member T2 and the second pixel electrode PE2.
The first scan line SL1 and the second scan line SL2 are positioned on the substrate 100.Both be arranged in parallel the first scan line SL1 and the second scan line SL2, and the first scan line SL1 and the second scan line SL2 are set directly on the surface of substrate 100.Based on the consideration of conductivity, the first scan line SL1 and the second scan line SL2 generally are to use metal material.Therefore, the first scan line SL1 and the second scan line SL2 can be described as the first metal layer again.Yet, the invention is not restricted to this, according to other embodiment, the first scan line SL1 and the second scan line SL2 also can use other electric conducting materials.
Data wire DL is arranged on the substrate 100, and data wire DL is not parallel to the first scan line SL1 and the second scan line SL2 is provided with.Particularly, some and the first scan line SL1 of data wire DL and the second scan line SL2 are positioned at same rete.According to present embodiment, data wire DL comprises at least one first data line segment DL-1 and at least one second data line segment DL-2.The first above-mentioned data line segment DL-1 and the first scan line SL 1 and the second scan line SL2 are positioned at same rete, and therefore the first above-mentioned data line segment DL-1 also belongs to the part of the first metal layer.Particularly, the first data line segment DL-1 does not electrically contact with the first scan line SL1 and the second scan line SL2.That is to say that the first data line segment DL-1 and the first scan line SL1 and the second scan line SL2 separate.In addition, the second above-mentioned data line segment DL-2 crosses over the first scan line SL1 and the second scan line SL2.In other words, accompany an insulating barrier (for example being first insulating barrier 102) between the second data line segment DL-2 and the first scan line SL1 and the second scan line SL2, so that the second data line segment DL-2 and the first scan line SL1 and the second scan line SL2 electric insulation.In addition, according to present embodiment, be to see through contact hole C3 and be electrically connected between the first data line segment DL-1 and the second data line segment DL-2.In other words, contact hole C3 is in the insulating barrier (for example being first insulating barrier 102) of the overlapping region between the first data line segment DL-1 and the second data line segment DL-2, to be electrically connected the first data line segment DL-1 and the second data line segment DL-2.Based on the consideration of conductivity, data wire DL generally is to use metal material, and the second data line segment DL-2 of data wire DL can be described as second metal level again.Yet, the invention is not restricted to this, according to other embodiment, data wire DL also can use other electric conducting materials.
If dot structure of the present invention is the display panels that is applied to narrow preset, then this dot structure can more comprise one scan signal transmssion line GP.Sweep signal transmission line GP is used for the bearing of trend of scan line is translated into the direction parallel with data wire, uses the use number that reduces gate drivers.Therefore, sweep signal transmission line GP is not parallel to the first scan line SL1 and the second scan line SL2 is provided with, and sweep signal transmission line GP is electrically connected with the first scan line SL1.According to present embodiment, above-mentioned sweep signal transmission line GP comprises at least one first sweep signal transmission line section GP1 and at least one second sweep signal transmission line section GP2.The first sweep signal transmission line GP1 and the first scan line SL1 and the second scan line SL2 are positioned at same rete.Therefore the first above-mentioned sweep signal transmission line GP1 also belongs to the part of the first metal layer.In other words, the first sweep signal transmission line GP1 can directly be connected with the first scan line SL1.In addition, the second above-mentioned sweep signal transmission line section GP2 crosses over the second scan line SL2.In other words, accompany an insulating barrier (for example being first insulating barrier 102) between the second above-mentioned sweep signal transmission line section GP2 and the second scan line SL2, so that the second sweep signal transmission line section GP2 and the second scan line SL2 electric insulation.In addition, according to present embodiment, be to see through contact hole C4 and be electrically connected between the first sweep signal transmission line GP1 and the second sweep signal transmission line section GP2.In other words, contact hole C4 is in the insulating barrier (for example being first insulating barrier 102) of the overlapping region between the first sweep signal transmission line GP1 and the second sweep signal transmission line section GP2, to be electrically connected the first sweep signal transmission line GP1 and the second sweep signal transmission line section GP2.Based on the consideration of conductivity, sweep signal transmission line GP generally is to use metal material, and the second sweep signal transmission line section GP2 of sweep signal transmission line GP can be described as second metal level again.Yet, the invention is not restricted to this, according to other embodiment, sweep signal transmission line GP also can use other electric conducting materials.
The first active member T1 is electrically connected with the second scan line SL2 and data wire DL.In the present embodiment, the first active member T1 comprises grid G 1, channel C H1, source S 1 and drain D 1.Grid G 1 is electrically connected with the second scan line SL2.Channel C H1 is positioned at the top of grid G 1.Source S 1 and drain D 1 are positioned at the top of channel C H1, and source S 1 is electrically connected with data wire DL.
The second active member T2 is electrically connected with the first scan line SL1 and the first active member T1.In the present embodiment, the second active member T2 comprises grid G 2, channel C H2, source S 2 and drain D 2.Grid G 2 is electrically connected with the first scan line SL1.Channel C H2 is positioned at the top of grid G 2.Source S 2 and drain D 2 are positioned at the top of channel C H2, and source S 2 is electrically connected with the drain D 1 of the first active member T1.
The first above-mentioned active member T1 and the second active member T2 are to be that example illustrates with the bottom grid film transistor, but the invention is not restricted to this.According to other embodiment, the above-mentioned first active member T1 and the second active member T2 are with the top grid type thin-film transistor.
Capacitance electrode line CL is positioned on second insulating barrier 104 and cover data line DL.In the present embodiment, capacitance electrode line CL is arranged on second insulating barrier 104 of data wire DL top and on second insulating barrier 104 of part first scan line SL1 and second scan line SL2 top.The layout type of the capacitance electrode line CL of present embodiment is except the usefulness of the electrode wires that can be used as reservior capacitor, and it can also cover near scan line in the display panels and the data wire light leak because of lqiuid crystal molecule tipping caused.Yet the do not ration the power supply layout type that holds electrode wires CL of the present invention must be as shown in Figure 1 a form.According to other embodiment, the layout type of capacitance electrode line CL also can be other kinds form.Based on the consideration of conductivity, capacitance electrode line CL generally is to use metal material.Therefore, capacitance electrode line CL can be described as the 3rd metal level again.Yet, the invention is not restricted to this, according to other embodiment, capacitance electrode line CL also can use other electric conducting materials.
Particularly, capacitance electrode line CL more covers the first depression R1 (as shown in Figure 3) of first insulating barrier 102.In more detail, capacitance electrode line CL cover second insulating barrier 104 with and the surface of the second depression R2, or says that the capacitance electrode line CL of part is positioned at second R2 that caves in.In the present embodiment, because first insulating barrier 102 has the first depression R1, and second insulating barrier 104 corresponding first insulating barrier 102 first the depression R1 above also have second the depression R2, therefore the capacitance electrode line CL that is positioned on second insulating barrier 104 can insert the second depression R2, so that the first data line segment DL-1 of data wire DL is almost coated by capacitance electrode line CL or covers.
The 3rd insulating barrier 106 is positioned on the capacitance electrode line CL.The 3rd insulating barrier 106 also covers the first active member T1 and the second active member T2, data wire DL and sweep signal transmission line GP, and therefore the 3rd insulating barrier 106 can be described as protective layer again.
The first pixel electrode PE1 is positioned on the 3rd insulating barrier 106 and with the first active member T1 and is electrically connected.In the present embodiment, be to see through contact hole C1 and be electrically connected between the first pixel electrode PE1 and the first active member T1.In more detail, contact hole C1 is formed in second insulating barrier 104 and the 3rd insulating barrier 106, and electrically contacts with the drain D 1 and the first pixel electrode PE1 of the first active member T1.Because the first pixel electrode PE1 is positioned at the top of common electrode line CL, therefore the first pixel electrode PE1 can produce capacitance coupling effect with electrode wires CL together, to constitute a reservior capacitor.
The second pixel electrode PE2 is positioned on the 3rd insulating barrier 106 and with the second active member T2 and is electrically connected.In the present embodiment, be to see through contact hole C2 and be electrically connected between the second pixel electrode PE2 and the second active member T2.In more detail, contact hole C2 is formed in second insulating barrier 104 and the 3rd insulating barrier 106, and electrically contacts with the drain D 2 and the second pixel electrode PE2 of the second active member T2.Because the second pixel electrode PE2 is positioned at the top of common electrode line CL, therefore the second pixel electrode PE2 can produce capacitance coupling effect with electrode wires CL together, to constitute a reservior capacitor.
What deserves to be mentioned is, because the first active member T1 and the second active member T2 in the dot structure of present embodiment are shared data wire DL.Therefore, between the first pixel electrode PE1 and the second pixel electrode PE2, then another data wire need be set.Thereby the space between the first pixel electrode PE1 and the second pixel electrode PE2 then can be provided with sweep signal transmission line GP.
As mentioned above, because the first data line segment DL-1 of data wire DL is almost enveloped by capacitance electrode line CL, so capacitance electrode line CL can be used as the first data line segment DL-1 of data wire DL and the shielding layer between the first pixel electrode PE1/, the second pixel electrode PE2.In general, owing to can bestow common voltage (Vcom) on the capacitance electrode line CL, therefore, capacitance electrode line CL can reduce the parasitic capacitance that is produced between the first data line segment DL-1 of data wire DL and the first pixel electrode PE1/, the second pixel electrode PE2 effectively, and then reduces by the electric charge of the first pixel electrode PE1/, the second pixel electrode PE2 or the influence that signal is subjected to above-mentioned parasitic capacitance.
In the embodiment of above-mentioned Fig. 3, be in first insulating barrier 102, to form the first depression R1, and because of second insulating barrier 104 be conformably to cover on first insulating barrier 102 so that second insulating barrier 104 also has second R2 that caves in above the first depression R1 of corresponding first insulating barrier 102.Therefore the capacitance electrode line CL that is positioned on second insulating barrier 104 can insert the second depression R2, so that the first data line segment DL-1 of data wire DL is almost enveloped by capacitance electrode line CL.Yet, the invention is not restricted to this, according to other embodiment, can also directly in second insulating barrier 104, form the second depression R2, as shown in Figure 4.
Fig. 4 only illustrates the generalized section of the dot structure of Fig. 1 along B-B ' hatching.In other words, the dot structure of this embodiment is similar to the aforementioned embodiment, and difference only is the section place of B-B ' hatching.Please refer to Fig. 4, second insulating barrier 104 of this embodiment has the second depression R2, and the second depression R2 is positioned at the first depression R1 top.In more detail, the first depression R1 of first insulating barrier 102 exposes substrate 100 surfaces, the second depression R2 of second insulating barrier 104 also exposes the surface of substrate 100, that is to say that the part that second insulating barrier 104 and first insulating barrier 102 stack together can have depression.Therefore, the capacitance electrode line CL that is formed on second insulating barrier 104 is the surface that conformably covers second insulating barrier 104, the first depression R1 and the second depression R2.Thereby capacitance electrode line CL can contact with the surface of substrate 100.
In the embodiment of Fig. 4, owing to capacitance electrode line CL can contact with the surface of substrate 100 at the first depression R1 and the second depression R2 place, so the first data line segment DL-1 of data wire DL can be further by the complete coating of capacitance electrode line CL.Therefore capacitance electrode line CL can be used as the first data line segment DL-1 of data wire DL and the shielding layer between the first pixel electrode PE1/, the second pixel electrode PE2.Similarly, owing to can bestow common voltage (Vcom) on the capacitance electrode line CL, therefore, capacitance electrode line CL can reduce the parasitic capacitance that is produced between the first data line segment DL-1 of data wire DL and the first pixel electrode PE1/, the second pixel electrode PE2 effectively, and then reduces by the electric charge of the first pixel electrode PE1/, the second pixel electrode PE2 or the influence that signal is subjected to above-mentioned parasitic capacitance.
Though all be to be example in the above-described embodiment with dot structure shown in Figure 1, yet, the invention is not restricted to this, in other words, in other embodiments, dot structure of the present invention also can have other layout type.Fig. 5 is the vertical view of dot structure according to still another embodiment of the invention.Fig. 6 is the generalized section of Fig. 5 along hatching A-A ', B-B ', C-C ' and D-D '.What pay special attention to is, the element of the element of Fig. 5 and dot structure shown in Figure 6 and the dot structure of Figure 1 and Figure 2 is roughly the same, therefore use identical label to represent components identical, and can with reference in the preamble corresponding to the explanation of Fig. 1, below only describe between the two main difference.Please refer to Fig. 5, the dot structure of present embodiment comprises the first scan line SL1, the second scan line SL2, data wire DL, first insulating barrier 102, second insulating barrier 104, capacitance electrode line CL, the 3rd insulating barrier 106, the first active member T1, the first pixel electrode PE1, the second active member T2 and the second pixel electrode PE2.
The first active member T1 is electrically connected with the second scan line SL2 and data wire DL.In the present embodiment, the first active member T1 comprises grid G 1, channel C H1, source S 1 and drain D 1.Grid G 1 is electrically connected with the second scan line SL2.Channel C H1 is positioned at the top of grid G 1.Source S 1 and drain D 1 are positioned at the top of channel C H1, and source S 1 is electrically connected with data wire DL.
The second active member T2 is electrically connected with the first scan line SL1 and the first active member T1.In the present embodiment, the second active member T2 comprises grid G 2, channel C H2, source S 2 and drain D 2.Grid G 2 is electrically connected with the first scan line SL1.Channel C H2 is positioned at the top of grid G 2.Source S 2 and drain D 2 are positioned at the top of channel C H2.Source S 2 sees through contact hole C5 and is electrically connected with the first pixel electrode PE1, and the first pixel electrode PE1 is electrically connected with the drain D 1 of the first active member T1 by contact hole C1, and therefore the second active member T2 is electrically connected with the first active member T1.
Please be simultaneously with reference to Fig. 5 and Fig. 6, in the present embodiment, be to be electrically connected between the first pixel electrode PE1 and the first active member T1 through contact hole C1.In more detail, contact hole C1 is formed in second insulating barrier 104 and the 3rd insulating barrier 106, and electrically contacts with the drain D 1 and the first pixel electrode PE1 of the first active member T1.Be to see through contact hole C2 and be electrically connected between the second pixel electrode PE2 and the second active member T2.In more detail, contact hole C2 is formed in second insulating barrier 104 and the 3rd insulating barrier 106, and electrically contacts with the drain D 2 and the second pixel electrode PE2 of the second active member T2.
In the present embodiment, capacitance electrode line CL has network structure (mesh structure), and it has opening OP.Capacitance electrode line CL is positioned on second insulating barrier 104 and cover part data wire DL.In the present embodiment, capacitance electrode line CL is arranged on second insulating barrier 104 of data wire DL top and on second insulating barrier 104 of the first scan line SL1 and second scan line SL2 top.Particularly, capacitance electrode line CL more covers the first depression R1 (as shown in Figure 6) of first insulating barrier 102.In more detail, capacitance electrode line CL cover second insulating barrier 104 with and second the depression R2 the surface.In the present embodiment, because first insulating barrier 102 has the first depression R1, and second insulating barrier 104 corresponding first insulating barrier 102 first the depression R1 above also have second the depression R2, therefore the capacitance electrode line CL that is positioned on second insulating barrier 104 can insert the second depression R2, so that capacitance electrode line CL envelopes segment data line DL.In addition, according to other embodiment, can also directly in second insulating barrier 104, form the second depression R2, as shown in Figure 7.In the embodiment shown in fig. 7, owing to capacitance electrode line CL can contact with the surface of substrate 100 at the first depression R1 and the second depression R2 place, so the both sides of data wire DL-1 can further be coated by capacitance electrode line CL or cover.
As mentioned above, because capacitance electrode line CL envelopes segment data line DL, so capacitance electrode line CL can be used as the first data line segment DL-1 of data wire DL and the shielding layer between the first pixel electrode PE1/, the second pixel electrode PE2.
Fig. 8 is the schematic diagram of display floater according to an embodiment of the invention.Please refer to Fig. 8, the display floater of present embodiment comprises first substrate 100, second substrate 200 and the display medium 300 between first substrate 100 and second substrate 200.
The material of first substrate 100 can be glass, quartz, organic polymer or metal or the like.Comprise on first substrate 100 being provided with pel array layer 150, described pel array layer 150 is made of a plurality of dot structure.And the dot structure in the pel array layer 150 can be as Fig. 1 and dot structure, Fig. 1 and dot structure, Fig. 5 and dot structure shown in Figure 6 shown in Figure 4 shown in Figure 3, or Fig. 5 and dot structure shown in Figure 7.The material of second substrate 200 can be glass, quartz or organic polymer or the like.In one embodiment, can comprise on second substrate 200 and be provided with the electrode layer (not shown).Electrode layer is a transparency conducting layer, and its material comprises metal oxide, for example is indium tin oxide or indium-zinc oxide.Electrode layer is to be covered in all sidedly on second substrate 200.In addition, according to another embodiment of the present invention, can comprise more on second substrate 200 being provided with the colour filter array (not shown) that it comprises red, green, blue look filter pattern.In addition, can comprise more on second substrate 200 the shielding pattern layer (not shown) is set that it can be described as black matrix again, it is arranged between the pattern of colour filter array.Display medium 300 can comprise liquid crystal molecule or electrophoretic display medium.
In sum, owing to data wire of the present invention can be enveloped by capacitance electrode line, so capacitance electrode line can be used as the shielding layer between data wire and the pixel electrode.In addition, because of can bestowing common voltage on the capacitance electrode line, so capacitance electrode line can reduce the parasitic capacitance that is produced between data wire and the pixel electrode effectively, and then reduces the electric charge of pixel electrode or the influence that signal is subjected to above-mentioned parasitic capacitance.Therefore, use the display floater of this kind dot structure to have better display quality.
Though the present invention discloses as above with embodiment; right its is not in order to qualification the present invention, any the technical staff in the technical field, without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is when being as the criterion with claim institute confining spectrum.
Claims (13)
1. a dot structure is characterized in that, described dot structure is positioned on the substrate, and described dot structure comprises:
One first scan line and one second scan line;
One data wire, it is not parallel to described first scan line and the described second scan line setting, and wherein Yi Bufen described data wire and described first scan line and described second scan line are positioned at same rete;
One first insulating barrier covers described first scan line, described second scan line and described partial data line, and wherein said first insulating barrier has one first depression, and it is positioned at the both sides of described partial data line;
One second insulating barrier covers described first insulating barrier;
One capacitance electrode line is positioned on described second insulating barrier and covers described data wire, and wherein said capacitance electrode line more covers described first depression of described first insulating barrier;
One the 3rd insulating barrier is positioned on the described capacitance electrode line;
One first active member, it is electrically connected with described second scan line and described data wire;
One first pixel electrode is positioned on described the 3rd insulating barrier and with described first active member and is electrically connected;
One second active member, it is electrically connected with described first scan line and described first active member; And
One second pixel electrode is positioned on described the 3rd insulating barrier and with described second active member and is electrically connected.
2. dot structure as claimed in claim 1 is characterized in that, described first depression of described first insulating barrier exposes the surface of described substrate.
3. dot structure as claimed in claim 1 is characterized in that, described second insulating barrier conformably covers on the surface of first insulating barrier, so that described second insulating barrier forms one second depression above described first depression.
4. dot structure as claimed in claim 3 is characterized in that, described capacitance electrode line covers the surface of described second insulating barrier and described second depression.
5. dot structure as claimed in claim 1 is characterized in that, described second insulating barrier has one second depression, and described second depression is positioned at the described first depression top.
6. dot structure as claimed in claim 5 is characterized in that, described first depression and described second depression expose the surface of described substrate.
7. dot structure as claimed in claim 5 is characterized in that, described capacitance electrode line covers the surface of described second insulating barrier, described first depression and described second depression.
8. dot structure as claimed in claim 1, it is characterized in that, described data wire comprises at least one first data line segment and at least one second data line segment, described at least one first data line segment is positioned at same rete with described first scan line and described second scan line genus and does not electrically contact each other, and described at least one second data line segment is crossed over described first scan line and described second scan line.
9. dot structure as claimed in claim 8 is characterized in that, more comprises a contact hole, the overlapping region between described at least one first data line segment and described at least one second data line segment.
10. dot structure as claimed in claim 1 is characterized in that, more comprises the one scan signal transmssion line, and it is not parallel to described first scan line and the described second scan line setting, and described sweep signal transmission line is electrically connected with described first scan line.
11. dot structure as claimed in claim 10, it is characterized in that, described sweep signal transmission line comprises at least one first sweep signal transmission line section and at least one second sweep signal transmission line section, described at least one first sweep signal transmission line and described first scan line and described second scan line are positioned at same rete, described at least one first sweep signal transmission line directly is connected with described first scan line, and described at least one second sweep signal transmission line section is crossed over described second scan line.
12. dot structure as claimed in claim 10 is characterized in that, described sweep signal transmission line is between described first pixel electrode and described second pixel electrode.
13. a display floater is characterized in that, comprising:
One first substrate, it has a plurality of dot structures, and each dot structure is according to claim 1;
One second substrate is positioned at the subtend of described first substrate; And
One display medium is between described first substrate and described second substrate.
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| CN2010101984391A CN101887892B (en) | 2010-06-07 | 2010-06-07 | Pixel structure and display panel comprising same |
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| CN2010101984391A CN101887892B (en) | 2010-06-07 | 2010-06-07 | Pixel structure and display panel comprising same |
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| CN101887892B CN101887892B (en) | 2012-02-01 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103439821A (en) * | 2013-08-26 | 2013-12-11 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display array substrate and liquid crystal display |
| CN110109305A (en) * | 2019-04-12 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
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| CN103439821A (en) * | 2013-08-26 | 2013-12-11 | 南京中电熊猫液晶显示科技有限公司 | Liquid crystal display array substrate and liquid crystal display |
| CN103439821B (en) * | 2013-08-26 | 2017-03-01 | 南京中电熊猫液晶显示科技有限公司 | A kind of LCD (Liquid Crystal Display) array substrate and liquid crystal display |
| WO2020124896A1 (en) * | 2018-12-19 | 2020-06-25 | 深圳市华星光电半导体显示技术有限公司 | Liquid crystal display panel |
| CN110109305A (en) * | 2019-04-12 | 2019-08-09 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| US11333946B2 (en) | 2019-04-12 | 2022-05-17 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display module |
| CN111258141A (en) * | 2020-03-06 | 2020-06-09 | Tcl华星光电技术有限公司 | Display panel and display device |
| WO2021174632A1 (en) * | 2020-03-06 | 2021-09-10 | Tcl华星光电技术有限公司 | Display panel and display apparatus |
| US11610532B2 (en) | 2020-03-06 | 2023-03-21 | Tcl China Star Optoelectronics Technology Co., Ltd. | Display panel and display device |
| CN115097675A (en) * | 2022-07-21 | 2022-09-23 | 合肥京东方显示技术有限公司 | Array substrate and manufacturing method thereof, liquid crystal display panel and display device |
| CN115097675B (en) * | 2022-07-21 | 2024-04-16 | 合肥京东方显示技术有限公司 | Array substrate, manufacturing method thereof, liquid crystal display panel and display device |
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