CN101635300A - Thin film transistor substrate and manufacturing process thereof - Google Patents
Thin film transistor substrate and manufacturing process thereof Download PDFInfo
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- CN101635300A CN101635300A CN200810142521A CN200810142521A CN101635300A CN 101635300 A CN101635300 A CN 101635300A CN 200810142521 A CN200810142521 A CN 200810142521A CN 200810142521 A CN200810142521 A CN 200810142521A CN 101635300 A CN101635300 A CN 101635300A
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Abstract
The invention relates to a thin film transistor substrate and a manufacturing process thereof. The thin film transistor substrate comprises a plurality of scanning lines, a plurality of thin film transistors, a plurality of first data lines which are arranged on the same layer with the scanning lines, a plurality of second data lines which stride over the scanning lines and are connected with the first data lines, and a public electrode which covers the first data lines. The grid electrodes of the thin film transistors are connected to the scanning lines, and the source electrodes are connected to the second data lines.
Description
Technical field
The invention relates to a kind of thin film transistor base plate and manufacturing process thereof.
Background technology
Display panels generally includes a thin film transistor base plate, a colored filter substrate and is clipped in liquid crystal layer between these two substrates, it is by applying voltages to this two substrates respectively, control therebetween that liquid crystal molecule reverses and realizes passing through or not passing through of light, thereby reach the purpose of demonstration.The liquid crystal drive mode of tradition display panels is a nematic mode, yet its angular field of view is narrow, when promptly observing picture from different perspectives, will observe different display effects.
Fringe field switch (Fringe Field Switching, FFS) technology is based on problems such as the visual angle of traditional display panels is narrow and small and the solution that proposes, itself and plane internal switch (In-Plane Switching, IPS) wide viewing angle technology difference is, the switching edge technology will place by the public electrode integral body that transparency conducting layer forms above or below the pixel electrode, thereby obtained fringe field efficiently, improved aperture opening ratio, and reduced the light leakage.Therefore, the fringe field switching technique has better visual angle and contrast.
Seeing also Fig. 1, is a kind of part plan schematic diagram of prior art thin film transistor base plate.This thin film transistor base plate 100 comprises scan line 117, many data wire 146, a plurality of thin-film transistor 101, a plurality of pixel electrode 135 and public electrodes 156 that parallel interval is provided with that many parallel interval are provided with.These many data wires 146 and these 117 vertically insulated intersecting of multi-strip scanning line.This thin-film transistor 101 is positioned at the intersection of this scan line 117 and this data wire 146.The grid 116 of this thin-film transistor 101 is connected to this scan line 117, and source electrode 144 is connected to this data wire 146, and drain electrode 145 is connected to this pixel electrode 135.
Seeing also Fig. 2, is the generalized section of this thin film transistor base plate 100 along II1-II1 direction and II2-II2 direction.This thin film transistor base plate 100 comprises a substrate of glass 111.This scan line 117 and this grid 116 are arranged on the upper surface of this substrate of glass 111.The upper surface of this scan line 117, this grid 116 and this substrate of glass 111 is provided with a gate insulator 121.126 pairs of this semiconductor channel layers should grid 116 be arranged on the upper surface of this gate insulator 121, and these pixel electrode 135 contiguous these semiconductor channel layers 126 are arranged on the upper surface of this gate insulator 121.145 pairs of this source electrode 144 and this drain electrodes should grid 116 be arranged on the upper surface of this semiconductor layer channel layer 126, and should the drain gate insulator 121 of 145 coverings between this semiconductor channel layer 126 and this pixel electrode 135 and the part of this pixel electrode 135, this data wire 146 strides across the upper surface that this scan line 117 is arranged on this gate insulator 121.This passivation layer 151 covers this data wire 146, this gate insulator 121, this source electrode 144, this drain electrode 145 and this pixel electrode 135.156 pairs of this public electrodes should data wire 146 and this pixel electrode 135 be arranged on the upper surface of this passivation layer 151.
Seeing also Fig. 3, is the manufacturing process flow diagram of this thin film transistor base plate 100.The manufacturing process of this thin film transistor base plate 100 mainly comprises five road masks, and its key step is as follows:
Step S1: form grid and scan line;
Step S2: form gate insulator and semiconductor channel layer;
Step S3: form pixel electrode;
Step S4: form source electrode, drain electrode, data wire and groove;
Step S5: form passivation layer and public electrode.
But, this thin film transistor base plate 100 that obtains by above-mentioned manufacturing process, all only has a passivation layer 151 between its data wire 146 and the public electrode 156 and between pixel electrode 135 and the public electrode 156, thereby the thinner thickness between two pole plates of the electric capacity that the electric capacity that this data wire 146 and this public electrode 156 constitute and this pixel electrode 135 and this public electrode 156 constitute, make that the capacitance of these two electric capacity is bigger, thereby need expend more electric weight and need the long charging interval these two electric capacity chargings.
Summary of the invention
In order to solve the problem that the power consumption of prior art thin film transistor base plate is many and the charging interval is long, be necessary to provide a kind of little power consumption and short thin film transistor base plate of charging interval.
In order to solve the problem that the thin film transistor base plate power consumption is many and the charging interval is long that prior art thin film transistor base plate manufacturing process obtains, be necessary to provide the manufacturing process of short thin film transistor base plate of a kind of little power consumption and charging interval.
A kind of thin film transistor base plate, it comprises the multi-strip scanning line, a plurality of thin-film transistors, and many are arranged on first data wire with one deck with this multi-strip scanning line, many stride across this scan line and connect second data wire of this first data wire, and one covers the public electrode of this first data wire.The grid of this thin-film transistor is connected to this scan line, and source electrode is connected to this second data wire.
A kind of manufacturing process of thin film transistor base plate, it comprises the steps: to provide a substrate, forms grid, multi-strip scanning line and many first data wires of a plurality of thin-film transistors in this substrate; In this substrate, form pixel electrode; On grid, this multi-strip scanning line, these many first data wires and this pixel electrode of these a plurality of thin-film transistors, form a gate insulator; On this gate insulator, form the semiconductor channel layer in regular turn; Source electrode, the drain electrode that forms a plurality of thin-film transistors on this semiconductor channel layer strides across this scan line with many and is connected second data wire of this first data wire; On these a plurality of thin-film transistor source electrodes, drain electrode and these many second data wires, form a passivation layer; On this passivation layer, form the public electrode of this first data wire of covering.
Compared with prior art, thin film transistor base plate of the present invention and manufacturing process thereof are that this first data wire and this scan line are arranged on same one deck, make the distance of this first data wire and this public electrode increase, thereby the thickness between two pole plates of the electric capacity that this first data wire and this public electrode constitute increases, the capacitance of this electric capacity reduces, thereby can shorten the charging interval of this electric capacity and can reach the effect of power saving.
Description of drawings
Fig. 1 is a kind of part plan schematic diagram of prior art thin film transistor base plate.
Fig. 2 is the generalized section of thin film transistor base plate shown in Figure 1 along II1-II1 direction and II2-II2 direction.
Fig. 3 is the manufacturing process flow diagram of thin film transistor base plate shown in Figure 1.
Fig. 4 is the part plan schematic diagram of thin film transistor base plate first execution mode of the present invention.
Fig. 5 is the generalized section of thin film transistor base plate shown in Figure 4 along V1-V1 direction and V2-V2 direction.
Fig. 6 is the manufacturing process flow diagram of thin film transistor base plate shown in Figure 4.
Fig. 7 to Figure 18 is the side structure schematic diagram of each step of manufacturing process of thin film transistor base plate shown in Figure 4.
Figure 19 is the manufacturing process flow diagram of thin film transistor base plate second execution mode of the present invention.
Embodiment
Seeing also Fig. 4, is the part plan schematic diagram of thin film transistor base plate first execution mode of the present invention.This thin film transistor base plate 200 comprises multi-strip scanning line 217, many first data wires 218, many second data wires 256, a plurality of thin-film transistor 201, a plurality of pixel electrode 225, a public electrode 266, a plurality of first through hole 243 and a plurality of second through holes 245.
This multi-strip scanning line 217 is parallel to each other and is provided with at interval.This first data wire 218 is vertical mutually with this scan line 217 and be arranged on same one deck, and this first data wire 218 is making itself and this scan line 217 mutually insulateds near this scan line 217 places disconnection.This second data wire 256 be positioned at this scan line 217 directly over, and be positioned at first data wire 218 of these scan line 217 both sides by two first through hole 243 cross-over connections.The grid 216 of this thin-film transistor 201 is connected to this scan line 217, and source electrode 254 is connected to this second data wire 256, and drain electrode 255 is connected to this pixel electrode 225 by this second through hole 245.This public electrode 266 covers this scan line 217, this first data wire 218, this second data wire 256 and this pixel electrode 225.
Seeing also Fig. 5, is the generalized section of this thin film transistor base plate 200 along V1-V1 direction and V2-V2 direction.This thin film transistor base plate 200 comprises a substrate of glass 211.This first data wire 218, this scan line 217, this grid 216 and this pixel electrode 225 are arranged on the upper surface of this substrate of glass 211.Two parts that this first data wire 218 disconnects are positioned at this scan line 217 both sides.This pixel electrode 225 is positioned at a side of this grid 216.The upper surface of this first data wire 218, this scan line 217, this grid 216, this pixel electrode 225 and this substrate of glass 211 is provided with a gate insulator 231.231 pairs of this gate insulators should first data wire, 218 contiguous these scan lines 217 two ends respectively form one first through hole 243, position that should pixel electrode 225 contiguous these drain electrodes 255 is formed one second through hole 245.236 pairs of this semiconductor channel layers should grid 216 be arranged on the upper surface of this gate insulator 231.255 pairs of this source electrode 254 and this drain electrodes should grid 216 be arranged on the upper surface of this semiconductor layer channel layer 236, and should drain electrode 255 cover this second through hole 245 and the gate insulator 231 between this semiconductor channel layer 236 and this second through hole, this second data wire 256 covers these two first through holes 243 and the gate insulator 231 between these two first through holes 243.This passivation layer 261 covers this gate insulator 231, this second data wire 256, this source electrode 254 and should drain 255.The upper surface that 266 pairs of this public electrodes should first data wire 218, this second data wire 256 and this pixel electrode 225 are arranged on this passivation layer 261.
See also Fig. 6 to Figure 18, Fig. 6 is the manufacturing process flow diagram of this thin film transistor base plate 200, and Fig. 7 to Figure 18 is the side structure schematic diagram of each step of manufacturing process of this thin film transistor base plate 200.The manufacturing process of this thin film transistor base plate 200 mainly comprises six road masks, and concrete steps are as follows:
Step S 21: form grid, scan line and first data wire;
See also Fig. 7 and Fig. 8, a substrate of glass 211 is provided, form a gate metal layer 213 and one first photoresist layer 215 thereon in regular turn.Wherein, this gate metal layer 213 can be a single layer structure, also can be a sandwich construction, and its material can be aluminum-based metal, molybdenum, chromium or copper.
Provide one first mask (figure does not show) to aim at this first photoresist layer 215 and expose, again the first photoresist layer 215 after the exposure is developed, thereby form a predetermined photoresist pattern.This gate metal layer 213 is carried out etching,, remove this first photoresist layer 215, and then form this grid 216, this scan line 217 and this first data wire 218 to remove not by the part of grid pole metal level 213 of this photoresist pattern covers.Wherein, this grid 216 is connected to this scan line 217.This first data wire 218 is vertical mutually with this scan line 217.
Step S22: form pixel electrode;
See also Fig. 9 and Figure 10, on this grid 216, this scan line 217 and this first data wire 218, form one first transparency conducting layer 221 and one second photoresist layer 223 in regular turn.Provide one second mask (figure does not show) to aim at this second photoresist layer 223 and expose, again the second photoresist layer 223 after the exposure is developed, thereby form a predetermined photoresist pattern.This first transparency conducting layer 221 is carried out etching,, remove this second photoresist layer 223, and then form this pixel electrode 225 to remove not by the partially transparent conductive layer 221 of this photoresist pattern covers.
Step S23: form gate insulator and semiconductor channel layer;
See also Figure 11 and Figure 12, on this grid 216, this scan line 217, this first data wire 218 and this pixel electrode 225, form a gate insulator 231, semi-conductor layer 233 and one the 3rd photoresist layer 235 in regular turn.Wherein, this gate insulator 231 is a silicon nitride (SiNx) film, and this semiconductor layer 233 comprises that one is positioned at amorphous silicon layer 2332 and on this gate insulator 231 and is positioned at heavily doped amorphous silicon layer 2331 on this amorphous silicon layer 2332.
Provide one the 3rd mask (figure does not show) to aim at the 3rd photoresist layer 235 and expose, again the 3rd photoresist layer 235 after the exposure is developed, thereby form a predetermined photoresist pattern.This semiconductor layer 233 is carried out etching,, remove the 3rd photoresist layer 235, and then form this semiconductor channel layer 236 to remove not by the part semiconductor layer 233 of this photoresist pattern covers.
Step S24: form first through hole and second through hole;
See also Figure 13 and Figure 14, on this gate insulator 231 and this semiconductor channel layer 236, form one the 4th photoresist layer 241.Provide one the 4th mask (figure does not show) to aim at the 4th photoresist layer 241 and expose, again the 4th photoresist layer 241 after the exposure is developed, thereby form a predetermined photoresist pattern.This gate insulator 231 is carried out etching, to remove not by the part of grid pole insulating barrier 231 of this photoresist pattern covers, and then form this first through hole 243 and this second through hole 245, remove the 4th photoresist layer 241, make that this first data wire 218 and this pixel electrode part are exposed to outside.
Step S25: form source electrode, drain electrode, second data wire and groove;
See also Figure 15 and Figure 16, on this gate insulator 231, this first through hole 243, this second through hole 245 and this semiconductor channel layer 236, form one source/drain metal layer 251 and one the 5th photoresist layer 253 in regular turn.Provide one the 5th mask (figure does not show) to aim at the 5th photoresist layer 253 and expose, again the 5th photoresist layer 253 after the exposure is developed, thereby form a predetermined photoresist pattern.This source/drain metal layer 251 is carried out etching, and then form this source electrode 254, this drain electrode 255 and this second data wire 256.Further adopt HCl (hydrogen chloride) and the mist of SF6 (sulphur hexafluoride) this semiconductor channel layer 236 to be carried out etching, form this groove 257, remove the 5th photoresist layer 253 as etching gas.Wherein, this source electrode 254 is connected to this second data wire 256, this second data wire 256 is by two first these first data wires 218 of through hole 243 cross-over connections, make this first data wire form a data wire that connects this thin film transistor base plate 200, this drain electrode 255 is connected to this pixel electrode 225 by this second through hole 245.
Step S26: form passivation layer and public electrode.
See also Figure 17 and Figure 18, on this gate insulator 231, this source electrode 254, this drain electrode 255, this second data wire 256 and this groove 257, form a passivation layer 261, one second transparency conducting layer 263 and one the 6th photoresist layer 265 in regular turn.Provide one the 6th mask (figure does not show) to aim at the 6th photoresist layer 265 and expose, again the 6th photoresist layer 265 after the exposure is developed, thereby form a predetermined photoresist pattern.This second transparency conducting layer 263 is carried out etching, remove the 6th photoresist layer 265, and then form this public electrode 266.
Compared with prior art, thin film transistor base plate 200 of the present invention and manufacturing process thereof are that this first data wire 218 and this pixel electrode 225 are arranged on same one deck with this scan line, thereby make between this first data wire 218 and this public electrode 266, and all increase by a gate insulator 231 between this pixel electrode 225 and this public electrode 266, make the thickness between two pole plates of the electric capacity that this first data wire 218 and this public electrode 266 constitutes increase, also make the thickness between two pole plates of the electric capacity that this pixel electrode 225 and this public electrode 266 constitutes increase, reduce the capacitance of these two electric capacity, thereby can shorten the charging interval of these two electric capacity and can reach the effect of power saving.
Seeing also Figure 19, is the manufacturing process flow diagram of thin film transistor base plate second execution mode of the present invention.This thin film transistor base plate and the first execution mode transistor base 200 are roughly the same, mainly comprise six road light shields, and concrete steps are as follows:
Step S31: form grid, scan line and first data wire;
Step S32: form pixel electrode;
Step S33: form gate insulator, first through hole and second through hole;
Step S34: form semiconductor channel layer;
Step S35: form source electrode, drain electrode, second data line and groove;
Step S36: form passivation layer and public electrode.
Its main distinction is: form gate insulator, first through hole and second through hole at the 3rd road mask, form semiconductor channel layer at the 4th road mask.
Claims (10)
1. thin film transistor base plate, it comprises: multi-strip scanning line, a plurality of thin-film transistor and a public electrode, it is characterized in that: this thin film transistor base plate comprises that further many are arranged on first data wire and many second data wires with one deck with this multi-strip scanning line, this second data wire strides across this scan line and connects this first data wire, the grid of these a plurality of thin-film transistors is connected respectively to this multi-strip scanning line, source electrode is connected respectively to these many second data wires, and this public electrode covers this first data wire.
2. thin film transistor base plate as claimed in claim 1, it is characterized in that: this thin film transistor base plate further comprises a plurality of first through holes, this first data wire is vertical mutually with this scan line and in close this scan line place disconnection, this second data wire is positioned at first data wire of these scan line both sides by two first through hole cross-over connections.
3. thin film transistor base plate as claimed in claim 2, it is characterized in that: this thin film transistor base plate further comprises a plurality of pixel electrodes and a plurality of second through hole, this pixel electrode and this scan line are arranged on same one deck, and the drain electrode of this thin-film transistor is connected to this pixel electrode by this second through hole.
4. thin film transistor base plate as claimed in claim 3 is characterized in that: this first through hole and this second through hole form in same mask manufacturing technology steps.
5. thin film transistor base plate as claimed in claim 4 is characterized in that: this public electrode further covers this scan line, this second data wire and this pixel electrode.
6. thin film transistor base plate as claimed in claim 1 is characterized in that: this first data wire and this scan line are same materials.
7. the manufacturing process of a thin film transistor base plate, it comprises the steps:
A., one substrate is provided, in this substrate, forms grid, multi-strip scanning line and many first data wires of a plurality of thin-film transistors;
B. in this substrate, form pixel electrode;
C. on grid, this multi-strip scanning line, these many first data wires and this pixel electrode of these a plurality of thin-film transistors, form a gate insulator; On this gate insulator, form the semiconductor channel layer in regular turn;
D. source electrode, the drain electrode that forms a plurality of thin-film transistors on this semiconductor channel layer strides across this scan line with many and is connected second data wire of this first data wire;
E. on source electrode, drain electrode and these many second data wires of these a plurality of thin-film transistors, form a passivation layer; On this passivation layer, form the public electrode of this first data wire of covering.
8. the manufacturing process of thin film transistor base plate as claimed in claim 7, it is characterized in that: further comprise a plurality of first through holes and a plurality of second through hole that run through this gate insulator among this step c, this first through hole is to should second data wire, this second through hole is to drain electrode that should thin-film transistor, and this first through hole and this second through hole form in same mask manufacturing technology steps.
9. the manufacturing process of thin film transistor base plate as claimed in claim 7, it is characterized in that: among this step a, this gate, this scan line and this first data wire form in same mask manufacturing technology steps.
10. the manufacturing process of thin film transistor base plate as claimed in claim 7, it is characterized in that: in this steps d, this source electrode, this drain electrode and this second data wire form in same mask manufacturing technology steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810142521A CN101635300A (en) | 2008-07-25 | 2008-07-25 | Thin film transistor substrate and manufacturing process thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810142521A CN101635300A (en) | 2008-07-25 | 2008-07-25 | Thin film transistor substrate and manufacturing process thereof |
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| CN101635300A true CN101635300A (en) | 2010-01-27 |
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| CN200810142521A Pending CN101635300A (en) | 2008-07-25 | 2008-07-25 | Thin film transistor substrate and manufacturing process thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887892A (en) * | 2010-06-07 | 2010-11-17 | 友达光电股份有限公司 | Pixel structure and display panel comprising same |
| CN102645797A (en) * | 2011-05-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Liquid crystal display device and manufacturing method and display appliance thereof |
-
2008
- 2008-07-25 CN CN200810142521A patent/CN101635300A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887892A (en) * | 2010-06-07 | 2010-11-17 | 友达光电股份有限公司 | Pixel structure and display panel comprising same |
| CN101887892B (en) * | 2010-06-07 | 2012-02-01 | 友达光电股份有限公司 | Pixel structure and display panel comprising same |
| CN102645797A (en) * | 2011-05-17 | 2012-08-22 | 京东方科技集团股份有限公司 | Liquid crystal display device and manufacturing method and display appliance thereof |
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Open date: 20100127 |