CN101883126A - DP-NET data link control mechanism with strict time certainty - Google Patents

Abstract

The invention provides a DP-NET data link control mechanism with strict time certainty, comprising a time certainty bus polling engine (TCPE) mechanism, a link data additional transmission (LDAT) mechanism and a time definiteness link data memory control (LDMC) mechanism; particularly, a time certainty polling period control table (TCPPCT) is provided to realize strict time certainty polling to each slave station under a given period; the LDAT mechanism is provided to realize the instantaneity of bus management operation on the premise that the strict time certainty polling requirement of each slave station is realized under the given period; the time definiteness link data memory control mechanism is provided to realize the priority level and the certainty of the bus data on the transmission time. Currently, the DP-NET bus with the strict time certainty data link control mechanism can be applied in multiple projects of multiple state-owned big power stations. The practice proves that the DP-NET data link control mechanism with the strict time certainty provided by the invention realizes strict time certainty data access of a main controller to each slave station under the given period, thus achieving the purpose of the invention.

Description

Has the deterministic DP-NET data link of strict time controlling mechanism

Technical field

The present invention relates to a kind of about DP-NET (Rigid Time Decentralized Peripheral Access Net, abbreviation DP-NET) time deterministic data controlling links (the Time Certainty Data Link Control of bus, be called for short TCDLC) mechanism, more particularly, relate to and a kind ofly be used to solve master controller being distributed in on-the-spot process control data from control appliance, realize the data link control protocol of strict time certainty transmission control, belong to fieldbus (Fieldbus) field.

Technical background

Fieldbus has been applied in the industrial automation control field, widely for the industrial automation control data transmission provides more outstanding approach since being born.By fieldbus, be distributed in on-the-spot intelligent measurement and control unit and automation control system and constitute the interconnected communication network, realize the digitlization transmission of field intelligent device process signal amount in the control system.It has improved the control signal transmission performance, be scene, the networking of industrial automation control system, and higher automation provides solid foundation.

Fieldbus is nearly hundred kinds at present, has much become international standard, for example FF, Profibus-DP, CAN-BUS, WorldFIP, InterBus or the like.For the DCS that realizes industrial automation control (Distributed Control System is called for short DCS) system, it is a kind of domestic demand that the field control data are obtained the strict time certainty of transmitting with control signal.But at present in this field, much the fieldbus of having used is inadequate slightly on this problem when running into big data quantity.Typical example, the DCS system supports it is not enough in electricity generation system for electric parameters protection control at present, when its problem just was fieldbus transmission big data quantity, protection control was difficult to accomplish the strict time certainty.For this problem, starting with from the raising data transfer bandwidth of having solves, and starting with from the system applies appropriate design of also having solves.And as one of this problem-solving approach, the DP-NET bus is started with from the data link controlling mechanism, implementation procedure data strict time certainty transmission control.

Fieldbus DP-NET adopts polling mechanism on data link control main body, the poll time is strict definite, and this is consistent with using very wide Profibus-DP substantially.But the outstanding feature of DP-NET polling mechanism is: (1) adds polling mechanism by bus management data and slave station process data are provided, and when realizing the strict time certainty transmission of slave station process data, guarantees the real-time Transmission of bus management data; (2), realize the strict certainty visit under the different polling cycles of different slave stations by slave station strict time certainty polling cycle control table mechanism is provided.Optimized principal and subordinate's polling mechanism by these two means; effectively utilized the high bandwidth of DP-NET physical link; realized that the DP-NET main station controller provides powerful support for for the participation power plant system electric parameters protection control of DCS system provides the strict time certainty transmission control of field data under the big process data amount.

Summary of the invention

The objective of the invention is: research and develop a kind of independent intellectual property right that has, the outstanding DP-NET data link controlling mechanism that solves strict this problem of certainty of time of DCS systematic procedure transfer of data.

1, the invention provides a kind of time deterministic bus data controlling links mechanism TCDLC that has, it comprises:

(1) time certainty bus polling engine (Time Certainty Polling Engine is called for short TCPE) mechanism;

(2) link data additional transmitted (Link Data Appending Transmission is called for short LDAT) mechanism;

(3) time certainty link data internal memory control (Link Data Memory Control is called for short LDMC) mechanism.

Preferably, described DP-NET main website data link control protocol employing application-specific integrated circuit (ASIC) (ApplicationSpecific Integrated Circuit is called for short ASIC) chip DPMaster realizes, perhaps adopts software sDPMaster software to realize.

2, the invention provides deterministic principal and subordinate's polling engine mechanism RTPE of a kind of time, it comprises:

(1) time certainty poll control (Time Certainty Control for Polling is called for short TCCP) mechanism;

(2) data link management control (Data Link Management Control is called for short DLMC) mechanism;

(3) poll is replied control (Polling and Response Control is called for short PRC) mechanism.

3, the invention provides a kind of time certainty cycle polling controlling mechanism, comprising:

(1) cycle poll control (Equal Period Polling Control is called for short EPPC) mechanism such as;

(2) adjustable cycle polling control (Adjustable Polling Period Control is called for short APPC) mechanism.

4, the invention provides a kind of time certainty polling cycle control table (Time Certainty Polling PeriodControl Table is called for short TCPPCT).

5, the invention provides a kind of time certainty link data additional transmitted mechanism LDAT, this mechanism comprises:

(1) to three kinds of classification of bus data: logic control data, emergency data and bus management data;

(2) certainty of three class data is transmitted: the logic control data are done cycle certainty transmission, and emergency data is done preferential certainty transmission, and the bus management data are done the uncertainty additional transmitted;

(3) the additional generting machanism of link data;

(4) the additional mechanism for resolving of link data.

6, the invention provides a kind of certainty link data memory mechanism, comprising:

(1) provide three to send buffer memory: the logic control data send buffer memory, emergency data sends buffer memory and the bus management data send buffer memory;

(2) provide three to receive buffer memory: logic control Data Receiving buffer memory, emergency data receive buffer memory and bus management Data Receiving buffer memory;

(3) slave station separate, stored district group (Slave Independent Memery Area Group is called for short SIMAG) type buffer memory;

(4) slave station stored in association piece group (Slave United Memery Block Group is called for short SUMBG) type buffer memory.

Compared with the prior art, advantage of the present invention comprises the following aspects:

(1) this time deterministic data controlling links mechanism has realized the strict time deterministic data transmission control of DP-NET bus, provides powerful support for for the participation power plant system electric parameters protection control of DCS system provides.

(2) this time deterministic data controlling links mechanism provides principal and subordinate's polling cycle adjustable complete machine system, polling cycle at the different slave stations that are provided with, realize the certainty transmission control of the different polling cycles of many slave stations, thereby reduced bus load, improved the bus bandwidth utilance.

(3) this time deterministic data controlling links mechanism has realized the Dynamic Maintenance function of DP-NET bus links efficiently, by data link additional transmitted mechanism, realizes the real time polling of bus management data.Under the strict time certainty prerequisite that has guaranteed the specified data transmission, satisfied the dynamic fault error correction of bus node, basic function demands such as dynamical system upgrading.

Description of drawings

Fig. 1 represents the deterministic principal and subordinate's polling engine of strict time according to the present invention mechanism;

Fig. 2 represents according to additional data generting machanism of the present invention;

Fig. 3 represents according to additional data mechanism for resolving of the present invention;

Fig. 4 represents according to bus master certainty link data caching mechanism of the present invention;

Fig. 5 represents according to bus master polling cycle control table mechanism of the present invention.

Embodiment

Bus master data link controlling mechanism TCDLC of the present invention is by forming with the lower part:

1) strict time certainty bus polling engine mechanism TCPE;

2) link data additional transmitted controlling mechanism LDAT;

3) time certainty link data internal memory controlling mechanism LDMC.

One, please refer to Fig. 1, TCPE is by forming with the lower part for the deterministic principal and subordinate's polling engine mechanism of strict time of the present invention:

1) be responsible for the TCCP of time certainty poll control: it is by timer (being shown among the figure with P1), time certainty polling cycle control table TCPPCT (being shown among the figure) with P8, and poll pattern change over switch MUX (being shown among the figure with P11) constitutes;

2) be responsible for poll and reply the PRC of control: it is by poll control (being shown among the figure with P4) and reply control (being shown among the figure with P5) formation;

3) be responsible for the DLMC that the bus links management is controlled: it is by orderly movable slave station chain (Orderly List of ActiveSalve, be called for short OLAS) (being shown among the figure) with P2, unordered non-movable slave station chain (Disorderly List of InactiveSalve, be called for short DLIS) (being shown among the figure) with P3, and data link control DLC (being shown among the figure with P6) constitutes.

There is the following course of work in each several part:

1.TCPE the course of work comprises following two:

The establishment process of next the poll slave station under cycle such as a, the realization poll control EPPC pattern:

$\left\{\begin{array}{c}P2:C7\→(C3,D1)---\left(1\right)\\ P11:(C3,\mathrm{MUX}=\mathrm{EPPC})\→C4---\left(2\right)\end{array}\right.$

Subprocess (1), the moving in order slave station chain OLAS that lives determines the process of the slave station that the next one will be polled.After receiving the control signal C7 that data link control DLC link P6 sends, after orderly movable slave station chain P2 determines the next slave station that will be polled of output, prepare out this slave station information D 1 when sending this poll node poll acknowledgement control signal C3, the course of work of certainty poll control start-up time TCCP.

Subprocess (2), realization wait the process of cycle poll control EPPC model selection.It is the APPC pattern that selector switch MUX is set, and this poll node poll acknowledgement control signal C3 through link P11, directly as next node poll acknowledgement control signal C4 output, is started the course of work of inquiry controlling unit P4.

But the establishment process of next the poll slave station under b, the realization adjustment cycle poll control APPC pattern:

$\left\{\begin{array}{c}P2:C7\&RightArrow;(C3,D1)---\left(1\right)\\ P11:(C3,\mathrm{MUX}=\mathrm{APPC})\&RightArrow;C3---\left(2\right)\\ P8:(\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009100836510E0000031.png,H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}2,C3,D1)\&RightArrow;C4---\left(3\right)\end{array}\right.$

Subprocess (1), the moving in order slave station chain of living is determined the process of the slave station that the next one will be polled.After receiving the control signal C7 that data link control DLC link P6 sends, orderly movable slave station chain P2 determines to export the next polled slave station of wanting, prepare out this slave station information D 1 when sending this poll node poll acknowledgement control signal C3, the course of work of certainty poll control start-up time TCCP.

Subprocess (2), but realize adjustment cycle poll control APPC model selection process.It is the APPC pattern that selector switch MUX is set, and link P11 sends this poll node poll acknowledgement control signal C3, starts the poll periodic Control table P8 course of work.

Subprocess (3), the polling cycle control table course of work.After receiving poll node poll acknowledgement control signal C3, polling cycle table P8 reads this slave station information D 1, this slave station is done the judgement whether polling cycle arrives, and the result that will confirm starts the course of work of inquiry controlling unit P4 as next node poll acknowledgement control signal C4 output at last.

2. poll is replied the control PRC course of work and is comprised following two:

A, strict certainty inquiry of deadline control procedure:

$\left\{\begin{array}{c}P4:(C4,D0)\&RightArrow;C8---\left(1\right)\\ P4:(C4,D1)\&RightArrow;(\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}10,D5)---\left(2\right)\\ P4:(C5,D2)\&RightArrow;(\mathrm{<figure-callout\; id="11"\; label="C"\; filenames="H2009100836510E0000011.png"\; state="\{\{state\}\}">C</figure-callout>}11,D5)---\left(3\right)\\ P4:(C8,D3)\&RightArrow;(\mathrm{<figure-callout\; id="11"\; label="C"\; filenames="H2009100836510E0000011.png"\; state="\{\{state\}\}">C</figure-callout>}11,D5)---\left(4\right)\end{array}\right.$

Subprocess (1) is realized the process that polling operation is confirmed.After receiving the next node poll acknowledgement control signal C4 that TCCP sends, inquiry controlling unit P4 reads confirmation D0 and handles, when if there is not next slave station that needs poll in the D0 indication, the P4 feedback redefines the control request signal C8 of next polling message, the course of work of log-on data controlling links DLC link P6.

Subprocess (2), realization are determined the process of the process data inquiry control of slave station.After receiving the next node poll acknowledgement control signal C4 that TCCP sends, inquiry controlling unit P4 reads behind the confirmation D0 and handles, when if D0 indication need be to next slave station poll of confirming, read this slave station information D 1, when being ready to this poll slave station information D 5, the output procedure data C10 that transmits control signal, the certainty internal memory control start-up time LDMC course of work.

Subprocess (3) is realized the process of the inquiry control of unknown slave station.After receiving the definite non-movable slave station polling request control signal C5 of DLC link, inquiry controlling unit P4 reads this non-movable slave station information D 2 and handles, when preparing out this poll slave station information D 5, the output link data are added control signal C11, start the additional course of work that sends controlling unit.

Subprocess (4) is realized the process that bus links management inquiry is controlled.After receiving the definite bus management message polling control request signal C8 of DLC link, inquiry controlling unit P4 reads management inquiry information D 3 and handles, when preparing out this management polling message D5, the output link data are added control signal C11, start the additional course of work that sends controlling unit.

The process of b, deadline definite response control:

P5：(C14，D7)→(C9，D6)

By the additional reception controlling unit P8 of link data additional transmitted LDAT, the link acknowledgement Data Receiving control request signal C14 that sends, triggering is replied controlling unit P5 and is read link acknowledgement data D7, finishes and replys control procedure.The link acknowledgement data D6 that will handle at last does output and prepares, the control request signal of output link management simultaneously C9, the course of work of log-on data controlling links DLC.

3. data link management control DLMC comprises the following course of work:

$\left\{\begin{array}{c}P6:\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009100836510E0000011.png,H2009100836510E0000031.png"\; state="\{\{state\}\}">C</figure-callout>}1\&RightArrow;C7---\left(1\right)\\ P6:C8\&RightArrow;C6---\left(2\right)\\ P6:C8\&RightArrow;(C8,D3)---\left(3\right)\\ P6:(C9,D6)\&RightArrow;(C6,C7,D3)---\left(4\right)\\ P2:(C7,D3)---\left(5\right)\\ P3:(C6,D3)---\left(6\right)\end{array}\right.$

Subprocess (1), realization start the process of definite work of the movable slave station of next poll.After receiving the automatic regular polling control signal C1 that timer P1 sends, P6 is when the movable slave station of next poll of output is determined request msg D3 to data link control DLC link, the C7 that transmits control signal, startup activity slave station chain P2 carry out next definite course of work that needs the movable slave station of poll.

Subprocess (2), realization starts the process of definite work of the non-movable slave station of next poll.Receive inquiry controlling unit P4 feedback redefine polling message control signal C8 after, when not having bus links control poll demand, P6 is when the movable slave station of next poll of output is determined request msg D3 to data link control DLC link, output control signal C6 starts unordered non-slave station chain P3 alive and carries out definite course of work that next needs initialized non-movable slave station.

Subprocess (3) realizes starting the process that bus links is controlled definite work of polling message.Receive poll control P4 feedback redefine polling message signal C8 after, when having the bus management demand, the management data D3 of inquiry is wanted in the preferential output of data link control DLC link P6, send bus management data polling request signal C8 simultaneously, start the poll course of work that inquiry controlling unit P4 carries out bus links management information.

Subprocess (4) is realized the process that data link is safeguarded.After receiving that the link acknowledgement of replying controlling unit P5 transmission is handled control request signal C9, data link control DLC link P6 reads the link acknowledgement data D6 that P5 prepares.According to the link management data of link acknowledgement data D6, finish following data link management subprocess with subprocess (3) the institute inquiry of correspondence:

1) realizes the data link management control procedure.Control inquiry according to the data link management that subprocess (3) is done, with link acknowledgement information, carry out management Control work such as status poll, configuration verification, failure diagnosis, statistic record, link redundancy arbitration, its result is exported with data D3, and send control signal C7, start the slave station maintenance process of orderly movable slave station chain P2.

2) realize definite process that bus is dynamically added operation to slave station, also promptly realize definite process of bus slave station " heat is inserted " control.Non-movable slave station inquiry of bus links and the link acknowledgement situation done according to subprocess (3), after making slave station and doing the judgement of " heat insert " operation, when sending slave station from non-activity chain removal request data D3, the C6 that transmits control signal starts the course of work of unordered dynamic non-activity chain P3.When sending slave station then and add activity chain request msg D3, the C7 that transmits control signal starts the course of work of orderly movable slave station chain P2.

3) realize the definite process of bus, also promptly realize definite process of bus slave station " hot drawing " control the dynamic deletion action of slave station.According to bus links condition managing process and bus links Redundancy Management process, after making the slave station off-line and judging, the output slave station sends the course of work that control signal C7 starts orderly movable slave station chain P2 from activity chain removal request information D 3 time.When the output slave station adds non-movable slave station chain information D3, send the course of work that control signal C6 starts unordered non-activity chain P3 then.

Subprocess (5) is realized the maintenance process of orderly movable slave station chain.After receiving the movable slave station supervisory signal C7 that the bus links management link sends, orderly movable slave station chain link P2 reads the slave station information D 3 that the bus links management link sends.According to the data of D3, the maintenance process of orderly movable slave station chain comprises following subprocess:

1) realizes that slave station adds the process of main website activity chain.If D3 represents slave station and does " heat is inserted " operation that P2 does movable slave station chain node according to slave station polling cycle size and adds operation in order, realizes that slave station adds the process of main website activity chain.

2) realize the process of slave station from main website activity chain deletion.If D3 represents slave station and does " hot drawing " operation that P2 does the orderly deletion action of orderly movable slave station chain node, the process of realization activity slave station deletion.

3) realization activity slave station managing control information maintenance process.If D3 represents the slave station managing control information and upgrades that P2 does the slave station information of being safeguarded upgrading, realization activity slave station managing control information maintenance process.

Subprocess (6) is finished the maintenance process of non-movable slave station chain.After receiving the non-movable slave station supervisory signal C6 that the bus links management link sends, non-movable slave station chain link P3 reads the slave station information D 3 that the bus links management link sends.According to the data of D3, the maintenance process of non-movable slave station chain comprises following subprocess:

1) realizes that slave station adds the process of the non-activity chain of main website.If D3 represents slave station and does " hot drawing " operation that P2 does the chain node with this slave station and adds operation, realizes that slave station adds the process of the non-activity chain of main website.

2) realize the process of slave station from the non-activity chain deletion of main website.If D3 represents slave station and does " heat is inserted " operation that P2 does the orderly deletion action of non-movable slave station chain node, realizes the process of slave station from the non-activity chain deletion of main website.

Two, please refer to Fig. 1 again, certainty link data additional transmitted mechanism LDAT of the present invention is by forming with the lower part:

1) the additional controlling unit (being shown among the figure) that sends of link data with P7

2) the additional controlling unit (being shown among the figure) that receives of link data with P8

There is the following course of work in each several part:

1, the additional transmission control of link data comprises following process:

$\left\{\begin{array}{c}P7:(C13,D8,D9,D10)\&RightArrow;(C22,D14)---\left(1\right)\\ P7:(\mathrm{<figure-callout\; id="11"\; label="C"\; filenames="H2009100836510E0000011.png"\; state="\{\{state\}\}">C</figure-callout>}11,D5)\&RightArrow;(C22,D14)---\left(2\right)\\ P7:(\mathrm{<figure-callout\; id="11"\; label="C"\; filenames="H2009100836510E0000011.png"\; state="\{\{state\}\}">C</figure-callout>}11,C13,D5,D8,D9,D10)\&RightArrow;(C22,D14)---\left(3\right)\end{array}\right.$

Subprocess (1), the additional process that sends of implementation procedure data.Send at LDMC under the additional transmission request signal C13 triggering of preferential controlling unit P18 output, additional sending link P7 reads the highest priority data D8 of P18 control output, and D9, or D10 handle according to the envelope frame of additional data generting machanism implementation procedure data.The additional isl frame D14 that finishes of output exports the signal C22 that transmits control signal simultaneously, starts the course of work of serial data transmitting element SDSTC.

Subprocess (2), the additional process of sending of realization link management polling data.Under the triggering of the additional transmission of link management control data request signal C11, additional sending link P7 reads link management polling data D5, finish the envelope frame of management polling data handles by the additional data generting machanism, the additional isl frame D14 that finishes of output, export the signal C22 that transmits control signal simultaneously, start the course of work of serial data transmitting element SDSTC.

Subprocess (3), the additional process of sending of realization link management data and application data.Send the additional transmission request signal C13 triggering of preferential controlling unit P18 output at LDMC after, additional sending link reads the highest priority data D8 of P18 control output, D9, or D10.If receive the additional request signal C11 that sends of link management data this moment, read link management polling data D5 from data link control DLC link P6 simultaneously, then append to process data by the additional data generting machanism.The additional isl frame D14 that finishes of output at last exports the signal C22 that transmits control signal simultaneously, starts the course of work of serial data transmitting element SDSTC.

2, the additional reception control of link data comprises following process:

$\left\{\begin{array}{c}P7:(C23,D15)\&RightArrow;(C14,D7)---\left(1\right)\\ P7:(C23,D15)\&RightArrow;(C23,\mathrm{<figure-callout\; id="11"\; label="D"\; filenames="H2009100836510E0000011.png"\; state="\{\{state\}\}">D</figure-callout>}11,D12,D13)---\left(2\right)\end{array}\right.$

Subprocess (1), the additional receiving course of link control and management information in the realization reply data.Additional receive the character stream data reception signal C23 that controlling unit P8 receives that SDSTC sends after, receive complete link data frame by data D15 after, the parsing of finishing link control and management information in the reply data receives.Received signal C14 is replied in output at last, and prepares link control and management information D 7 in the output reply data.

Subprocess (2), the additional parsing receiving course of realization answering data.Additional receive the character stream data reception signal C23 that controlling unit P8 receives that SDSTC sends after, receive complete link data frame by data D15 after, finish the parsing that receives answering data in the data and receive.Received signal C14 is replied in output at last, and prepares output answering data D11, D12, or D13.

Three, please refer to Fig. 1 again, certainty link data memory mechanism TCMC of the present invention is by forming with the lower part:

1) sends priority controlling unit (being shown among the figure) with P18;

2) receive priority controlling unit (being shown among the figure) with P19;

3) emergency data sends buffer memory (being shown among the figure with P12);

4) logic control data send buffer memory (being shown among the figure with P13);

5) bus management data send buffer memory (being shown among the figure with P14);

6) emergency data receives buffer memory (being shown among the figure with P15);

7) logic control Data Receiving buffer memory (being shown among the figure) with P16;

8) bus data receives buffer memory (being shown among the figure with P17);

There is the following course of work in each several part:

1, sends priority control and comprise following process

$\left\{\begin{array}{c}P18:\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}10\&RightArrow;(C13,D16,D8)---\left(1\right)\\ P18:\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}10\&RightArrow;(C13,C17,D9)---\left(2\right)\\ P18:\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}10\&RightArrow;(C13,C18,D10)---\left(3\right)\\ P18:\mathrm{<figure-callout\; id="10"\; label="C"\; filenames="H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}10\&RightArrow;(C13,C17,C18,D9,D10)---\left(4\right)\end{array}\right.$

Subprocess (1) is realized the preferential transmission control of emergency data.After the emergency data that priority transmission controlling unit P18 receives sends request signal C10, the output emergency data sends buffer memory P12 and sends enabling signal C16, the additional C13 that transmits control signal of output simultaneously, the additional sending link P7 of triggering reads emergency data D8 and adds transmission.

Subprocess (2) is realized the transmission control of logic control data.Behind the non-emergent data sending request signal C10 that priority transmission controlling unit P18 receives, the output logic control data sends buffer memory P13 and sends enabling signal C17, the additional C13 that transmits control signal of output simultaneously, the additional sending link P7 of triggering reads logic control data D9 and adds transmission.

Subprocess (3) is realized the transmission control of bus management data.Behind the non-emergent data sending request signal C10 that priority transmission controlling unit P18 receives, if there is no logic control data and when existing the bus management data to send, then the output bus management data sends buffer memory P14 and sends enabling signal C18, the additional C13 that transmits control signal of output simultaneously, the additional sending link P7 of triggering reads bus management data D10 and adds transmission.

Subprocess (4) is realized the additional transmission control of logic control and bus management data.Behind the non-emergent data sending request signal C10 that priority transmission controlling unit P18 receives, if when existing logic control data and bus management data to send, then the output logic control data sends buffer memory P13 and sends enabling signal C17 and bus management data transmission buffer memory P14 transmission enabling signal C18, the additional C13 that transmits control signal of output simultaneously, the additional sending link P7 of triggering reads logic control data D9 and bus management data D10 adds transmission.

2, receive priority control and comprise following process

$\left\{\begin{array}{c}P19:C15\&RightArrow;(C19,D11)---\left(1\right)\\ P19:C15\&RightArrow;(C20,D12)---\left(2\right)\\ P19:C15\&RightArrow;(C21,D13)---\left(3\right)\end{array}\right.$

Subprocess (1) is realized the reception control of emergency data.After the emergency data that priority transmission controlling unit P19 receives received request signal C15, the output emergency data received buffer memory P15 and sends enabling signal C19, and the triggering emergency data receives buffer memory P15 and reads emergency data D11.

Subprocess (2) is realized the reception control of logic control data.Behind the logic control Data Receiving request signal C15 that priority transmission controlling unit P19 receives, the output logic control data receives buffer memory P16 and sends enabling signal C20, triggers logic control Data Receiving buffer memory P16 and reads logic control data D12.

Subprocess (3) is realized the reception control of bus management data.Behind the bus management Data Receiving request signal C15 that priority transmission controlling unit P19 receives, the output bus management data receives buffer memory P17 and sends enabling signal C21, triggers bus management Data Receiving buffer memory P17 and reads bus management data D13.

Four, please refer to Fig. 2, link additional data message generting machanism of the present invention comprises with the lower part:

1) additional data generates FIFO (being shown among the figure with P4); This FIFO is by additional data frames head part, routine data part, and additional data is partly formed.

2) the additional generation of link data controlled (being shown among the figure with P1);

The additional data message generates and has following process:

$\left\{\begin{array}{c}P1:(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009100836510E0000011.png,H2009100836510E0000031.png"\; state="\{\{state\}\}">C</figure-callout>}1,\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009100836510E0000031.png,H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}2,D5)\&RightArrow;D8---\left(1\right)\\ P1:(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009100836510E0000011.png,H2009100836510E0000031.png"\; state="\{\{state\}\}">C</figure-callout>}1,\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009100836510E0000031.png,H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}2,D5)\&RightArrow;(C3,C4)---\left(2\right)\\ P2:(C3,D6)\&RightArrow;D9---\left(3\right)\\ P3:(C3,D7)\&RightArrow;D10---\left(4\right)\\ P1:C5---\left(5\right)\end{array}\right.$

Subprocess (1), realization generates the process of link data frame head.According to the polling data that is started, the additional control P1 that sends of link data reads necessary poll train circuit-switched data information D 5, generates corresponding data frame head D8, and writes the additional data frames head part that additional data generates FIFO.

Subprocess (2), the process of decision polling data send mode.The additional control P1 that sends of link data sends under the triggering of control request signal C2 in the process data that log-on data controlling links data send signal C1 and TCMC output, sends routine data copy enabling signal C3 or additional data copy enabling signal C4 respectively.

Subprocess (3), expression generates the process of conventional link data.Under the routine data copy enabling signal C3 that the additional transmission control of link data P1 sends triggers, do cycle certainty transmission according to the logic control data, emergency data is done preferential certainty transmission, bus management data and data link management control data are done the principle of uncertainty additional transmitted, and deterministic data is done the routine data transmission, uncertainty is done the additional principle that sends, reading will be as the data message D6 of routine data poll, as the routine data D9 of correspondence, write the routine data part that additional data generates FIFO.

Subprocess (4), expression generates the process of conventional link data.Under the additional data copy enabling signal C4 that the additional transmission control of link data P1 sends triggers, do cycle certainty transmission according to the logic control data, emergency data is done preferential certainty transmission, bus management data and data link management control data are done the principle of uncertainty additional transmitted, and deterministic data is done the routine data transmission, uncertainty is done the additional principle that sends, reading will be as the data message D7 of additional poll, as the additional data D10 of correspondence, write the additional data part that additional data generates FIFO.

Subprocess (5) starts the transmission control of additional data.Link data is additional to send the control P1 C5 that transmits control signal, and starts the process of transmitting that control additional data also generates data fifo.

Five, please refer to Fig. 3, link additional data packet parsing mechanism of the present invention comprises with the lower part:

1) additional data is resolved FIFO (being shown among the figure with P4); This FIFO is by additional data frames head part, routine data part, and additional data is partly formed.

2) the additional parsing of link data controlled (being shown among the figure with P1).

There is process in the additional data packet parsing:

$\left\{\begin{array}{c}P1:(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009100836510E0000011.png,H2009100836510E0000031.png"\; state="\{\{state\}\}">C</figure-callout>}1,D8)\&RightArrow;(\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009100836510E0000031.png,H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}2,C3)---\left(1\right)\\ P1:(\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="H2009100836510E0000011.png,H2009100836510E0000031.png"\; state="\{\{state\}\}">C</figure-callout>}1,D8)\&RightArrow;(C4,D5)---\left(2\right)\\ P2:(\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="H2009100836510E0000031.png,H2009100836510E0000041.png"\; state="\{\{state\}\}">C</figure-callout>}2,D9)\&RightArrow;D6---\left(3\right)\\ P3:(C3,D10)\&RightArrow;D7---\left(4\right)\\ P1:C5---\left(5\right)\end{array}\right.$

Subprocess (1), additional data is resolved decision process.The additional control P1 that resolves of link data received signal C1 trigger link data finishes the reception of link additional data D8 and resolves.Parsing according to D8 produces routine data copy control signal C2 or additional data copy control signal C3.

Subprocess (2), data link management control data resolving.The additional control P1 that resolves of link data received signal C1 trigger link data finishes the reception of link additional data D8 and resolves, and when parsing link management control data D5, sends and replys enabling signal C4 to replying controlling unit.

Subprocess (3), routine data resolving.Routine data is resolved copy link P2, under the triggering of routine data copy control signal C2, finishes the resolving of routine data, and to TCMC link output routine data D6.

Subprocess (4), additional data resolving.Additional data is resolved copy link P3, under the triggering of additional data copy control signal C3, finishes the resolving of additional data, and to TCMC link output additional data D7.

Subprocess (5), the receiving course of startup resolution data.The additional control P1 that resolves of link data after finishing data parsing control, sends resolution data received signal C5 to SSMS.

Six, please refer to Fig. 4, slave station separate, stored of the present invention district group SIMAG type buffer memory is achieved as follows:

1) SIMAG type buffer memory is made of the separate, stored district group corresponding to slave station;

2) each group separate, stored district is corresponding to the formation of a slave station data linear list;

3) each linear list unit in the linear list formation of each group unit, the link data message of a corresponding slave station;

4) the group number of SIMAG type buffer memory, linear list queue length, and linear list length is configurable;

5) logical data sends buffer memory and the realization of bus management data transmission buffer memory employing SIMAG type buffer memory.

Seven, please refer to Fig. 4 again, slave station stored in association piece group SUMBG type buffer memory of the present invention is achieved as follows:

1) SUMBG type buffer memory is made of multistage slave station stored in association piece group;

2) each slave station stored in association piece is that the unit is formed by the linear list corresponding to each slave station;

3) the linear list unit of each slave station stored in association piece is corresponding to the link data message of a slave station;

4) the piece number of SUMBG type buffer memory, linear list length are configurable;

5), provide the memory block that has up-to-date link data data all the time for data cached the reading of SUMBG;

6), provide empty memory block all the time for data cached the writing of SUMBG.

7) logic control The data SUMBG type buffer memory is realized.

Eight, please refer to Fig. 5, time certainty polling cycle control table TCPPCT of the present invention is achieved as follows:

1) time certainty polling cycle control table TCPPCT is a bivariate table about slave station cycle and tributary address;

2) row of each in the table is corresponding to a value in the orderly periodic linear table of the cycle formation of whole slave stations;

3) each unit comprises tributary address and two information of slave station poll permission flag in the table;

4) each slave station is corresponding to unit in the bivariate table;

5) has identical poll priority with the slave station in the delegation in the table;

6) polling cycle is more little in the table, and the poll priority that has is high more.

The operation of polling cycle control table TCPPCT comprises with the lower part:

1) slave station poll permission flag refresh process in the periodic Control table;

Under timing signal that timer sends drives, according to calculating the over and done with time whether in the wait list after the periodic quantity of certain delegation, with the poll permission flag set of all slave stations of the slave station of this row correspondence.

2) periodic Control table slave station poll permission flag access process;

Find corresponding unit by slave station polling cycle and address, the value of read access sign indicates zero clearing after reading.

3) the periodic Control table unit adds process;

According to the access cycle of slave station, find in the table the position that should add, do the bivariate table unit and add operation.

4) periodic Control table unit delete procedure;

According to the address of slave station, the operation of bivariate table element deletion is done in the position of finding in the table to be answered.

Nine, of the present invention provide etc. cycle poll control EPPC pattern realization principle as follows:

1) each polling time slot equates;

2) the next slave station in the movable slave station chain of each time slot poll;

3) in movable slave station chain, keep an empty slave node;

4) poll emergency data when empty node poll;

5) the support activities slave station dynamically adds and deletion.

Ten, of the present invention provide etc. cycle poll control APPC pattern realization principle as follows:

1) each polling time slot equates;

2) each movable slave station can be set to the polling cycle of polling time slot integral multiple arbitrarily;

3) all slave stations that polling cycle is not set are endowed, and divide equally deduction and fall by all the total time slot of remaining poll after the polling time slot that the polling cycle slave station occupied has been set, and be scaled the polling cycle value after the polling cycle;

4) each time slot carries out poll to limit priority slave station among the polling cycle control table TCPPCT;

5) keep intrinsic polling time slot and send use as emergency data;

6) the support activities slave station dynamically adds and during deletion, to the polling cycle value of polling cycle slave station is not set, and on principle 3) adjust automatically;

7) the support activities slave station dynamically adds and during deletion, to the renewal of polling cycle table TCPPCT.

11, the strict time that realizes by above mechanism is determined distributed peripheral access fieldbus, and the typical technology index of realization is done as follows:

1) adopting bus baud rate typical rate is 5Mbps, maximum polling data frame length 200B, and minimum-poll is spaced apart 500us, and effective procedure data transfer bandwidth maximum can reach 4Mbps, minimum control cycle Da Keda 1ms;

2) if adopting slave station maximum node number is 127, then maximum control cycle is no more than 64ms;

3) there are this relation in slave station polling cycle and slave station number: all slave station access frequency sums satisfy following relation:

1/T ₁* N ₁+ 1/T ₂* N ₂+ ... 1/T _k* N _k≤ 2x10 ³-C. (C is the bus management constant, less than 100) satisfies this condition, will realize the strict time certainty visit of main website to slave station.

Claims (4)

1. one kind has the deterministic data link controlling mechanism of strict time, and content comprises:

(1) time certainty bus polling engine TCPE mechanism specifically comprises: time certainty poll control TCCP mechanism; Data link management control DLMC mechanism; Poll is replied control PRC mechanism;

(2) link data additional transmitted LDAT mechanism;

(3) time certainty link data internal memory control LDMC mechanism.

It is characterized in that:

In content (1), poll is provided by the time certainty cycle polling controlling mechanism of control PRC mechanism by providing, and realizes the certainty poll of bus slave station.

Be also that in content (2) link data additional transmitted LDAT mechanism realizes the additional transmitted of bus management data on the slave station process data by link data additional transmitted mechanism is provided.

Also be in content (3) logic control data, emergency data, bus management metadata cache mechanism that time certainty link data internal memory control LDMC mechanism provides, the bus data priority control of realization.

2. a kind of deterministic DP-NET data link control of strict time RTDLC mechanism that has according to claim 1 is characterized in that: in middle content (1), specifically also comprise a lower part:

(1) creates a kind of time certainty polling cycle control table TCPPCT;

(2) realize adjustable cycle polling control APPC mechanism by TCPPCT.

3. a kind of deterministic DP-NET data link control of strict time RTDLC mechanism that has according to claim 1 is characterized in that: in middle content (2), specifically also comprise a lower part:

(1) to three kinds of classification of bus data: logic control data, emergency data and bus management data;

(2) certainty of three class data is transmitted: the logic control data are done cycle certainty transmission, and emergency data is done preferential certainty transmission, and the bus management data are done the uncertainty additional transmitted;

(3) the additional generting machanism of link data;

(4) the additional mechanism for resolving of link data.

4. a kind of deterministic DP-NET data link control of strict time RTDLC mechanism that has according to claim 1 is characterized in that: in middle content (3), specifically also comprise a lower part:

(1) provide three independently to send buffer memory: the logic control data send buffer memory, emergency data sends buffer memory and the bus management data send buffer memory;

(2) provide three independently to receive buffer memory: logic control Data Receiving buffer memory, emergency data receive buffer memory, reach bus management Data Receiving buffer memory;

(3) slave station separate, stored district group SIMAG type buffer memory, and by its logic control data that constitute transmission buffer memory;

(4) slave station stored in association piece group SUMBG type buffer memory, and by its logic control Data Receiving buffer memory that constitutes.

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