CN109976272A - Stringent access and the distributed peripheral bus system and its control method in sampling time - Google Patents
Stringent access and the distributed peripheral bus system and its control method in sampling time Download PDFInfo
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Abstract
The invention discloses a kind of stringent access and the distributed peripheral bus system and its control method in sampling time, which includes a monobus main website and at least one bus slave station；The physical layer of its system uses low-voltage differential signal (LVDS) bussing technique of dual redundant；Its data link layer realizes that the FASTDP-BUS protocol integrated test system chip is realized using specific integrated circuit (ASIC) mode using the field programmable gate array (FPGA) or FASTDP-BUS protocol integrated test system chip for realizing FASTDP-BUS link protocol；Its application layer uses FASTDP-BUS application layer protocol specification, and FPGA or FASTDP-BUS is controlled the CPU realization that chip is mapped to internal address space by industry standard architecture (ISA) bus.Using the present invention, the data access time certainty based on bus can be effectively promoted, the time determinability that analog quantity samples, while simplifying bus data mechanism.
Description
Technical field
The present invention relates to Fieldbus Intelligent control technologies, more particularly to a kind of stringent access and the distribution in sampling time
Peripheral bus system and its control method.
Background technique
The interconnections such as sensor, measurement and control unit and automatic control system of the fieldbus by distribution on site, are realized defeated
Enter the intercommunication of output (IO) data, provides strong support for information transmission, the information control of industrial automation control system.
Up to hundred kinds of the type of fieldbus, much have become international standard, such as: PROFIBUS, controller LAN (CAN,
Controller Area Network), Device Net, INTERBUS, foundation fieldbus (FF, Foudation
Field Bus) etc., respectively play an important role in the controls.
PROFIBUS bus is rotated using main website token time piece, and high-priority data considers multiple clips transmission, and
Principal and subordinate's polling mechanism, transmission speed highest 12Mbps, has standard fieldbus function, is mainly used for including process control etc.
Industrial control field, but cannot be used for electric system complexity protective relaying device at present；The more main website non-destructives of CAN bus are sent
Conflict arbitration mechanism, maximum speed 1Mbps within message 8B byte and other standards fieldbus function, are mainly used for vapour
The control of vehicle electronic equipment.INTERBUS bus uses the annular forwarding mechanism of main website control, and transmission data length is no more than 512
Position, transmission speed are not higher than 10Mbps, are mainly used for industrial production line；Other buses also have reapective features, here not
It repeats again.
Recently as DCS, PLC, PAC etc. control equipment application field constantly extend, such as expand to electric system,
The fields such as relay protection, data transmission are also accordingly extended.On the one hand, Current bus cannot fully meet this
Data transmission capabilities required by a little fields；On the other hand, as electronic communication develops, market emerges numerous Novel electrics
Son and communication device, current field bus technique seem that some backwardnesss are in urgent need to be improved again.Current field bus technique is urgently
It is promoted and is solved from the following aspect:
1) transmission speed has to be hoisted.Complex industrial produces the fast automatic controls such as control, high-voltage relay protection, emergency brake
Device processed needs to realize the data sampling speed of microsecond (μ s) rank of big quantity I O, requires plate step velocity all in 100Mbps
Left and right, it is even higher.The fieldbus speed of mainstream at present, especially plate grade fieldbus speed is very low, Profibus-DP generation
One of table field maximum speed, but its speed is not higher than 12Mbps.
2) transmission time certainty has to be hoisted.The industrial production control of complicated high speed, power high voltage relay protection etc. are fast
Fast automatic device, under the requirement of comparable band point ability, it is desirable that I/O data synchronized sampling, error showed at present less than 1 μ seconds
Field bus is unable to reach the precision, is limited in the application in these fields.Involved data class is various simultaneously, such as real-time IO number
According to, emergent control data, history curve data, history event data, recorder data, IO management data, diagnostic data etc., pass
Defeated time determinability, two priority classes are all different, and field bus technique still has very big deficiency at present.
3) data delivery mechanism needs to be simplified.Current live bus is in transmission data classification, the right to use of universal serial bus
There is also deficiencies on the interaction mechanism of arbitration and data；FF bus is using the transmission token arbitration bus right to use, PROFIBUS
It is rotated using main website token time piece, high-priority data considers multiple clips transmission and principal and subordinate's polling mechanism and CAN
The more control domain fields of bus and short data frame pattern etc. cause bus scheduling complicated, and bus bandwidth availability reduces.
Summary of the invention
In view of this, the main purpose of the present invention is to provide the distribution periphery of a kind of stringent access and sampling time is total
Linear system system and control method, effectively promoting data transmission bauds, promoting the certainty of transmission time and simplifying data transmitting machine
System.
In order to achieve the above objectives, the technical scheme of the present invention is realized as follows:
It is a kind of it is stringent access and the sampling time distributed peripheral bus system, comprising:
One monobus main website and at least one bus slave station；The physical layer of its system uses the low voltage difference of dual redundant
Signal LVDS bussing technique；Its data link layer is using the on-site programmable gate array FPGA for realizing FASTDP-BUS link protocol
Or FASTDP-BUS protocol integrated test system chip is realized, the FASTDP-BUS protocol integrated test system chip uses application-specific integrated circuit ASIC side
Formula is realized；Its application layer uses FASTDP-BUS application layer data specification, and will by industry standard architecture isa bus
The CPU that FPGA or FASTDP-BUS protocol integrated test system chip is mapped to internal address space is realized.
Wherein, the data link layer, data link frame are divided into containing the link layer for applying data APP DATA field
Data frame and without application data APP DATA field link layer data frame；Wherein, described containing using data APP DATA's
Link layer data frame includes application layer data；The link layer data frame without application data APP DATA includes indication field
The LLC DATA field of length；The application layer data, including following field: sending in the application layer data message in caching and wrap
Whole length LE3 fields of Addr containing Dest, DUn, FCS field, destination address Dest Addr field, APP DATA field with
And and verification FCS field；The APP DATA field includes multiple data field DU；Each DU length is 1 byte；
The link layer data frame containing application data APP DATA, including following field:
Frame synchronization head Sync Head field, destination address Dest Addr field, source address Src Addr field, link layer
Transmission channel CMD field, transmission frame control byte fc field, the length LE2 for having isl frame APP DATA field using data
Warning Mark field, APP DATA field, cyclic redundancy check code crc field and frame synchronization tail Sync Tail field；
The link layer data frame without application data APP DATA, including following field: frame synchronization head Sync Head word
Section, the control of destination address Dest Addr field, source address Src Addr field, link layer transfer channel C MD field, transmission frame
Byte fc field is represented without the application isl frame LE1 Warning Mark field of data, the length LLC DATA field of field, circulation
Redundancy check code crc field and frame synchronization tail Sync Tail field.
The application-layer data transmission channel of the distribution peripheral bus is included in isl frame head setting mark application layer
The FC control field in channel realizes the mark in the channel URG, the channel NORM, the channel WAVE, the channel MNG；Wherein:
The channel NORM, is used for transmission the channel of overlayable distributed I/O slave station real time data, the data include can cover,
The sampling input data such as AI, the DI of situations such as loss can be interrupted；And the outputs control such as cpu cycle property DO, AO for persistently exporting
Data；FASTDP-BUS bus is that each distributed I/O slave station in the channel is arranged independent reception caching, sends caching, structure
At the subchannel in the channel NORM；
The channel URG is used for transmission the channel of the emergency operation data of the distributed I/O for the transmission that can jump the queue；FASTDP-BUS is total
Line is that a common reception caching and a common reception is only arranged in the channel, and the caching is by all distributed I/O slave stations
Emergency data share；
The channel WAVE is used for transmission the channel of the data of the value of not overlayable distributed I O point, which includes can not
The data of the AI point of situations, DI point value, the SOE data of DI and the EVENT data etc. such as to cover, lose；FASTDP-BUS is
A common reception caching is only arranged in the channel, and the caching is shared by the emergency data of all distributed I/O slave stations；
The channel MNG, is used for transmission the channel of distributed I/O slave station configuration management data, which includes equipment self-described letter
The inquiry of the data such as breath, IO slave station operating parameter and configuration order etc.；All distributed I/O slave stations share the channel, only setting one
A common reception caching and a common reception caching are shared
Its distributed I/O slave station real-time Data Transmission channel, specifically:
The bus is that an independent real-time NORM data channel is arranged in each IO slave station, and sets according to application layer
Access cycle obtain bus access power；Each described corresponding channel of IO slave station is that a son of the channel NORM classification is logical
Road.
The link data transfer channel of its data link layer, is divided into: by the pair channel, synchronous of link layer creation and management
New tunnel, diagnosis channel are looked into channel；The link layer data channel is not provided with transmitting-receiving caching, direct by the data link layer
Processing；Wherein:
Pair channel is used for transmission the channel to the clock synchronization data of distributed I/O, and the period by setting is activating the channel
It sets time；
Synchronizing channel is used for transmission the channel of the synchronized sampling order to distributed I/O, according to the synchronous calibration of setting week
Phase activates the channel, realizes sampling step sequence calibration；
New tunnel is looked into, the channel of the distributed I/O querying command of new access bus is used for transmission；During bus free, press
The channel is activated according to new access system IO slave station polling cycle, the distributed I/O newly run in FASTDP-BUS bus is looked into
It askes and initializes；
Channel is diagnosed, the channel that link layer is directed to Diagnosis of Links order is used for transmission, according to the interval between diagnosis of setting, activation
Realize diagnosis in the channel.
Each channel of the bus carries out bus access, the channel access ready list according to channel access ready list mechanism
For two-dimensional structure, it is made of the corresponding row unit of corresponding row access cycle and channel；Controlled including fixed priority channel,
The control of access time uncertainty channel, the control of NORM and IO slave station channel, further include period ready flag refresh control time slot
Rotate ready flag control.
Its channel access time determinability criterion, is divided into: when IO slave station channel period is not present in ready list, then default is adopted
With equal-opportunity sequential access mechanism；When configuring IO slave station channel period in ready list, then ready list prioritization of access is used
Controlling mechanism.
Its channel access priority arbitration mechanism are as follows: by the ready flag position of channel access ready list set, realize logical
Road priority arbitration.
Its Channel Exchange controlling mechanism are as follows: after the channel obtains the bus right to use, in defined switching time slot,
In the transmission of uplink and downlink data, by channel address, attribute and channel data, with the destination address of link data frame,
FC control domain and data field mutually map, and realize the data exchange of main website and slave station transmission data between corresponding channel.
It is a kind of it is stringent access and the sampling time distributed peripheral bus system implementation method, comprising:
One monobus main website and at least one bus slave station are set；
The physical layer of the bus system is set to use the low-voltage differential signal LVDS bussing technique of dual redundant；
Make the data link layer of the bus system using the field programmable gate array for realizing FASTDP-BUS link protocol
FPGA or FASTDP-BUS protocol integrated test system chip realizes that the FASTDP-BUS protocol integrated test system chip uses specific integrated circuit
ASIC mode is realized；
Make the application layer of the bus system using FASTDP-BUS application layer data specification, and passes through Industry Standard Architecture knot
Structure isa bus realizes the CPU that FPGA or FASTDP-BUS protocol integrated test system chip is mapped to internal address space.
Stringent access of the invention and the distributed peripheral bus system and its control method in sampling time, compare existing skill
Art has the following beneficial effects:
1) FASTDP-BUS bus data transfer speed has obtained very big promotion.FASTDP-BUS bus using FPGA or
The hardware circuits such as ASIC are increased to 1~20 microsecond for time slot is accessed, and are increased to fieldbus speed using LVDS technology
100Mbps is, it can be achieved that 1 Microsecond grade strict time certainty (Firm Real-Time).The most high speed of remote super-P ROFIBUS bus
Spend 12Mbps, CAN bus H1 grades of 1Mbps, FF bus of fieldbus 31.25Kbps.It is high-speed field bus in electric power
The application in empty field is protected to provide the foundation Deng other.
2) FASTDP-BUS bus realizes the stringent certainty in access and sampling time.It is different from PROFIBUS bus
The just coarse access control mechanisms of two grades of priority, token time piece rotation mechanism, the message based priority of FF bus
Control, the data exchange ways of token mode, the conflict of Ethernet uncertain mechanism etc., FASTDP-BUS caused by making a concession
The priority of sequential access mechanism and channel access ready list mechanism according to data that has equal opportunities of bus use default, reality
The strict time certainty of channel access and IO slave station controlling of sampling is showed.To be live total now in electric relay protection, urgent
Application in the Key Controls such as control system, the control of safety level nuclear power, provides key support.
3) FASTDP-BUS bus realizes efficient data transmission mechanism.FASTDP-BUS bus is to data root in bus
The features such as according to importance, time determinability, provides a kind of comprehensive channel classification；And access ready list machine is devised to channel
System；It is efficient to realize that data exchange biography in master-salve station interchannel using Channel Exchange mechanism under priority arbitration mechanism control
It is defeated；It is especially promptly multiplexed mechanism, idle multiplexing mechanism, saves the token passing process of FF bus waste bus bandwidth, overcomes
The transmission inefficiencies of the poll acknowledgement mechanism of PROFIBUS bus；Meanwhile FASTDP-BUS bus provides random data biography
Defeated channel realizes the big datas such as Wave data, historical data, file data, utilizes the transmission of idle bus bandwidth；Therefore
FASTDP-BUS bus is deterministic simultaneously in the strict time for realizing IO slave station acquisition control, supports fieldbus increasingly
More integrated data transmission demands.
Detailed description of the invention
Fig. 1 strictly accesses for the embodiment of the present invention and the distributed peripheral bus system schematic in sampling time；
Fig. 2 is the data link frame format schematic diagram of FASTDP-BUS of embodiment of the present invention bus；
Fig. 3 is the application-layer data transmission access diagram of FASTDP-BUS of embodiment of the present invention bus；
Fig. 4 is the bus distributed IO slave station real-time Data Transmission access diagram of FASTDP-BUS of the embodiment of the present invention；
Fig. 5 is FASTDP-BUS of embodiment of the present invention bus links layer data transmission channel schematic diagram；
Fig. 6 is that FASTDP-BUS of embodiment of the present invention bus run accesses ready list schematic diagram；
Fig. 7 is that FASTDP-BUS of embodiment of the present invention bus master channel downlink exchanges control schematic diagram；
Fig. 8 is that FASTDP-BUS of embodiment of the present invention bus master channel uplink exchanges control schematic diagram；
Fig. 9 is that FASTDP-BUS of embodiment of the present invention bus slave station channel uplink exchanges control schematic diagram.
Specific embodiment
With reference to the accompanying drawing and the embodiment of the present invention the present invention is described in further detail.
Fig. 1 strictly accesses for the embodiment of the present invention and the distributed peripheral bus system schematic in sampling time.
As shown in Figure 1, the stringent access and the distributed peripheral bus system in sampling time, i.e.,
FASTDP-BUS bus system comprising a monobus main website and one or more bus slave stations.Its total linear system
The physical layer of system uses low-voltage differential signal (LVDS) bussing technique of dual redundant, and message transmission rate is up to 100Mbps；Its
Data link layer is using the field programmable gate array (FPGA) or FASTDP-BUS agreement for realizing FASTDP-BUS link protocol
It controls chip to realize, which is realized using specific integrated circuit (ASIC) mode；Its application layer uses FASTDP-
BUS application layer data specification, and by industry standard architecture (ISA) bus by FPGA or
The CPU that FASTDP-BUS control chip is mapped to internal address space is realized.
Fig. 2 is the data link frame format schematic diagram of FASTDP-BUS of embodiment of the present invention bus.
As shown in Fig. 2, meaning representated by each field is as follows in the data link frame format of the FASTDP-BUS bus:
Sync Head: frame synchronization head；
Sync Tail: frame synchronization tail；
Dest Addr: destination address；
Src Addr: source address；
FC: transmission frame control byte；
CMD: link layer transfer channel；
LE1: the isl frame without application data is represented；
LLC DATA: the length of field；
LE2: there is the length of the isl frame APP DATA field using data；
LE3: whole length in the application layer data message in caching comprising Dest Addr, DUn, FCS field are sent；
DU: data field is completely filled up to the data field position of link layer by application layer CMD field and DATA data；
FCS: and verification, be application layer data LE field after, before FCS, 8 of all application data fields are cumulative
With；When doing isl frame packing, which, which will lose, be may be not present；
CRC: cyclic redundancy check code word section.
Fig. 3 is the application-layer data transmission access diagram of FASTDP-BUS of embodiment of the present invention bus.
As shown in figure 3, in the application-layer data transmission channel of the FASTDP-BUS bus, the application layer data refers to
The data or order that terminate in application layer are transmitted since application level function generates.On isl frame head, mark application layer channel is set
FC control field, realize the channel URG, the channel NORM, the channel WAVE, the channel MNG mark.Wherein:
The channel-NORM, is used for transmission the channel of overlayable distributed I/O slave station real time data, which includes that can cover
Lid can be interrupted AI, the DI of situations etc. such as loss sampling input data；And DO, AO output control that cpu cycle property persistently exports
Data；FASTDP-BUS bus is that each distributed I/O slave station in the channel is arranged independent reception caching, sends caching, structure
At the subchannel in the channel NORM.
The channel-URG is used for transmission the channel of the emergency operation data of the distributed I/O for the transmission that can jump the queue；FASTDP-BUS
Bus is that the channel is only arranged common reception caching and a common reception, and the caching by all distributed I/Os from
The emergency data stood is shared.
The channel-WAVE is used for transmission the channel of the data of the value of not overlayable distributed I O point, which includes can not
The data of the AI point of situations, DI point value, the SOE data of DI and the EVENT data etc. such as to cover, lose；FASTDP-BUS is
A common reception caching is only arranged in the channel, and the caching is shared by the emergency data of all distributed I/O slave stations.
The channel-MNG, is used for transmission the channel of distributed I/O slave station configuration management data, which includes equipment self-described
The inquiry of the data such as information, IO slave station operating parameter and configuration order etc.；All distributed I/O slave stations share the channel, are only arranged
A pair of of common reception caching is cached with a common reception.
Fig. 4 is the real-time NORM data transmission channel signal of the bus distributed IO slave station of FASTDP-BUS of the embodiment of the present invention
Figure.
As shown in figure 4, the FASTDP-BUS bus is that each IO slave station one independent real-time NORM data of setting are logical
Road, and bus access power is obtained according to the access cycle of application layer setting.Each corresponding channel of IO slave station is the channel NORM
A subchannel.Wherein:
Each IO slave station possesses the real-time NORM data uplink caching of oneself independent IO and down buffer storage；
For the real time data of each IO slave station when exchanging in bus, FC control field is that the mark channel NORM carries out；
The real-time NORM data of all IO slave stations itself constitute the whole of NORM channel data；
The real-time NORM data transmit-receive caching that all IO slave stations independently possess, constitutes the whole of the channel NORM caching；
The real-time NORM data transmission channel that all IO slave stations independently possess constitutes the whole in the channel NORM.
Fig. 5 is FASTDP-BUS of embodiment of the present invention bus links layer link data transfer access diagram.
As shown in figure 5, the FASTDP-BUS bus links layer data, refers to and transmits or service because link layer functionality generates
Terminate in the data or order of link layer.The FC on isl frame head is all reset about application layer data channel control bit, to identify
Link layer data channel, specific channel, which is distinguished, to be identified pair channel, synchronizing channel by link layer order, looks into new tunnel, diagnosis
Channel.Link layer data channel is not provided with transmitting-receiving caching, is directly handled by FASTDP-BUS link layer.Wherein:
Pair channel: the channel to the clock synchronization data of distributed I/O is transmitted, activates the channel in the whole second by the period of setting
It sets time；
Synchronizing channel: transmitting the channel to the synchronized sampling order of distributed I/O, according to the synchronous calibration period of setting,
The channel is activated, realizes sampling step sequence calibration；
Look into new tunnel: the channel of the distributed I/O querying command of the new access bus of transmission；During bus free, according to
New access system IO slave station polling cycle activates the channel, inquires the distributed I/O newly run in FASTDP-BUS bus
And initialization；
Diagnose channel: transmitting link layer is activated for the channel of the orders such as Diagnosis of Links according to the interval between diagnosis of setting
Realize diagnosis in the channel.
Fig. 6 is that FASTDP-BUS of embodiment of the present invention bus run accesses ready list schematic diagram.
As shown in fig. 6, the case where FASTDP-BUS bus run access ready list, is as follows:
1) two-dimensional structure of ready list:
Ready list is a bivariate table, is made of the corresponding row unit of corresponding row access cycle and channel；It is specifically divided into
Fixed priority channel, NORM and IO slave station channel and time uncertainty channel three parts；
The every a line lead-in section of ready list stores unique periodic quantity corresponding with the row；It is special: emergency access and random
Property the corresponding period field value of data channel be 0；
, can be containing maximum 127 channel units after the every a line period field of ready list, each location contents is logical containing this
Road ID and ready flag；
The channel unit of the every a line of ready list, ascending by channel ID number, in the row, continuous arrangement is deposited from left to right
Storage.
2) the fixed priority channel part of ready list:
Fixed priority channel part occupies the first three rows of ready list, and each row major grade immobilizes, channel access
Time strictly determines；
The fixation of ready list the first row is occupied alone by synchronizing channel；Its period determines by sample-synchronous register value, just
Thread mark is by period ready flag refresh operation set (mark=1)；
The fixation of the second row of ready list is occupied alone by emergency access, and period 0, ready flag position is sent out by emergency data
It send and requests set (mark=1), and reset (mark=0) after emergency data sends caching as sky；
The fixation of ready list the third line is occupied alone by pair channel, and the period is set by clock synchronization period register value, just
Thread mark is by period ready flag refresh operation set (mark=1).
3) the access time uncertainty channel part of ready list:
Time uncertainty channel part comes last two row of ready list, is accounted for using bus certainty time access path
With the free timeslot except time slot, the bus access in limitation sexual cycle or randomness time slot rotation mechanism is carried out, affiliated channel is visited
Ask that the time has uncertainty；
Ready list row second from the bottom is restricted data cycle channel, fixed to be occupied by looking into new tunnel and diagnosis channel,
Period is set by link management period register, and ready flag is controlled by period ready flag refresh operation, access time
Point is limited by bus free opportunity；
Ready list row last is random data channel, by the channel MNG, the whole channel the WAVE unity of possession, week
Phase is 0, rotates access bus using free timeslot, ready flag operates control by time slot rotation ready flag；
Random data channel row is occupied except first unit is fixed by the channel MNG, and other channels WAVE are by application layer
Dynamic configuration；The each channel WVAE ID corresponds to the ID for an IO slave station for needing WAVE data to transmit.
4) NORM the and IO slave station channel part of ready list:
- NORM and IO slave station channel occupy the row in ready list except first three rows and rear two row, and channel access needs are pressed
It is strictly determined according to the time；
The access cycle of all unduplicated IO slave stations is arrived into big arranged in sequence from childhood, respectively as row period field, certainly
It is upper and under the corresponding every a line of the generation part ready list；
By the IO slave station in the same period, according to channel ID size, Coutinuous store from left to right is corresponding in the period
In row.
5) period ready flag refresh operation:
Ready list every 1 microsecond (μ s), judge and by table each reach the setting period, and the period be not 0 it is logical
The ready flag set (mark=1) in road；
It is immediately clear by ready flag after the ready path access bus of periodic channel (i.e. the period is not 0) terminates
Zero (mark=0)；
6) time slot rotation ready flag operation
Without set (mark=1) in ready list, random data channel obtains a time slot rotation operation；
After current channel bus access time slot, by removing (mark=0) this channel ready mark, and will be tight
The operation of the ready flag set (mark=1) of adjacent next channel unit, completes an idle bus time slot rotation；
To first MNG channel unit of random data channel row, ready flag position be initialized as set (mark=
1), time slot rotation is forced since MNG channel unit.
As shown in fig. 6, being FASTDP-BUS channel access priority arbitration mechanism.All data of FASTDP-BUS bus
It all needs to realize bus access by sharing unique physical channel, therefore according to different data feature, each data channel needs are pressed
The access right of bus is obtained according to different priorities.
FASTDP-BUS bus realizes channel priorities arbitration by the ready flag position of channel access ready list set,
Specific arbitration rules are as follows:
It provides in ready list, the channel of any ready flag set (mark=1), bus access priority is above not
The channel of set；
It provides in ready list, the channel of highest priority, preferential exclusive bus access power；
It provides in ready list, if whole rows and channel ready flag set, priority is passed line by line as line number increases
Subtract；The first row, i.e. synchronizing channel have highest bus access priority；And last line, i.e. random data channel, only
Minimum bus access priority；
Ready list is provided with channels all in a line, channel access priority is equal；Channel ID value is small because arranging in the line
Preceding units and first obtain bus access priority.
It is the explanation to FASTDP-BUS channel access time determinability criterion below.
Channel bus accesses time slot: from main website by main website tunnel data transport to slave station, receiving slave station port number to main website
According to cut-off, the time experienced is a switching time slot；Switching time slot fixation is limited to 19 microseconds (μ s), two time slot gaps
Limit 1 microsecond (μ s)；
IO slave station channel period is not present in ready list, by default using the sequential access mechanism that has equal opportunities, at this time sternly
Lattice certainty criterion are as follows:
Wherein, Δ T is maximum time slot, and T is whole channel access periods, and N is total number of channels, TctrlIt is the control period.
Meet under this condition, channel access time and IO slave station controlling of sampling time, is with all channels successively sequence
Accessing a spent time is the period, strictly determined.Citing: maximum time slot is 20 microseconds, and 127 slave stations are total to time-consuming T and are
2.54 milliseconds, the control period needs to be greater than 5.08 milliseconds, therefore the access time in each channel, the controlling of sampling of every IO slave station
Time strictly determines；
If configuring IO slave station channel period in ready list, controlled using ready list prioritization of access, at this time strict time
Certainty criterion are as follows:
Wherein, Δ T is maximum time slot, and Ti is that stringent time determinability channel period N is strict time certainty channel
Sum, C are time slot constants.
Time slot constant C is used for the certain time slot reserved to access time uncertainty channel, to meet random data visit
Ask demand；The sum of the access frequency in whole access time strictly determined channels, less than the bus slots after deduction time slot constant
Bandwidth, then obtaining whole requirements for access at these channel periods least common multiple moment.For example, C is equal to 1000, leave for non-true
Qualitative channel at least 1000 time slots, as long as therefore meet: the sum of access frequency of all cycle channels is less than 499000, bus
Upper channel access time and IO slave station acquisition control time realize the determination of time stringency from high to low according to priority
Property.
Fig. 7 is that FASTDP-BUS of embodiment of the present invention bus master channel downlink exchanges control schematic diagram；
Fig. 8 is that FASTDP-BUS of embodiment of the present invention bus master channel uplink exchanges control schematic diagram；Fig. 9 is the present invention
Embodiment FASTDP-BUS bus slave station channel uplink exchanges control schematic diagram.
The FASTDP-BUS Channel Exchange controlling mechanism is as follows: after channel obtains the bus right to use, in defined friendship
It changes in time slot, in the transmission of uplink and downlink data, by channel address, attribute and channel data, with link data frame
Destination address, FC control domain and data field mutually map, and realize the number of main website and slave station transmission data between corresponding channel
According to exchange；
The exchange control of main website channel downlink: channel down buffer storage data work is read in the channel that main website is obtained for arbitration
For link frame data field, using channel address as the destination address of link data frame, using channel type as FC control domain
Attribute generates downlink data frame to Bus repeater；
The exchange control of main website channel uplink: main website is directed to the link data frame received, using data frame raw address as logical
Track address finds the corresponding upstream data of link frame data and caches and store and write using FC control Domain Properties as channel type
Enter；
Channel is unanimously preferential: after main website down going channel data exchange to slave station, the preferential uplink of slave station is consistent with the channel
Channel data；
Channel multiplexing mechanism: after main website down going channel data exchange to slave station, slave station is multiplexed the time slot uplink and the channel
Inconsistent data；
Idle multiplexing mechanism: after main website down going channel data exchange to slave station, the data that slave station corresponds to the channel are not ready
When, channel multiplexing mechanism is enabled, will be sent on the inconsistent other channel datas in channel；
Promptly it is multiplexed mechanism: after main website down going channel data exchange to slave station, if the emergency access data ready of slave station,
Channel multiplexing mechanism is then enabled immediately, and preferential will send in emergency access data；
The exchange control of slave station channel uplink: slave station is directed to the main website downlink data channel received, according to elder generation by promptly counting
According to, to consistent row of channels, arrive the sequencing in inconsistent channel, arbitrating access channel again；According to the channel attributes arbitrated out, divide
It Qi Yong not be multiplexed mechanism, the consistent override mechanism in channel, idle multiplexing mechanism promptly, channel data is done to link data frame and is reflected
It penetrates.
The FASTDP-BUS bus links Data Transmission Controlling process is as follows:
Master station application layer caches downlink data write-in channel downlink data；
Main website refreshes access ready flag set by channel access ready list；
Main website goes out the data channel of currently the only highest priority by channel priorities arbitration mechanism, ruling；
Main website exchanges controlling mechanism by main website channel downlink, realizes channel downlink data to downlink data frame
Mode to Bus repeater；
After slave station receives main website downlink data frame and handles, controlling mechanism is exchanged using slave station channel uplink immediately,
Slave station uplink data frames are sent to bus；
Main website receives in bus after slave station uplink data frames, exchanges controlling mechanism using bus master channel uplink,
Realize the exchange in data from station channel to main website channel；
Master station application layer caches from channel upstream data and reads upstream data.
The foregoing is only a preferred embodiment of the present invention, is not intended to limit the scope of the present invention.
Claims (10)
1. a kind of distributed peripheral bus system of stringent access and sampling time characterized by comprising a monobus
Main website and at least one bus slave station；The physical layer of its system uses the low-voltage differential signal LVDS bussing technique of dual redundant；
Its data link layer is using the on-site programmable gate array FPGA or FASTDP-BUS agreement for realizing FASTDP-BUS link protocol
It controls chip to realize, the FASTDP-BUS protocol integrated test system chip is realized using application-specific integrated circuit ASIC mode；Its application layer
Using FASTDP-BUS application layer protocol specification, and pass through industry standard architecture isa bus for FPGA or FASTDP-BUS
The CPU that control chip is mapped to internal address space is realized.
2. the distributed peripheral bus system in stringent access and sampling time according to claim 1, which is characterized in that institute
Data link layer is stated, data link frame is divided into containing the link layer data frame using data APP DATA field and without using number
According to the link layer data frame of APP DATA field；Wherein, described containing the link layer data frame for applying data APP DATA, include
Application layer data；The link layer data frame without application data APP DATA, the LLC DATA word comprising indication field length
Section；The application layer data, including following field: send caching in application layer data message in comprising Dest Addr, DUn,
Whole length LE3 fields of FCS field, destination address Dest Addr field, APP DATA field and and verification FCS field；
The APP DATA field includes multiple data field DU；Each DU length is 1 byte；
The link layer data frame containing application data APP DATA, including following field:
Frame synchronization head Sync Head field, destination address Dest Addr field, source address Src Addr field, link layer transfer
Channel C MD field, transmission frame control byte fc field, have using the isl frame APP DATA field of data length LE2 instruction
Attribute field, APP DATA field, cyclic redundancy check code crc field and frame synchronization tail Sync Tail field；
The link layer data frame without application data APP DATA, including following field: frame synchronization head Sync Head field,
Destination address Dest Addr field, source address Src Addr field, link layer transfer channel C MD field, transmission frame control byte
Fc field represents length LLC DATA field, cyclic redundancy without isl frame LE1 Warning Mark field, field using data
Check code CRC field and frame synchronization tail Sync Tail field.
3. the distributed peripheral bus system in stringent access and sampling time according to claim 1, which is characterized in that institute
The application-layer data transmission channel for stating distributed peripheral bus, the FC control including mark application layer channel is arranged on isl frame head
Field processed realizes the mark in the channel URG, the channel NORM, the channel WAVE, the channel MNG；Wherein:
The channel NORM, is used for transmission the channel of overlayable distributed I/O slave station real time data, the data include can cover, can between
The sampling input data such as AI, the DI of situations such as disconnected loss；And the outputs control data such as cpu cycle property DO, AO for persistently exporting；
FASTDP-BUS bus is that each distributed I/O slave station in the channel is arranged independent reception caching, sends caching, is constituted
The subchannel in the channel NORM；
The channel URG is used for transmission the channel of the emergency operation data of the distributed I/O for the transmission that can jump the queue；FASTDP-BUS bus is
The channel is only arranged a common reception caching and caches with a common reception, and the caching is by all distributed I/O slave stations
Emergency data share；
The channel WAVE, is used for transmission the channel of the data of the value of not overlayable distributed I O point, which includes that cannot cover
The data of the AI points of situations such as lid, loss, the data such as DI point, DI point SOE, EVENT；FASTDP-BUS is that the channel is only arranged one
A common reception caching, and the caching is shared by the emergency data of all distributed I/O slave stations；
The channel MNG, is used for transmission the channel of distributed I/O slave station configuration management data, the data include equipment self-description information,
The inquiry of the data such as IO slave station operating parameter and configuration order etc.；All distributed I/O slave stations share the channel, only setting one
Common reception caching and a common reception caching are shared.
4. the distributed peripheral bus system in stringent access and sampling time according to claim 3, which is characterized in that its
The real-time NORM data transmission channel of distributed I/O slave station, specifically:
The bus is that an independent real-time NORM data channel, and the visit set according to application layer is arranged in each IO slave station
Ask that the period obtains bus access power；Each described corresponding channel of IO slave station is a subchannel of the channel NORM classification.
5. the distributed peripheral bus system in stringent access and sampling time according to claim 1, which is characterized in that its
The link data transfer channel of data link layer, is divided into: by link layer creation and the pair channel managed, synchronizing channel, Cha Xin
Channel, diagnosis channel；The link layer link data channel is not provided with transmitting-receiving caching, is directly handled by the data link layer；
Wherein:
Pair channel is used for transmission the channel to the clock synchronization data of distributed I/O, and the period by setting is activating the channel to carry out
Clock synchronization；
Synchronizing channel is used for transmission the channel of the synchronized sampling order to distributed I/O, according to the synchronous calibration period of setting, swashs
It serves somebody right channel, realization sampling step sequence calibration；
New tunnel is looked into, the channel of the distributed I/O querying command of new access bus is used for transmission；During bus free, according to new
Access system IO slave station polling cycle activates the channel, to the distributed I/O newly run in FASTDP-BUS bus carry out inquiry and
Initialization；
It diagnoses channel and, according to the interval between diagnosis of setting, activates the channel for link layer transfer to the channel of Diagnosis of Links order
Realize diagnosis.
6. being existed according to access stringent described in claim 3~5 and the distributed peripheral bus system in sampling time, feature
In each channel of the bus carries out bus access according to channel access ready list mechanism, and the channel access ready list is two
Structure is tieed up, is made of the corresponding row unit of corresponding row access cycle and channel；Including the control of fixed priority channel, access
The control of time uncertainty channel, the control of NORM and IO slave station channel；It further include period ready flag refresh control time slot rotation
Ready flag control.
7. being existed according to access stringent described in claim 3~5 and the distributed peripheral bus system in sampling time, feature
In channel access time determinability criterion is divided into:
When IO slave station channel period is not present in ready list, then default using equal-opportunity sequential access mechanism；Work as ready list
Middle configuration IO slave station channel period then uses ready list prioritization of access controlling mechanism.
8. being existed according to access stringent described in claim 3~5 and the distributed peripheral bus system in sampling time, feature
In channel access priority arbitration mechanism are as follows: by the ready flag position of channel access ready list set, realize that channel is preferential
Grade arbitration.
9. being existed according to access stringent described in claim 3~5 and the distributed peripheral bus system in sampling time, feature
In Channel Exchange controlling mechanism are as follows: after the channel obtains the bus right to use, in defined switching time slot, upper
In capable and downlink data transmission, by channel address, attribute and channel data, controlled with the destination address of link data frame, FC
Domain processed and data field mutually map, and realize the data exchange of main website and slave station transmission data between corresponding channel.
10. a kind of implementation method of the distributed peripheral bus system of stringent access and sampling time, which is characterized in that packet
It includes:
One monobus main website and at least one bus slave station are set；
The physical layer of the bus system is set to use the low-voltage differential signal LVDS bussing technique of dual redundant；
Make the data link layer of the bus system using the on-site programmable gate array FPGA for realizing FASTDP-BUS link protocol
Or FASTDP-BUS control chip realizes that the FASTDP-BUS protocol integrated test system chip is real using application-specific integrated circuit ASIC mode
It is existing；
Make the application layer of the bus system using FASTDP-BUS application layer data specification, and passes through industry standard architecture
Isa bus realizes the CPU that FPGA or FASTDP-BUS protocol integrated test system chip is mapped to internal address space.
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