CN101882593B - Method for improving breakdown voltage from N-well to another N-well - Google Patents
Method for improving breakdown voltage from N-well to another N-well Download PDFInfo
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- CN101882593B CN101882593B CN2009100506934A CN200910050693A CN101882593B CN 101882593 B CN101882593 B CN 101882593B CN 2009100506934 A CN2009100506934 A CN 2009100506934A CN 200910050693 A CN200910050693 A CN 200910050693A CN 101882593 B CN101882593 B CN 101882593B
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- trap
- well
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- under
- puncture voltage
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Abstract
The invention discloses a method for improving breakdown voltage from an N-well to another N-well, which comprises the following steps: providing a silicon substrate; forming a first N-well and a second N-well which are adjacent in the silicon substrate; arranging a shallow-groove isolating structure between the first N-well and the second N-well; arranging a P-well under the shallow-groove isolating structure to isolate the first N-well from the second N-well; and respectively forming a first isolating P-well and a second isolating P-well under the first N-well and the second N-well by an ion injection technology. The method respectively forms the isolating P-wells under the two adjacent N-wells by the ion injection technology with high energy, thereby preventing drain current from passing through the low-impedance silicon substrate under the P-wells, enabling the drain current to mainly pass through the isolating P-wells under the two high-impedance N-wells, greatly reducing the drain current value between the two adjacent N-wells, and greatly improving the breakdown voltage value.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of method that improves the N-trap to N-trap puncture voltage.
Background technology
In fabrication of semiconductor device; When two adjacent traps are the N trap; The structure of these two adjacent N traps is as shown in Figure 1, and this two adjacent N trap 110 and 120 is arranged in the silicon substrate 130, because of the many sons in the N trap are electronics; So the leakage current that causes this two adjacent N trap 110 and 120 and electric leakage breakdown probability can be greater than two adjacent P traps; Be leakage current and the electric leakage breakdown probability thereof that reduces this two adjacent N trap 110 and 120, except meeting is provided with the fleet plough groove isolation structure 140 (STI) this two adjacent N trap 110 and 120, also the zone under fleet plough groove isolation structure 140 is carried out the boron ion again and is injected and form one deck P trap 150; The injection energy range that this boron ion injects is 25 to 170 kiloelectron-volts, and the implantation dosage scope is 4.4 * 10
12To 1.5 * 10
13Atom per square centimeter.Through measuring instrument this two adjacent N trap 110 and 120 is carried out leakage tests; Find its leakage current 150 times low-impedance silicon substrates 130 of P trap of mainly flowing through, (value that puncture voltage is defined as leakage current is 1.0 * 10 to measure this two adjacent N trap 110 and 120 s' puncture voltage through measuring instrument in addition
-9The magnitude of voltage of ampere every micron the time) be merely 6 to 8 volts, it can not satisfy the requirement to device performance, and then can influence the quality of related application product less than normal 14 to 15 volts required puncture voltage.
Summary of the invention
The present invention is intended to solve in the prior art; Only isolating through fleet plough groove isolation structure and P trap between two adjacent N traps causes mainly flow through under the P trap low-impedance silicon substrate and its value of leakage current bigger; And cause the puncture voltage between two adjacent N traps lower, and then cause technical problems such as the performance of semiconductor device is not good.
In view of this, the present invention provides the method for a kind of N-of raising trap to N-trap puncture voltage, may further comprise the steps:
One silicon substrate is provided;
In said silicon substrate, form adjacent a N trap and the 2nd N trap;
Between a said N trap and the 2nd N trap, fleet plough groove isolation structure is set;
The P trap is set, to separate a said N trap and the 2nd N trap under said fleet plough groove isolation structure; And
Under a said N trap and the 2nd N trap, form first respectively through ion implantation technology and isolate the P trap and the second isolation P trap.
Optional, the injection energy range that said ion implantation technology is is 400 to 2000 kiloelectron-volts, the implantation dosage scope is 2 * 10
12To 1 * 10
13Atom per square centimeter.
Optional, said ion implantation technology injects for the boron ion or indium ion injects.
Optional, said P trap is to process through the boron ion implantation technology, and it injects energy range is 25 to 170 kiloelectron-volts, and the implantation dosage scope is 4.4 * 10
12To 1.5 * 10
13Atom per square centimeter.
In sum; Raising N-trap provided by the invention uses high-octane ion implantation technology to the method for N-trap puncture voltage; Under two adjacent N traps, form to isolate the P trap respectively, thereby stoped the leakage current low-impedance silicon substrate under the P trap of flowing through, make the leakage current isolation P trap under the N trap of high impedance of mainly flowing through; Make the leakage current value between two adjacent N traps significantly reduce, breakdown voltage value also is increased dramatically.
Description of drawings
Shown in Figure 1 is the structural representation of two adjacent N traps in the prior art;
Shown in Figure 2 for the structural representation of the adjacent N trap that one embodiment of the invention provided;
Shown in Figure 3ly be a kind of N-of raising trap that one embodiment of the invention provided flow chart to the method for N-trap puncture voltage;
Shown in Figure 4 is at the TCAD simulation curve figure that carries out the puncture voltage between the injection of ion implantation technology intermediate ion energy, ion implantation dosage and adjacent N trap.
Embodiment
For making the object of the invention, characteristic more obviously understandable, provide preferred embodiment and combine accompanying drawing, the present invention is described further.
One embodiment of the invention provides the method for a kind of N-of raising trap to N-trap puncture voltage, please combine referring to Fig. 2 and Fig. 3, and this method may further comprise the steps:
Step S310 at first provides a silicon substrate 200.
Step S320 forms an adjacent N trap 210 and the 2nd N trap 220 in said silicon substrate 200.
Step S330 is provided with fleet plough groove isolation structure (STI) 230 between a said N trap 210 and the 2nd N trap 220.Because the many sons in the N trap are electronics; So the leakage current that causes this two adjacent N trap 210 and 220 and electric leakage breakdown probability can be greater than two adjacent P traps; Be leakage current and the electric leakage breakdown probability thereof that reduces this two adjacent N trap 210 and 220, fleet plough groove isolation structure 230 be set this two adjacent N trap 210 and 220.
Step S340 is provided with P trap 240 230 times at said fleet plough groove isolation structure, to separate a said N trap 210 and the 2nd N trap 220.In order further to reduce this two adjacent N trap 210 and 220 the leakage current and the breakdown probability of leaking electricity thereof; Also the zone under fleet plough groove isolation structure 230 is carried out the injection of boron ion again and is formed P trap 240; The injection energy range that this boron ion injects is 25 to 170 kiloelectron-volts, and the implantation dosage scope is 4.4 * 10
12To 1.5 * 10
13Atom per square centimeter.
Step S350 forms first for 220 times at a said N trap 210 and the 2nd N trap respectively through ion implantation technology and isolates the P trap 250 and the second isolation P trap 260, and the silicon substrate 200 that links to each other with P trap 240 a N trap 210 and the 2nd N trap 220 and its underpart separates.Owing under two adjacent N traps, form respectively and isolate the P trap; Thereby make the leakage current isolation P trap under two N traps of high impedance of mainly flowing through; Make the leakage current value between two adjacent N traps significantly reduce; Breakdown voltage value also is increased dramatically, and its puncture voltage of experiment proof can rise to 26 volts from 6 volts.
In the present embodiment, employed in the said ion implantation technology for the boron ion injects or the indium ion injection, but the present invention is not limited to this, all can all being included in the present invention by realization ion of the present invention.
When carrying out the ion injection, injecting energy range is 400 to 2000 kiloelectron-volts, and the implantation dosage scope is 2 * 10
12To 1 * 10
13Atom per square centimeter.
See also Fig. 4, it is depicted as at the graph of relation that carries out the puncture voltage between the injection of ion implantation technology intermediate ion energy, ion implantation dosage and adjacent N trap.
Be injected to example with the boron ion, when injecting 800 kiloelectron-volts of energy, ion implantation dosage is 1 * 10
12To 5 * 10
12When the atom per square centimeter interval increased, puncture voltage also increased thereupon, arrived 2 * 10 at ion implantation dosage
12During atom per square centimeter, puncture voltage reaches about 16 volts, has been higher than normal 14 to the 15 volts required puncture voltage of practical application.When ion implantation dosage approximately arrives 5 * 10
12During atom per square centimeter, puncture voltage reaches about 26 volts, is much higher than normal 14 to the 15 volts required puncture voltage of practical application.
In sum, only isolate between two adjacent N traps in the prior art and cause mainly flow through under the P trap low-impedance silicon substrate and its value of leakage current bigger, and cause the puncture voltage between two adjacent N traps lower through fleet plough groove isolation structure and P trap.The raising N-trap that the embodiment of the invention provides uses high-octane ion implantation technology to the method for N-trap puncture voltage; Under two adjacent N traps, form respectively and isolate the P trap; Thereby stoped the leakage current low-impedance silicon substrate under the P trap of flowing through; Make the leakage current isolation P trap under the N trap of high impedance of mainly flowing through, make that the leakage current value between two adjacent N traps significantly reduces, breakdown voltage value also is increased dramatically.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (4)
1. method that improves the N-trap to N-trap puncture voltage may further comprise the steps:
One silicon substrate is provided;
In said silicon substrate, form adjacent a N trap and the 2nd N trap;
Between a said N trap and the 2nd N trap, fleet plough groove isolation structure is set;
The P trap is set, to separate a said N trap and the 2nd N trap under said fleet plough groove isolation structure; And
Under a said N trap and the 2nd N trap, form first respectively through ion implantation technology and isolate the P trap and the second isolation P trap.
2. raising N-trap according to claim 1 is characterized in that to the method for N-trap puncture voltage wherein, the injection energy range that said ion implantation technology is is 400 to 2000 kiloelectron-volts, and the implantation dosage scope is 2 * 10
12To 1 * 10
13Atom per square centimeter.
3. raising N-trap according to claim 1 is characterized in that to the method for N-trap puncture voltage wherein, said ion implantation technology injects for the boron ion or indium ion injects.
4. raising N-trap according to claim 1 is to the method for N-trap puncture voltage; It is characterized in that wherein, the P trap that said fleet plough groove isolation structure is provided with down is to process through the boron ion implantation technology; It injects energy range is 25 to 170 kiloelectron-volts, and the implantation dosage scope is 4.4 * 10
12To 1.5 * 10
13Atom per square centimeter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100506934A CN101882593B (en) | 2009-05-06 | 2009-05-06 | Method for improving breakdown voltage from N-well to another N-well |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100506934A CN101882593B (en) | 2009-05-06 | 2009-05-06 | Method for improving breakdown voltage from N-well to another N-well |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101882593A CN101882593A (en) | 2010-11-10 |
| CN101882593B true CN101882593B (en) | 2012-01-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100506934A Expired - Fee Related CN101882593B (en) | 2009-05-06 | 2009-05-06 | Method for improving breakdown voltage from N-well to another N-well |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9252251B2 (en) | 2006-08-03 | 2016-02-02 | Infineon Technologies Austria Ag | Semiconductor component with a space saving edge structure |
| CN103165604B (en) * | 2011-12-19 | 2016-11-09 | 英飞凌科技奥地利有限公司 | There is the semiconductor device of joint space-efficient marginal texture |
| CN111785770A (en) * | 2019-04-03 | 2020-10-16 | 北京大学 | Substrate leakage isolation structure of conventional tunneling field effect transistor and process method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230024A (en) * | 1998-03-25 | 1999-09-29 | 日本电气株式会社 | Semiconductor device |
-
2009
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230024A (en) * | 1998-03-25 | 1999-09-29 | 日本电气株式会社 | Semiconductor device |
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