CN101881982B - Voltage stabilizing circuit for preventing overshoot and reference circuit - Google Patents
Voltage stabilizing circuit for preventing overshoot and reference circuit Download PDFInfo
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- CN101881982B CN101881982B CN2009100833847A CN200910083384A CN101881982B CN 101881982 B CN101881982 B CN 101881982B CN 2009100833847 A CN2009100833847 A CN 2009100833847A CN 200910083384 A CN200910083384 A CN 200910083384A CN 101881982 B CN101881982 B CN 101881982B
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Abstract
The invention relates to the circuit protection field, which provides a voltage stabilizing circuit preventing overshoot and a reference circuit for solving the overshoot problem of a voltage stabilizing circuit in the prior art. The voltage stabilizing circuit preventing overshoot comprises a differential amplifier, an output stage, a control signal unit and a switch circuit. When the voltage stabilizing circuit is just powered on, the switch circuit controls the output stage according to control signals in order to restrain the output end overshoot of the output stage.
Description
Technical field
The present invention relates to circuit protection field, particularly a kind of mu balanced circuit and reference circuit that prevents overshoot.
Background technology
In the prior art, mu balanced circuit does not all have overshoot protection, and the too high meeting of the output voltage of mu balanced circuit causes the damage or the misoperation of follow-up circuit.
Generally, reference circuit comprises band-gap reference circuit and mu balanced circuit, and also there are the problems referred to above in reference circuit, and the reference circuit of low-power consumption also exists and start slow shortcoming, and this will inevitably restrict the speed that powers on of total system.
Reference circuit is that whole simulation system provides reference voltage, is very crucial module.Be illustrated in figure 1 as reference circuit synoptic diagram in the prior art, reference circuit is made up of band-gap reference circuit 101 and mu balanced circuit 102 two parts usually.
Mu balanced circuit 102 is made up of differential amplifier circuit, the output stage that links to each other with differential amplifier circuit.When mu balanced circuit powers on, the bias current I of differential amplifier circuit
BIASAlso do not set up, so differential amplifier circuit can't drive the efferent duct M9 of output stage; The source electrode of M9 links to each other with power supply, and when power supply rose gradually, the source electrode of M9 can rise with power supply with identical speed; And the grid of M9 can not rise with power supply, therefore owing to the influence of stray capacitance and miller compensation electric capacity; Along with the rising gradually of power supply, the source gate voltage missionary society of M9 becomes greatly gradually, when its during greater than the threshold voltage of M9; M9 can flow out bigger electric current on resistance string (R3 and R4), and this moment, a bigger overshoot can appear in the VREF end, and the power supply ascending velocity is fast more; This overshoot will be high more, up to the bias current I of differential amplifier circuit
BIASSet up, differential amplifier circuit could drive the overshoot that M9 suppresses the VREF end.When differential amplifying circuit is the grid capacitance of low-power consumption amplifier or M9 when very big, the duration of overshoot will be very long, and this will inevitably influence the regular event of total system when powering on.
Band-gap reference circuit 101 provides zero-temperature coefficient reference voltage V BG and bias current I for mu balanced circuit 102
BIAS, because the power consumption of band-gap reference circuit is very low, and in order to improve its PSRR, the size of M3, M4, M5 and M6 is bigger, the VBG place also can add a bigger shunt capacitance C
LSo, VBG and I when powering on
BIASNeed very long stabilization time, thereby limited the speed that powers on of total system.
There are a lot of technology to accelerate the speed that powers on of reference circuit now, can behind baseline stability, turn-off the rapid charge path effectively again simultaneously, thereby realize the reference circuit of low-power consumption through adding rapid charge path and feedback loop.Yet they all can not solve the reference voltage V BG overshooting problem that the rapid charge path causes effectively.
Summary of the invention
The embodiment of the invention provides a kind of mu balanced circuit and reference circuit that prevents overshoot, is used for solving the problem that the prior art mu balanced circuit does not have overshoot protection, and can solve the problem that has the reference circuit rapid charge now and prevent overshoot.
In order to solve the problems of the technologies described above, the embodiment of the invention provides a kind of mu balanced circuit that prevents overshoot, comprises differential amplifier, output stage, control signal unit and on-off circuit; Said differential amplifier is transfused to predetermined reference voltage, produces amplifying voltage according to said predetermined reference voltage; Said output stage, the output that produces said mu balanced circuit according to said amplifying voltage; Said control signal unit produces control signal according to the reference current of said differential amplifier; When said mu balanced circuit had just powered on, the reference current of said differential amplifier also not to be set up, and said control signal unit provides enabling signal; After the reference current of said differential amplifier was stable, said control signal unit provided cut-off signals; Said on-off circuit is controlled said output stage according to control signal; When said control signal was enabling signal, said on-off circuit turn-offed said output stage; When said control signal was cut-off signals, said on-off circuit let said differential amplifier drive said output stage.
A further aspect according to mu balanced circuit of the present invention; When said output stage comprises the PMOS transistor; Said on-off circuit is the PMOS transistor; The transistorized grid of the PMOS of said on-off circuit is connected with said control signal unit, and the transistorized source electrode of the PMOS of said on-off circuit links to each other with power supply, and the PMOS transistor drain of said on-off circuit links to each other with the transistorized grid of the PMOS of said output stage;
Perhaps said on-off circuit is a nmos pass transistor; The grid of the nmos pass transistor of said on-off circuit is connected with said control signal unit; The drain electrode of the nmos pass transistor of said on-off circuit is connected with power supply, and the source electrode of said nmos pass transistor is connected with the transistorized grid of the PMOS of said output stage;
Perhaps said on-off circuit is a cmos switch, and said cmos switch is connected between the transistorized grid of PMOS and power supply of said output stage, is controlled the conducting or the disconnection of said cmos switch by said control signal.
Another further aspect according to mu balanced circuit of the present invention; When said output stage comprises nmos pass transistor; Said on-off circuit is the PMOS transistor; The transistorized grid of the PMOS of said on-off circuit is connected with said control signal unit, and the PMOS transistor drain of said on-off circuit links to each other with ground, and the transistorized source electrode of the PMOS of said on-off circuit links to each other with the grid of the nmos pass transistor of said output stage;
Perhaps said on-off circuit is a nmos pass transistor; The grid of the nmos pass transistor of said on-off circuit is connected with said control signal unit; The drain electrode of the nmos pass transistor of said on-off circuit is connected with the grid of the nmos pass transistor of said output stage, and the source electrode of said nmos pass transistor is connected with ground;
Perhaps said on-off circuit is a cmos switch, and said cmos switch is connected between the grid and ground of nmos pass transistor of said output stage, is controlled the conducting of said cmos switch or is broken off by said control signal.
Another further aspect according to mu balanced circuit of the present invention; When said output stage comprised the PMOS transistor, said on-off circuit switched the transistorized grid of said output stage PMOS according to said control signal between the output of power supply and said differential amplifier.
Another further aspect according to mu balanced circuit of the present invention; When said output stage comprised nmos pass transistor, said on-off circuit switched the transistorized grid of said output stage PMOS according to said control signal between the output of ground and said differential amplifier.
In order to solve the problems of the technologies described above, the embodiment of the invention also provides a kind of low-power consumption reference circuit, comprises band-gap reference circuit, mu balanced circuit and quick-charging circuit; Said band-gap reference circuit provides bandgap voltage reference, bias current and control signal to said mu balanced circuit; Wherein said band-gap reference circuit comprises control signal unit and reference generating circuit;
Said control signal unit produces control signal, gives said reference generating circuit, said quick-charging circuit and said mu balanced circuit with said control signal; When the reference current of band-gap reference circuit was not set up, said control signal unit provided enabling signal; When the reference current of band-gap reference circuit was stablized, said control signal unit provided cut-off signals;
Said reference generating circuit utilizes said control signal to come normal the startup when powering on, for said mu balanced circuit provides bandgap voltage reference and bias current;
Said mu balanced circuit comprises differential amplifier, first on-off circuit, output stage; Said differential amplifier receives said bandgap voltage reference and bias current, produces amplifying voltage according to said bandgap voltage reference; Said output stage, the output that produces said mu balanced circuit according to said amplifying voltage; Said first on-off circuit is controlled said output stage according to control signal, and when said control signal was enabling signal, said on-off circuit turn-offed said output stage; When said control signal was cut-off signals, said on-off circuit let said differential amplifier drive said output stage.
Said quick-charging circuit; Being used for when said reference circuit powers on is said reference generating circuit output auxiliary current; Said bandgap voltage reference can be set up fast; And the size control output auxiliary current according to said bandgap voltage reference overshoot occurs to prevent said bandgap voltage reference.
According to another further aspect of reference circuit of the present invention, said quick-charging circuit is that a grid is connected with a fixed bias voltage, and source electrode is connected with said bandgap voltage reference end, the nmos pass transistor that drain electrode is connected with power supply.
Another further aspect according to reference circuit of the present invention; Between the drain electrode of said quick-charging circuit and power supply, also comprise the second switch circuit; One end of this second switch circuit is connected with power supply; The other end is connected with the drain electrode of said quick-charging circuit, when said reference circuit powers on, opens or turn-off said quick-charging circuit according to said control signal.
Another further aspect according to reference circuit of the present invention; Said second switch circuit is the PMOS transistor; The transistorized grid of said PMOS is connected with said control signal unit; The transistorized source electrode of said PMOS is connected with power supply, and said PMOS transistor drain is connected with the drain electrode of said quick-charging circuit;
Perhaps said second switch circuit is a nmos pass transistor, and the grid of said nmos pass transistor is connected with said control signal unit; The drain electrode of said nmos pass transistor is connected with power supply; The source electrode of said nmos pass transistor is connected with the drain electrode of said quick-charging circuit;
Perhaps said second switch circuit is a cmos switch, and said cmos switch is connected between the drain electrode and power supply of said quick-charging circuit, is controlled the conducting or the disconnection of said cmos switch by said control signal.
Another further aspect according to reference circuit of the present invention; Between the grid of said quick-charging circuit and said fixed bias voltage, also comprise the second switch circuit, said second switch circuit switches between said fixed bias voltage and ground according to the grid of said control signal with said quick-charging circuit.
The beneficial effect of the embodiment of the invention is, can effectively prevent the overshoot of mu balanced circuit, and for reference circuit, can realize rapid charge, and can suppress the overshoot phenomenon of reference circuit equally; The scenario-frame of the embodiment of the invention is simple, and cost is low.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Shown in Figure 1 is reference circuit synoptic diagram in the prior art;
Shown in Figure 2 is a kind of mu balanced circuit first example structure figure that prevents overshoot of the present invention;
Shown in Figure 3 is the circuit diagram of said control signal unit;
Fig. 4 a is depicted as on-off circuit employing PMOS transistor of the present invention and output stage is the mu balanced circuit embodiment circuit diagram of common-source stage;
Fig. 4 b is depicted as on-off circuit employing cmos switch of the present invention and output stage is the mu balanced circuit embodiment circuit diagram of common-source stage;
Fig. 4 c is depicted as on-off circuit employing nmos pass transistor of the present invention and output stage is the mu balanced circuit embodiment circuit diagram of source follower;
Fig. 4 d is depicted as on-off circuit employing PMOS transistor of the present invention and output stage is the mu balanced circuit embodiment circuit diagram of push-pull type output stage;
Shown in Figure 5 is a kind of another example structure of mu balanced circuit figure that prevents overshoot of the present invention;
Fig. 6 a is depicted as the present invention and adopts the single-pole double-throw switch (SPDT) of PMOS transistor and cmos switch combination and the mu balanced circuit embodiment circuit diagram that output stage is common-source stage;
Fig. 6 b is depicted as the present invention and adopts the single-pole double-throw switch (SPDT) of nmos pass transistor and cmos switch combination and the mu balanced circuit embodiment circuit diagram that output stage is source follower;
Fig. 6 c is depicted as the present invention and adopts the single-pole double-throw switch (SPDT) of PMOS transistor and cmos switch combination and the mu balanced circuit embodiment circuit diagram that output stage is the push-pull type output stage;
Shown in Figure 7 is a kind of low-power consumption reference circuit first example structure synoptic diagram of the present invention;
Shown in Figure 8 is a kind of low-power consumption reference circuit second example structure synoptic diagram of the present invention;
Shown in Figure 9 is a kind of low-power consumption reference circuit the 3rd example structure synoptic diagram of the present invention;
Shown in Figure 10 is a kind of low-power consumption reference circuit the 4th example structure synoptic diagram of the present invention;
Shown in Figure 11 is a kind of low-power consumption reference circuit the 5th example structure synoptic diagram of the present invention;
Shown in Figure 12 is a kind of low-power consumption reference circuit the 6th example structure synoptic diagram of the present invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
The embodiment of the invention provides a kind of mu balanced circuit and reference circuit that prevents overshoot.Below in conjunction with accompanying drawing the present invention is elaborated.
Be illustrated in figure 2 as a kind of mu balanced circuit first example structure figure that prevents overshoot of the present invention.
Comprise single-stage or multipole differential amplifier 201, on-off circuit 202, output stage 203, control signal unit 204.
Said differential amplifier 201, output stage 203 are prior art, and said control signal unit 204 produces control signal according to the reference current of said differential amplifier; Be illustrated in figure 3 as the circuit diagram (the present invention does not limit the circuit of control signal unit and forms mode) of said control signal unit, wherein I
XBe to come from the inner image current of differential amplifier, perhaps come from the outside bias current of differential amplifier.When said mu balanced circuit had just powered on, the reference current of said differential amplifier 201 also not to be set up, and said control signal unit 204 provides enabling signal; After the reference current of said differential amplifier 201 was stable, said control signal unit 204 provided cut-off signals.
On-off circuit 202 is controlled the output of said output stage 203 according to control signal when said mu balanced circuit powers on, thereby overshoot appears in the output terminal that prevents said mu balanced circuit; When said control signal was enabling signal, said on-off circuit 202 closures were turn-offed said output stage 203; When said control signal was cut-off signals, said on-off circuit 202 broke off, and drove said output stage 203 by said differential amplifier 201.
As one embodiment of the present of invention; When said output stage 203 is the resistance string of PMOS transistor and ground connection; Said on-off circuit 202 is PMOS transistors; Be depicted as on-off circuit 202 of the present invention like Fig. 4 a and adopt PMOS transistor and output stage 203 to be the mu balanced circuit embodiment circuit diagram of common-source stage, the transistorized grid of the PMOS of said on-off circuit is connected with said control signal unit 204; The transistorized source electrode of the PMOS of said on-off circuit is connected with power supply; The PMOS transistor drain of said on-off circuit is connected with the transistorized grid of the PMOS of said output stage.
As one embodiment of the present of invention, when said output stage 203 comprised the PMOS transistor, said on-off circuit was a nmos pass transistor, and the grid of the nmos pass transistor of said on-off circuit is connected with said control signal unit 204; The drain electrode of the nmos pass transistor of said on-off circuit is connected with power supply; The source electrode of said nmos pass transistor is connected with the transistorized grid of the PMOS of said output stage.
As one embodiment of the present of invention; When said output stage 203 comprises the PMOS transistor; Said on-off circuit is a cmos switch; Be depicted as on-off circuit of the present invention like Fig. 4 b and adopt cmos switch and output stage 203 to be the mu balanced circuit embodiment circuit diagram of common-source stage, said cmos switch is connected between the transistorized grid of PMOS and power supply of said output stage, is controlled the conducting or the disconnection of said cmos switch by said control signal.The PMOS transistor of wherein said cmos switch receives control signal ST, and the nmos pass transistor of said cmos switch receives the signal of ST negate.
When just powering on, the bias current of differential amplifier 201 is not also set up, and differential amplifier 201 does not also have driving force; Control signal unit 204 provides an enabling signal at this moment; The said on-off circuit 202 of conducting, on-off circuit 202 turn-offs the PMOS transistor of said output stage 203 through with moving supply voltage on the transistorized grid potential of the PMOS of said output stage 203; Make it can not output current, thereby suppressed the overshoot of said mu balanced circuit output terminal when powering on; After the bias current of differential amplifier 201 is set up; Differential amplifier 201 has had driving force, and this moment, control signal became shutdown signal, in time turn-offed said on-off circuit 202; Drive the efferent duct of output stage 203 by differential amplifier 201, make output voltage V
OUTBe stabilized in predetermined value.
As one embodiment of the present of invention; When said output stage comprises nmos pass transistor; Said on-off circuit is a nmos pass transistor; Being depicted as on-off circuit of the present invention like Fig. 4 c, to adopt nmos pass transistor and output stage be the mu balanced circuit embodiment circuit diagram of source follower, and the grid of the nmos pass transistor of said on-off circuit 202 is connected with said control signal unit 204; The source electrode of the nmos pass transistor of said on-off circuit is connected with ground; The drain electrode of the nmos pass transistor of said on-off circuit is connected with the grid of the nmos pass transistor of said output stage.
As one embodiment of the present of invention, when said output stage comprised nmos pass transistor, said on-off circuit was the PMOS transistor, and the transistorized grid of the PMOS of said on-off circuit is connected with said control signal unit 204; The PMOS transistor drain of said on-off circuit is connected with ground; The transistorized source electrode of said PMOS is connected with the grid of the nmos pass transistor of said output stage.
As one embodiment of the present of invention; When said output stage comprises nmos pass transistor; Said on-off circuit is a cmos switch, and said cmos switch is connected between the grid and ground of nmos pass transistor of said output stage, is controlled the conducting of said cmos switch or is broken off by said control signal.
When just powering on, the bias current of differential amplifier 201 is not also set up, and differential amplifier 201 does not also have driving force; Control signal unit 204 provides an enabling signal at this moment; The said on-off circuit 202 of conducting, on-off circuit 202 pulls down to ground voltage through the grid potential with the nmos pass transistor of said output stage 203, turn-offs the nmos pass transistor of said output stage 203; Make it can not output current, thereby suppressed the overshoot of said mu balanced circuit output terminal when powering on; After the bias current of differential amplifier 201 is set up; Differential amplifier 201 has had driving force, and this moment, control signal became shutdown signal, in time turn-offed said on-off circuit 202; Drive the efferent duct of output stage 203 by differential amplifier 201, make output voltage V
OUTBe stabilized in predetermined value.
As one embodiment of the present of invention; When said output stage comprises the resistance string of nmos pass transistor, PMOS transistor and ground connection; Said on-off circuit is the PMOS transistor; Being depicted as on-off circuit of the present invention like Fig. 4 d adopts PMOS transistor and output stage 203 to be the mu balanced circuit embodiment circuit diagram of push-pull type output stage; Said on-off circuit 202 is the PMOS transistor, and said output stage 203 is the push-pull type output stage of being made up of PMOS transistor and nmos pass transistor, and resistance string is as feedback resistance or pull-up resistor.The transistorized grid of the PMOS of said on-off circuit 202 is connected with said control signal unit 204; The transistorized source electrode of the PMOS of said on-off circuit is connected with supply voltage; The PMOS transistor drain of said on-off circuit is connected with the transistorized grid of PMOS in the said push-pull type output stage.
When just powering on, the bias current of differential amplifier 201 is not also set up, and differential amplifier 201 does not also have driving force; Control signal unit 204 provides an enabling signal at this moment; The said on-off circuit 202 of conducting, on-off circuit 202 turn-offs the PMOS transistor of said output stage 203 through with moving supply voltage on the transistorized grid potential of the PMOS of said output stage 203; Make it can not output current, thereby suppressed the overshoot of said mu balanced circuit output terminal when powering on; After the bias current of differential amplifier 201 is set up; Differential amplifier 201 has had driving force, and this moment, control signal became shutdown signal, in time turn-offed said on-off circuit 202; Drive the efferent duct of output stage 203 by differential amplifier 201, make output voltage V
OUTBe stabilized in predetermined value.
As one embodiment of the present of invention, when said on-off circuit 202 was the PMOS transistor, said control signal was a low level, and then said PMOS transistor is a conducting state, thereby controls the output of said output stage 203; Said control signal is a high level, and then said PMOS transistor is a cut-off state, and the output of said output stage 203 does not receive the transistorized control of said PMOS.
As one embodiment of the present of invention, when said on-off circuit 202 was nmos pass transistor, said control signal was a high level, and then said nmos pass transistor is a conducting state, thereby controls the output of said output stage 203; Said control signal is a low level, and then said nmos pass transistor is a cut-off state, and the output of said output stage 203 does not receive the control of said nmos pass transistor.
As one embodiment of the present of invention, when said on-off circuit 202 was cmos switch, said control signal was a high level, and then said cmos switch is a conducting state, thereby controls the output of said output stage 203; Said control signal is a low level, and then said cmos switch is a cut-off state, and the output of said output stage 203 does not receive the transistorized control of said PMOS.
Be illustrated in figure 5 as a kind of another example structure of mu balanced circuit figure that prevents overshoot of the present invention.
Present embodiment is similar basically with above-mentioned Fig. 2 embodiment, and in this description difference, something in common repeats no more.
In the present embodiment, said on-off circuit 202 is controlled the grid potential of the efferent duct of said output stage 203 according to control signal when said mu balanced circuit powers on, thereby overshoot appears in the output terminal that prevents said mu balanced circuit.
As one embodiment of the present of invention; When said output stage 203 is the resistance string of PMOS transistor and ground connection; Said on-off circuit 202 is made up of PMOS transistor and cmos switch; Be depicted as on-off circuit 202 of the present invention like Fig. 6 a and adopt the single-pole double-throw switch (SPDT) of PMOS transistor and cmos switch combination and the mu balanced circuit embodiment circuit diagram that output stage is common-source stage; The transistorized grid of the PMOS of said on-off circuit 202 is connected with said control signal unit 204, and the transistorized source electrode of the PMOS of said on-off circuit 202 links to each other with power supply, and the PMOS transistor drain of said on-off circuit 202 links to each other with the transistorized grid of the PMOS of said output stage 203; Said cmos switch is connected between the transistorized grid of PMOS of output and said output stage 203 of said differential amplifier 201, accepts the control conducting of said control signal or breaks off.
When just powering on, the bias current of differential amplifier 201 is not also set up, and differential amplifier 201 does not also have driving force; Control signal unit 204 provides an enabling signal at this moment; PMOS transistor turns in the said on-off circuit 202, the cmos switch in the said on-off circuit 202 breaks off, and cuts off the transistorized grid of PMOS of said output stage 203 and being connected of differential amplifier 201; With moving supply voltage on the transistorized grid potential of the PMOS of said output stage 203; Thereby turn-offed the PMOS transistor of said output stage 203, made it can not output current, suppressed the overshoot of said mu balanced circuit output terminal when powering on; After the bias current of differential amplifier 201 is set up; Differential amplifier 201 has had driving force; This moment, control signal became shutdown signal, and the PMOS transistor in the said on-off circuit 202 breaks off, and the cmos switch in the said on-off circuit 202 is closed; Drive the PMOS transistor of output stage 203 by differential amplifier 201, make output voltage V
OUTBe stabilized in predetermined value.
As one embodiment of the present of invention; When said output stage 203 is the resistance string of nmos pass transistor and ground connection; Said on-off circuit 202 is made up of nmos pass transistor and cmos switch; Be depicted as on-off circuit 202 of the present invention like Fig. 6 b and adopt the single-pole double-throw switch (SPDT) of nmos pass transistor and cmos switch combination and the mu balanced circuit embodiment circuit diagram that output stage is the source class follower; The grid of the nmos pass transistor of said on-off circuit 202 is connected with said control signal unit 204; The source electrode of the nmos pass transistor of said on-off circuit 202 links to each other with ground, and the drain electrode of the nmos pass transistor of said on-off circuit 202 links to each other with the grid of the nmos pass transistor of said output stage 203; Said cmos switch is connected between the grid of nmos pass transistor of output and said output stage 203 of said differential amplifier 201, accepts the control conducting of said control signal or breaks off.
When just powering on, the bias current of differential amplifier 201 is not also set up, and differential amplifier 201 does not also have driving force; Control signal unit 204 provides an enabling signal at this moment; Nmos pass transistor conducting in the said on-off circuit 202, the cmos switch in the said on-off circuit 202 breaks off, the grid of nmos pass transistor and being connected of differential amplifier 201 that cut off said output stage 203; The grid potential of the nmos pass transistor of said output stage 203 is pulled down to earth potential; Thereby turn-offed the nmos pass transistor of said output stage 203, made it can not output current, suppressed the overshoot of said mu balanced circuit output terminal when powering on; After the bias current of differential amplifier 201 is set up; Differential amplifier 201 has had driving force; This moment, control signal became shutdown signal, and the nmos pass transistor in the said on-off circuit 202 breaks off, and the cmos switch in the said on-off circuit 202 is closed; Drive the nmos pass transistor of output stage 203 by differential amplifier 201, make output voltage V
OUTBe stabilized in predetermined value.
As one embodiment of the present of invention; When said output stage 203 is the resistance string of nmos pass transistor, PMOS transistor and ground connection; Said on-off circuit 202 is made up of PMOS transistor and cmos switch; Be depicted as on-off circuit 202 of the present invention like Fig. 6 c and adopt the single-pole double-throw switch (SPDT) of PMOS transistor and cmos switch combination and the mu balanced circuit embodiment circuit diagram that output stage is the push-pull type output stage; The transistorized grid of the PMOS of said on-off circuit 202 is connected with said control signal unit 204; The transistorized source electrode of the PMOS of said on-off circuit 202 links to each other with power supply, and the PMOS transistor drain of said on-off circuit 202 links to each other with the transistorized grid of the PMOS of said output stage 203; Said cmos switch is connected between the transistorized grid of PMOS of output and said output stage 203 of said differential amplifier 201, accepts the control conducting of said control signal or breaks off.
When just powering on, the bias current of differential amplifier 201 is not also set up, and differential amplifier 201 does not also have driving force; Control signal unit 204 provides an enabling signal at this moment; PMOS transistor turns in the said on-off circuit 202, the cmos switch in the said on-off circuit 202 breaks off, and cuts off the transistorized grid of PMOS of said output stage 203 and being connected of differential amplifier 201; With moving supply voltage on the transistorized grid potential of the PMOS of said output stage 203; Thereby turn-offed the PMOS transistor of said output stage 203, made it can not output current, suppressed the overshoot of said mu balanced circuit output terminal when powering on; After the bias current of differential amplifier 201 is set up; Differential amplifier 201 has had driving force; This moment, control signal became shutdown signal, and the PMOS transistor in the said on-off circuit 202 breaks off, and the cmos switch in the said on-off circuit 202 is closed; Drive the PMOS transistor of output stage 203 by differential amplifier 201, make output voltage V
OUTBe stabilized in predetermined value.
Through above embodiment, in single-stage or multistage mu balanced circuit circuit, can realize control, thereby avoid overshoot phenomenon through on-off circuit to output stage.
Be illustrated in figure 7 as a kind of low-power consumption reference circuit first example structure synoptic diagram of the present invention.
Comprise band-gap reference circuit 600, mu balanced circuit 700, quick-charging circuit 800.
Said band-gap reference circuit 600 is used for to mu balanced circuit 700 bandgap voltage reference VBG, bias current I being provided
BIASWith control signal ST.Wherein said band-gap reference circuit comprises control signal unit and reference generating circuit; Said control signal unit produces control signal, gives said reference generating circuit, said quick-charging circuit and said mu balanced circuit with said control signal; Said reference generating circuit utilizes said control signal to come normal the startup when powering on, for said mu balanced circuit provides bandgap voltage reference VBG and bias current I
BIAS
Said mu balanced circuit 700 comprises single-stage or multipole differential amplifier, first on-off circuit, output stage; Said differential amplifier receives said reference voltage and bias current, produces amplifying voltage according to said bandgap voltage reference; Said output stage produces the output VREF of said mu balanced circuit according to said amplifying voltage; Said first on-off circuit is controlled said output stage according to control signal, thereby overshoot appears in the output terminal that prevents said mu balanced circuit; When said control signal was enabling signal, said on-off circuit turn-offed said output stage; When said control signal was cut-off signals, said on-off circuit let said differential amplifier drive said output stage.
Said quick-charging circuit 800; Being used for when said reference circuit powers on is said reference generating circuit output auxiliary current; Said bandgap voltage reference can be set up fast; And the size control output auxiliary current according to said bandgap voltage reference overshoot occurs to prevent said bandgap voltage reference.
Be illustrated in figure 8 as a kind of low-power consumption reference circuit second example structure synoptic diagram of the present invention.
Present embodiment is as the embodiment of the further refinement of Fig. 7 embodiment, comprising the reference circuit 600 of refinement, and mu balanced circuit 700 and quick-charging circuit 800.
Said quick-charging circuit 800 is that a grid is connected with a fixed bias voltage, and source electrode is connected with band-gap reference circuit 600 reference voltage output ends, drain electrode and power supply V
DDThe nmos pass transistor that is connected.
As one embodiment of the present of invention; Between the drain electrode of said quick-charging circuit 800 and power supply, also comprise second switch circuit 900; One end of this second switch circuit 900 is connected with power supply; The other end is connected with the drain electrode of said quick-charging circuit 800, when said reference circuit powers on, opens or turn-off said quick-charging circuit 800 according to said control signal.
When reference circuit just powers on; The reference current of reference generating circuit is not set up, and said control signal unit produces enabling signal, said second switch circuit 900 conductings; Said quick-charging circuit 800 provides auxiliary current for the bandgap voltage reference output terminal, so that VBG sets up fast; Rising gradually along with VBG; The grid of said quick-charging circuit 800 and the voltage difference between the source electrode reduce gradually, so the auxiliary current of quick-charging circuit 800 output also reduces gradually, when VBG when stablizing; Said quick-charging circuit 800 ends, thereby prevents the VBG overshoot effectively.This moment, said quick-charging circuit 800 had leakage current; This can influence the precision of band-gap reference circuit, therefore, and when the reference current of reference generating circuit is set up; Said control signal unit provides cut-off signals; Said second switch circuit 900 turn-offs, and thoroughly breaks off quick-charging circuit 800, to prevent said quick-charging circuit 800 electric leakage is arranged.
As one embodiment of the present of invention, said second switch circuit is the PMOS transistor, and the transistorized grid of said PMOS is connected with said control signal unit, perhaps turn-offs said quick-charging circuit 800 according to said control signal conducting; The transistorized source electrode of said PMOS is connected with power supply; Said PMOS transistor drain is connected with the drain electrode of said quick-charging circuit 800.
As one embodiment of the present of invention, said second switch circuit is a nmos pass transistor, and the grid of said nmos pass transistor is connected with said control signal unit, perhaps turn-offs said quick-charging circuit 800 according to said control signal conducting; The drain electrode of said nmos pass transistor is connected with power supply; The source electrode of said nmos pass transistor is connected with the drain electrode of said quick-charging circuit 800.
As one embodiment of the present of invention, said second switch circuit is a cmos switch, and said cmos switch is connected between the drain electrode and power supply of said quick-charging circuit 800, accepts the control conducting of said control signal or breaks off said quick-charging circuit.
As one embodiment of the present of invention; First on-off circuit 701 of said mu balanced circuit 700 can during for single tube switch or cmos switch or single-pole double-throw switch (SPDT), utilize and control said first on-off circuit 701 with quick-charging circuit 800 identical control signals as Fig. 2 or the described on-off circuit of Fig. 5; Further prevent overshoot phenomenon to follow-up circuit; And can accelerate the startup of whole reference circuit through demultiplex control signal, can also simplify circuit design simultaneously, save cost.
Be illustrated in figure 9 as a kind of low-power consumption reference circuit the 3rd example structure synoptic diagram of the present invention.
Comprise band-gap reference circuit 600, mu balanced circuit 700 is as the nmos pass transistor 800 of quick-charging circuit.
Said band-gap reference circuit 600 comprises control signal unit 601.
Between the drain electrode of nmos pass transistor 800 and power supply, also comprise second switch circuit 900, this second switch circuit adopts the PMOS transistor, and first on-off circuit 701 in the said mu balanced circuit 700 adopts the PMOS transistors.
The present invention adopts the PMOS transistor 900 and nmos pass transistor 800 of series connection; Directly to the VBG charging, wherein the grid of PMOS transistor 900 is controlled by the control signal ST that control signal unit 601 produces when powering on, and source electrode connects power supply; Breaking away from zero when M3 and M4 electric current annexs point and reaches when stablizing; Control signal ST becomes high level, turn-offs PMOS transistor 900, thereby can prevent that quick-charging circuit 800 from reaching at VBG and electric leakage is arranged after stable.The grid of nmos pass transistor 800 connects fixed bias voltage V
G, source electrode meets VBG, is used to control the size that auxiliary current is provided to VBG loca 602.VBG is very low when just powering on, thus nmos pass transistor 800 can VBG be set up fast for VBG provides big charging current.Rising gradually along with VBG; The grid of nmos pass transistor 800 and source voltage difference diminish gradually; So the auxiliary current of nmos pass transistor 800 output reduces gradually, when VBG when stablize, nmos pass transistor 800 entering cut-off regions; This moment, nmos pass transistor 800 can only be exported very little leakage current; Therefore this control mode can prevent effectively that overshoot from appearring in VBG, utilizes control signal ST to turn-off PMOS transistor 900 again, thereby said nmos pass transistor 800 can not influence the precision of VBG when having guaranteed operate as normal.
The present invention adopts a PMOS transistor 701 as first on-off circuit, and the grid of PMOS transistor 701 meets control signal ST, and drain electrode meets the grid V of M9
1, source electrode connects power supply, the bias current I of mu balanced circuit when just powering on
BIASAlso do not set up, control signal is a low level, 701 conductings of PMOS transistor, and the capacitor fast charging to M9 grid level place makes V
1Near supply voltage, M9 gets into cut-off region, makes it can not export big electric current on resistance R 3 and R4, thereby has suppressed the overshoot at voltage source V REF place.Work as I
BIASDuring approaching stablizing, control signal becomes high level, and PMOS transistor 701 is turned off, the M9 conducting, and this moment, differential amplifier 702 existing enough driving forces were controlled M9, made VREF be stabilized to predetermined value.This first on-off circuit has been saved hardware spending greatly through the control signal in the multiplexing band-gap reference circuit 600, and because it is cut off when operate as normal, so it can not influence the characteristic of mu balanced circuit.
The control signal that PMOS transistor gate in first on-off circuit of the present invention and second switch circuit and nmos pass transistor grid are received is opposite signal; For example to receive high level be cut-off signal to the PMOS transistor gate; Low level is a Continuity signal; It is cut-off signal that the nmos pass transistor grid receives low level, and high level is a Continuity signal.
Shown in figure 10 is a kind of low-power consumption reference circuit the 4th example structure synoptic diagram of the present invention.
Present embodiment is similar basically with above-mentioned Fig. 7 embodiment, and in this description difference, something in common repeats no more.
In the present embodiment; Between the grid of said quick-charging circuit 800 and said fixed bias voltage, also comprise second switch circuit 900; Said second switch circuit 900 switches between said fixed bias voltage and ground according to the grid of said control signal with said quick-charging circuit 800, realizes the control to quick-charging circuit 800.When said second switch circuit 900 switches to fixing bias voltage V according to said control signal with the grid of quick-charging circuit 800
GThe time, said quick-charging circuit 800 is started working, and the output auxiliary current is to VBG; When said second switch circuit switches to ground voltage according to said control signal, turn-off quick-charging circuit 800, thereby can prevent that quick-charging circuit 800 from reaching at VBG and electric leakage is arranged after stable.
Shown in figure 11 is a kind of low-power consumption reference circuit the 5th example structure synoptic diagram of the present invention.
In the present embodiment; Said second switch circuit 900 is made up of first nmos pass transistor 901 and second nmos pass transistor 902; The grid of said first nmos pass transistor 901 is connected with said control signal unit, the drain electrode of said first nmos pass transistor 901 and said fixed bias voltage V
GLink to each other, the source electrode of said first nmos pass transistor 901 links to each other with the grid of said quick-charging circuit 800; The grid of said second nmos pass transistor 902 is connected with the designature of said control signal, and the drain electrode of said second nmos pass transistor 902 links to each other with the grid of said quick-charging circuit 800, and the source electrode of said second nmos pass transistor 902 links to each other with ground.
Shown in figure 12 is a kind of low-power consumption reference circuit the 6th example structure synoptic diagram of the present invention.
In the present embodiment, said second switch circuit 900 is made up of PMOS transistor 901 and nmos pass transistor 902, and the grid of said PMOS transistor 901 is connected with said control signal unit, the source electrode of said PNMOS transistor 901 and said fixed bias voltage V
GLink to each other, the drain electrode of said PMOS transistor 901 links to each other with the grid of said quick-charging circuit 800; The grid of said nmos pass transistor 902 is connected with said control signal unit, and the drain electrode of said nmos pass transistor 902 links to each other with the grid of said quick-charging circuit 800, and the source electrode of said nmos pass transistor 902 links to each other with ground.
For above embodiment, second switch circuit 900 can also have multiple implementation, according to the description of previous embodiment about on-off circuit, also various deformation can be arranged in this example, and the present invention does not limit the embodiment of the second switch circuit in this example.
The beneficial effect of embodiments of the invention is, can effectively prevent the overshoot of mu balanced circuit, and for reference circuit, can realize rapid charge, and can suppress the overshoot phenomenon of reference circuit equally; The scenario-frame of the embodiment of the invention is simple, and cost is low.
Through the description of above embodiment, those skilled in the art can be well understood to the present invention and can realize through hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding; Technical scheme of the present invention can be come out with the embodied of software product, this software product can be stored in a non-volatile memory medium (can be CD-ROM, USB flash disk; Portable hard drive etc.) in; Comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.
Above-described embodiment; The object of the invention, technical scheme and beneficial effect have been carried out further explain, and institute it should be understood that the above is merely embodiment of the present invention; And be not used in qualification protection scope of the present invention; All within spirit of the present invention and principle, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a mu balanced circuit that prevents overshoot comprises differential amplifier, output stage, control signal unit and on-off circuit;
Said differential amplifier is transfused to predetermined reference voltage, produces amplifying voltage according to said predetermined reference voltage;
Said output stage, the output that produces said mu balanced circuit according to said amplifying voltage;
Said control signal unit produces control signal according to the reference current of said differential amplifier; When said mu balanced circuit had just powered on, the reference current of said differential amplifier also not to be set up, and said control signal unit provides enabling signal; After the reference current of said differential amplifier was stable, said control signal unit provided cut-off signals;
Said on-off circuit is controlled said output stage according to control signal; When said control signal was enabling signal, said on-off circuit turn-offed said output stage; When said control signal was cut-off signals, said on-off circuit let said differential amplifier drive said output stage.
2. mu balanced circuit according to claim 1; It is characterized in that; When said output stage comprised the PMOS transistor, said on-off circuit was the PMOS transistor, and the transistorized grid of the PMOS of said on-off circuit is connected with said control signal unit; The transistorized source electrode of the PMOS of said on-off circuit links to each other with power supply, and the PMOS transistor drain of said on-off circuit links to each other with the transistorized grid of the PMOS of said output stage;
Perhaps said on-off circuit is a nmos pass transistor; The grid of the nmos pass transistor of said on-off circuit is connected with said control signal unit; The drain electrode of the nmos pass transistor of said on-off circuit is connected with power supply, and the source electrode of said nmos pass transistor is connected with the transistorized grid of the PMOS of said output stage;
Perhaps said on-off circuit is a cmos switch, and said cmos switch is connected between the transistorized grid of PMOS and power supply of said output stage, is controlled the conducting or the disconnection of said cmos switch by said control signal.
3. mu balanced circuit according to claim 1; It is characterized in that; When said output stage comprised nmos pass transistor, said on-off circuit was the PMOS transistor, and the transistorized grid of the PMOS of said on-off circuit is connected with said control signal unit; The PMOS transistor drain of said on-off circuit links to each other with ground, and the transistorized source electrode of the PMOS of said on-off circuit links to each other with the grid of the nmos pass transistor of said output stage;
Perhaps said on-off circuit is a nmos pass transistor; The grid of the nmos pass transistor of said on-off circuit is connected with said control signal unit; The drain electrode of the nmos pass transistor of said on-off circuit is connected with the grid of the nmos pass transistor of said output stage, and the source electrode of said nmos pass transistor is connected with ground;
Perhaps said on-off circuit is a cmos switch, and said cmos switch is connected between the grid and ground of nmos pass transistor of said output stage, is controlled the conducting of said cmos switch or is broken off by said control signal.
4. mu balanced circuit according to claim 1; It is characterized in that; When said output stage comprised the PMOS transistor, said on-off circuit switched the transistorized grid of said output stage PMOS according to said control signal between the output of power supply and said differential amplifier.
5. mu balanced circuit according to claim 1; It is characterized in that; When said output stage comprised nmos pass transistor, said on-off circuit switched the transistorized grid of said output stage PMOS according to said control signal between the output of ground and said differential amplifier.
6. a low-power consumption reference circuit comprises band-gap reference circuit and mu balanced circuit, it is characterized in that this reference circuit also comprises quick-charging circuit;
Said band-gap reference circuit provides bandgap voltage reference, bias current and control signal to said mu balanced circuit; Wherein said band-gap reference circuit comprises control signal unit and reference generating circuit;
Said control signal unit reference current according to band-gap reference circuit when said reference circuit powers on produces control signal, gives said reference generating circuit, said quick-charging circuit and said mu balanced circuit with said control signal; When the reference current of band-gap reference circuit was not set up, said control signal unit provided enabling signal; When the reference current of band-gap reference circuit was set up, said control signal unit provided cut-off signals;
Said reference generating circuit utilizes said control signal to come normal the startup when powering on, for said mu balanced circuit provides bandgap voltage reference and bias current;
Said mu balanced circuit comprises differential amplifier, first on-off circuit, output stage; Said differential amplifier receives said bandgap voltage reference and bias current, produces amplifying voltage according to said bandgap voltage reference; Said output stage, the output that produces said mu balanced circuit according to said amplifying voltage; Said first on-off circuit is controlled said output stage according to said control signal, and when said control signal was enabling signal, said on-off circuit turn-offed said output stage; When said control signal was cut-off signals, said on-off circuit let said differential amplifier drive said output stage;
Said quick-charging circuit; Being used for when said reference circuit powers on is said reference generating circuit output auxiliary current; Said bandgap voltage reference can be set up fast; And the size control output auxiliary current according to said bandgap voltage reference overshoot occurs to prevent said bandgap voltage reference.
7. reference circuit according to claim 6 is characterized in that, said quick-charging circuit is that a grid is connected with a fixed bias voltage, and source electrode is connected with said bandgap voltage reference, the nmos pass transistor that drain electrode is connected with power supply.
8. reference circuit according to claim 7; It is characterized in that; Between the drain electrode of said quick-charging circuit and power supply, also comprise the second switch circuit; One end of this second switch circuit is connected with power supply, and the other end is connected with the drain electrode of said quick-charging circuit, when said reference circuit powers on, opens or turn-off said quick-charging circuit according to said control signal.
9. reference circuit according to claim 8; It is characterized in that; Said second switch circuit is the PMOS transistor; The transistorized grid of said PMOS is connected with said control signal unit, and the transistorized source electrode of said PMOS is connected with power supply, and said PMOS transistor drain is connected with the drain electrode of said quick-charging circuit;
Perhaps said second switch circuit is a nmos pass transistor, and the grid of said nmos pass transistor is connected with said control signal unit; The drain electrode of said nmos pass transistor is connected with power supply; The source electrode of said nmos pass transistor is connected with the drain electrode of said quick-charging circuit;
Perhaps said second switch circuit is a cmos switch, and said cmos switch is connected between the drain electrode and power supply of said quick-charging circuit, is controlled the conducting or the disconnection of said cmos switch by said control signal.
10. reference circuit according to claim 7; It is characterized in that; Between the grid of said quick-charging circuit and said fixed bias voltage, also comprise the second switch circuit, said second switch circuit switches between said fixed bias voltage and ground according to the grid of said control signal with the nmos pass transistor of said quick-charging circuit.
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| CN2009100833847A CN101881982B (en) | 2009-05-05 | 2009-05-05 | Voltage stabilizing circuit for preventing overshoot and reference circuit |
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| CN2009100833847A CN101881982B (en) | 2009-05-05 | 2009-05-05 | Voltage stabilizing circuit for preventing overshoot and reference circuit |
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Owner name: RENESAS INTEGRATED CIRCUIT DESIGN (BEIJING) CO., L Free format text: FORMER OWNER: RENESAS ELECTRONICS (CHINA) CO., LTD. Effective date: 20130521 |
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Effective date of registration: 20130521 Address after: 100191 Haidian District, Zhichun Road, No. 27 quantum core, layer 7, layer Patentee after: RENESAS IC DESIGN (BEIJING) CO., LTD. Address before: 100191, Haidian District, Zhichun Road, No. 27, No. 11, building 7, 8,, 9 Patentee before: Renesas Electronics (China) Co., Ltd. |