CN101645257B - Image display system with low-voltage drop voltage stabilizing circuit - Google Patents
Image display system with low-voltage drop voltage stabilizing circuit Download PDFInfo
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- CN101645257B CN101645257B CN 200810145855 CN200810145855A CN101645257B CN 101645257 B CN101645257 B CN 101645257B CN 200810145855 CN200810145855 CN 200810145855 CN 200810145855 A CN200810145855 A CN 200810145855A CN 101645257 B CN101645257 B CN 101645257B
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Abstract
The invention relates to an image display system, which comprises a low-voltage drop voltage stabilizing circuit used for receiving an input voltage and providing a stable output voltage. The low- voltage drop voltage stabilizing circuit comprises a regulating circuit, a first switch, a current source circuit and an inverting circuit, wherein the regulating circuit is provided with a regulating circuit input terminal, a regulating circuit output terminal and a regulating circuit control terminal; the first switch selectively forms a short circuit/an open circuit by being switched on/off; the current source circuit provides a constant current for both the regulating circuit control terminal and the regulating circuit output control; and the inverting circuit is provided with an inverting circuit input terminal coupled with the regulating circuit control terminal and inverts the output voltage from the regulating circuit output terminal. The regulating circuit control terminal adjusts the output voltage according to the received control voltage.
Description
Technical field
The present invention relates to a kind of image display system, particularly a kind of take the image display system of negative circuit as the low-pressure drop voltage-stabilizing circuit that the master was formed.
Background technology
In the known technology, usually utilize voltage regulator circuit that stable voltage source is provided.Voltage regulator circuit is for specific application-can divide into different kinds.For example, voltage regulator circuit can produce pressure drop voltage (drop-out voltage).Pressure drop voltage is the difference between input voltage and output voltage, in order to the normal operation of holding circuit.In circuit, if when the voltage that provides is higher than required minimum sustaining voltage, with the waste that virtually causes on the power.In Another Application, voltage regulator circuit also can be low-pressure drop voltage-stabilizing circuit (lowdrop-out voltage regulator, LDO).Low-pressure drop voltage-stabilizing circuit is a kind of of voltage regulator circuit, and it act as the less pressure drop voltage of generation, so that the output voltage after regulating is near input voltage.Low-pressure drop voltage-stabilizing circuit is mainly used in the low-voltage source device, especially with the device of battery as power supply, such as mobile phone, digital camera, personal digital assistant, notebook computer, desktop PC, TV, vehicle display, aviation with display or GPS etc.
Figure 1A shows that the calcspar of connection relationship between each circuit blocks falls in the mu balanced circuit 100 in known low-pressure.Low-pressure drop voltage-stabilizing circuit 100 comprises circuit for regulating and controlling 102, bleeder circuit 104 and error amplifier 106.The input voltage V that circuit for regulating and controlling 102 receives from the outside
IN, and produce output voltage V
OUTBleeder circuit 104 receives the output voltage V that circuit for regulating and controlling 102 provides
OUT, and be sent to error amplifier 106, and error amplifier 106 is again with this output voltage V
OUTFeed-in circuit for regulating and controlling 102.
Figure 1B shows that the circuit diagram of mu balanced circuit 100 falls in known low-pressure.Low-pressure drop voltage-stabilizing circuit 100 comprises circuit for regulating and controlling 102 (take P type metal oxide semiconductor field effect transistor (PMOS) by example), bleeder circuit 104 (being comprised of resistance 110 and 112), error amplifier 106 and other circuit component.Low-pressure drop voltage-stabilizing circuit 100 receives input voltage V at input end
IN, and provide output voltage V after regulating at output terminal
OUTThe grid of PMOS102 (gate) receives the output voltage from error amplifier 106.The positive input terminal of error amplifier 106 receives reference voltage signal V
REF, negative input end receives the voltage of feedbacking from bleeder circuit 104.Bleeder circuit 104 is according to its resistance value that forms, and the ratio contracting reduces the output voltage V of pressure drop mu balanced circuit 100
OUT, it is fed into the negative input end of error amplifier 106, supply and reference voltage signal V
REFMake comparisons, error amplifier 106 thereby generation regulation and control voltage are with the unstable output voltage of compensation low dropout mu balanced circuit 100.
If output voltage V is according to embodiments of the invention, the low-pressure drop voltage-stabilizing circuit of the image display system that proposes falls mu balanced circuit compared to known low-pressure, has simple circuit design, and do not need error amplifier and bleeder circuit, thereby the characteristic that has low power consumption and stable output is provided.Therefore, this low-pressure drop voltage-stabilizing circuit is particularly suitable for the environment of low burning voltage and low power consuming, and for example this low-pressure drop voltage-stabilizing circuit is particularly suitable for the design of low temperature polycrystalline silicon (LTPS) panel.
The above embodiments are in order to describe the present invention, and right the present invention is not limited to the description of above specific embodiment, and claim of the present invention is intended to comprise modification and the variation of all spirit according to the invention and scope.
Make it keep stable.
Yet known low-pressure is fallen mu balanced circuit 100 employed error amplifiers 106 and is consumed quite high power, and the use of bleeder circuit 104 also affects output voltage V
OUTDegree of stability.Because the unfavorable factor of said elements has limited known low-pressure and has fallen the application of mu balanced circuit 100 in the image display system design.
Therefore, the present invention provides a kind of low-pressure drop voltage-stabilizing circuit in the design of image display system, solves the disappearance of above-mentioned mentioned known technology to use less element, and obtains better energy-saving efficiency, regulated output voltage and reduce operating temperature.
Summary of the invention
The invention provides a kind of image display system with low-pressure drop voltage-stabilizing circuit, in order to receiving input voltage, and provide and be lower than input voltage and stable output voltage.
In embodiments of the invention, image display system comprises a low-pressure drop voltage-stabilizing circuit, in order to receiving input voltage, and provides stable output voltage.Low-pressure drop voltage-stabilizing circuit comprises circuit for regulating and controlling, the first switch, current source circuit and negative circuit.
Circuit for regulating and controlling has circuit for regulating and controlling input end, circuit for regulating and controlling output terminal and circuit for regulating and controlling control end.The first switch optionally forms short/open by connecting/cutting off.Current source circuit provides decides electric current to circuit for regulating and controlling control end and circuit for regulating and controlling output terminal.Negative circuit has the negative circuit input end that couples with the circuit for regulating and controlling output terminal, and with the negative circuit output terminal of circuit for regulating and controlling control end coupling, the in the future output voltage of Self-controlled circuit output end counter-rotating, wherein the circuit for regulating and controlling control end is adjusted output voltage according to the control voltage that receives.
When reading in conjunction with subsidiary schematic diagram, by the description of following specific embodiment, will more understand the method for construction of the present invention and operation, with and additional purpose and advantage.
Description of drawings
Figure 1A falls the calcspar of mu balanced circuit for showing known low-pressure;
The circuit diagram of mu balanced circuit falls in Figure 1B for the known low-pressure that shows Figure 1A;
Fig. 2 A is the low-pressure drop voltage-stabilizing circuit that comprises of demonstration image display system of the present invention and the calcspar of display panel;
Fig. 2 B is the according to an embodiment of the invention circuit diagram of the low-pressure drop voltage-stabilizing circuit that comprises of image display system of demonstration;
Fig. 3 A is that the circuit diagram under the decompression mode of mu balanced circuit falls in key diagram 2B mesolow;
Fig. 3 B is that the circuit diagram under the voltage stabilizing pattern of mu balanced circuit falls in key diagram 2B mesolow; And
The circuit diagram of the low-pressure drop voltage-stabilizing circuit that Fig. 4 comprises for image display system according to another embodiment of the present invention.
Embodiment
Fig. 2 A is in the embodiments of the invention, the calcspar that comprises the image display system 20 of low-pressure drop voltage-stabilizing circuit 200 and display panel 201, it shows the annexation of low-pressure drop voltage-stabilizing circuit 200 and display panel 201, and the connection relationship between each circuit blocks in the low-pressure drop voltage-stabilizing circuit 200.Image display system 20 can be mobile phone, digital camera, personal assistant (PDA), notebook computer, desktop PC, TV, vehicle display, GPS (GPS) or Portable DVD player.
Low-pressure drop voltage-stabilizing circuit 200 has input voltage V
INWith output voltage V
OUT, and comprise its circuit for regulating and controlling 202 blocks and negative circuit 212 blocks.Circuit for regulating and controlling 202 receives input voltage V
IN, and produce output voltage V
OUTSpecifically, output voltage V
OUTBe lower than input voltage V
IN, and output voltage V
OUTValue depends on different display applications.The output voltage V that negative circuit 212 receives from circuit for regulating and controlling 202
OUT, with its reversal of poles feed-in circuit for regulating and controlling 202 then, be positioned at the output voltage V of circuit for regulating and controlling 202 output terminals with compensation
OUTChange.
Fig. 2 B is the detailed circuit diagram that an embodiment of mu balanced circuit 200 falls in Fig. 2 A mesolow.In this embodiment, low-pressure drop voltage-stabilizing circuit 200 comprises circuit for regulating and controlling 202, the first switch 204, current source circuit 205 and negative circuit 212.
At first explanation, the first trigger pip 22 is the opposite square-wave signal of consistent logic level of cycle with the second trigger pip 24, wherein each cycle of these two trigger pips all has the first isometric period and the second period.For example, in the first period, the first trigger pip 22 is positioned at its high levle part 22a, and the second trigger pip 24 is positioned at its low level part 24a, so when the first period finished to enter for the second period simultaneously, the first trigger pip 22 is converted to its low level part 22b, and the second trigger pip 24 is converted to its high levle part 24b.
Circuit for regulating and controlling 202 has circuit for regulating and controlling input end 202a, circuit for regulating and controlling output terminal 202b and circuit for regulating and controlling control end 202c.Circuit for regulating and controlling input end 202a receives the input voltage V from external circuit
IN, control end 202c receives control voltage, adjusts according to this output voltage V that output terminal 202b provides
OUTThe first switch 204 is arranged between circuit for regulating and controlling input end 202a and the circuit for regulating and controlling control end 202c, switches on or off according to the second trigger pip 24.
In the present embodiment, current source circuit 205 also comprises second switch 206 and the 3rd switch 208.Second switch 206 is arranged between circuit for regulating and controlling control end 202c and the ground connection, switch on or off according to the first trigger pip 22 that receives, when it is connected, form constant current source bias voltage loop between circuit for regulating and controlling control end 202c and the ground connection, and produce a particular gate voltage.The 3rd switch 208 is arranged between circuit for regulating and controlling output terminal 202b and the ground connection, also switch on or off according to the first trigger pip 22 that receives, when it is connected, form constant current source bias voltage loop between circuit for regulating and controlling output terminal 202b and the ground connection, and produce a specific output voltage.
In the present embodiment, negative circuit 212 also comprises the first phase inverter 213, the 4th switch 214 and the first electric capacity 210.In other embodiment, the first phase inverter 213 can be reached NOR (anti-or) lock of identical function or NAND (anti-and) lock and replace it.The 4th switch 214 is arranged between the input end and output terminal of the first phase inverter 213, when switching on or off in order to receive the second trigger pip 24 when it, optionally make and form short circuit or open circuit between the input end of the first phase inverter 213 and the output terminal, wherein when short circuit forms, set bias voltage and set up the negative circuit working point.The first electric capacity 210 is arranged between the first phase inverter 213 input ends and the negative circuit input end 212a, and it receives the output voltage V from circuit for regulating and controlling output terminal 202b
OUT, and send it to negative circuit 212.
In addition, in another embodiment, low-pressure drop voltage-stabilizing circuit 200 further comprises the second electric capacity 232 and the 3rd electric capacity 234.The second electric capacity 232 is arranged between negative circuit output terminal 212b and the ground connection, in order to avoid high frequency response.The 3rd electric capacity 234 is arranged between negative circuit output terminal 212b and the circuit for regulating and controlling control end 202c.Need be appreciated that, depend on the design consideration, the second electric capacity 232 and the 3rd electric capacity 234 can be arranged at inside or the outside of low-pressure drop voltage-stabilizing circuit 200.
In sum, in the first period, the first trigger pip 22 is positioned at high levle part 22a, and the second trigger pip 24 is positioned at low level part 24a, and at this moment, the first switch 204, second switch 206, the 3rd switch 208 and the 4th switch 214 are all connection; And in the second period, the first trigger pip 22 is positioned at low level part 22b, and the second trigger pip 24 is positioned at high levle part 24b, and at this moment, the first switch 204, second switch 206, the 3rd switch 208 and the 4th switch 214 are all cut-out.
In the present embodiment, circuit for regulating and controlling 202 is embodied as N-type thin film transistor (TFT) (NTFT), wherein the drain electrode of N-type thin film transistor (TFT) 202 as circuit for regulating and controlling input end 202a, source electrode as output terminal 202b and grid as control end 202c.Second switch 206 and the 3rd switch 208 can be embodied as N-type or P type thin film transistor (TFT).Second switch 206 in the present embodiment is embodied as N-type thin film transistor (TFT) 206, and its source electrode is connected to ground connection, and drain electrode is connected to circuit for regulating and controlling control end 202c; The 3rd switch 208 also is embodied as the N-type thin film transistor (TFT), and its source electrode is connected to ground connection equally, and drain electrode then is connected to circuit for regulating and controlling output terminal 202b.The grid of the grid of N-type thin film transistor (TFT) 206 and N-type thin film transistor (TFT) 208 receives respectively the first trigger pip 22 and switches on or off according to this, when the first trigger pip 22 is positioned at high levle part 22a, second switch 206 and the 3rd switch 208 are for connecting, and when the first trigger pip 22 was positioned at low level part 22b, second switch 206 and the 3rd switch 208 were for cutting off.
As can be known above-mentioned by induction-arrangement, among the embodiment shown in Fig. 2 B, switching on or off by the second trigger pip 24 of the first switch 204 and the 4th switch 214 controlled, and switching on or off by the first trigger pip 22 of second switch 206 and the 3rd switch 208 controlled.When the second trigger pip 24 was positioned at low level 24a, the first switch 204 and the 4th switch 214 were set as connection, otherwise then for cutting off.When the first trigger pip 22 was positioned at high levle 22a, second switch 206 and the 3rd switch 208 were set as connection, otherwise then for cutting off.
The described trigger pip control mode of leading portion is so that low-pressure drop voltage-stabilizing circuit 200 can be divided into step-down and two kinds of operating modes of voltage stabilizing.Decompression mode carries out input voltage V
INLower voltage operation, have the input voltage of being lower than V with generation
INOutput voltage V
OUTThe voltage stabilizing pattern is carried out output voltage V
OUTVoltage stabilization operation, so that stable and operational voltage to be provided.Relation between the decompression mode of the connection of the first switch 204, second switch 206, the 3rd switch 208 and the 4th switch 214/cut-out and low-pressure drop voltage-stabilizing circuit/voltage stabilizing pattern is as follows with detailed description.
With reference to figure 3A, for the equivalent electrical circuit of mu balanced circuit 200 under decompression mode falls in the embodiments of the invention mesolow.Under this decompression mode, second switch 206 is the N-type thin film transistor (TFT), and the 3rd switch 208 also is the N-type thin film transistor (TFT).During this decompression mode, the first trigger pip 22 is positioned at high levle 22a, and the second trigger pip 24 is positioned at low level 24a.Therefore, the first switch 204, the 4th switch 214, N-type thin film transistor (TFT) 206 and N-type thin film transistor (TFT) 208 all are to connect.The first phase inverter 213 (details can with reference to figure 2B) is connected because of the 4th switch 214 and is short-circuited, so that the voltage of negative circuit 212 input ends equals the voltage of negative circuit 212 output terminals.
In addition, when the first switch 204 is connected, it can be considered as an equivalent resistance.Therefore, the input voltage V of circuit for regulating and controlling input end 202a
INBy the first switch 204 pressure drop occuring, and produces grid voltage V at circuit for regulating and controlling control end 202c
GAgain according to the relationship between field-effect transistor electric current and voltage:
I
D＝K*(V
GS-V
TH)
2
I wherein
DBe drain current, flow to source electrode 202b from the drain electrode 202a of N-type thin film transistor (TFT) 202, and with the field-effect transistor entity size of (NTFT belongs to this type of), that is width/height ratio is directly proportional; K is a constant; V
GSBe lock-source voltage; V
THBeing critical voltage, is to be a constant.
Therefore, according to the output voltage V of wishing to get
OUT(V
S), can set above-mentioned grid voltage V
GWith the electric current I by N-type thin film transistor (TFT) 202
DNeed be appreciated that I
DThe 3rd switching current I of N-type thin film transistor (TFT) 208 equals to flow through
3Therefore the entity size of N-type thin film transistor (TFT) 208 determines I
DCan obtain V by above-mentioned mathematical expression
S, i.e. output voltage V
OUT
With reference to figure 3B, it shows that the equivalent electrical circuit of mu balanced circuit 200 under the voltage stabilizing pattern falls in above-described embodiment mesolow.Under this pattern, the first trigger pip 22 is positioned at low level 22b, and the second trigger pip 24 is positioned at high levle 24b, therefore, the first switch 204 shown in Fig. 2 B, the 4th switch 214, N-type thin film transistor (TFT) 206 and N-type thin film transistor (TFT) 208 all cut off (for the annexation of actual circuit part of having an effect can clearlyer be presented, therefore do not show aforementioned components among Fig. 3 B).Output voltage V
OUTCan be inclined to because of its load that drives and rise or descend.Work as output voltage V
OUTDuring decline, the negative circuit 212 of position on the feedback loop that is coupled between circuit for regulating and controlling output terminal 202b and the circuit for regulating and controlling control end 202c, the voltage of its input end is along with decline.Produce the working point that bias voltage sets according to connecting by the 4th switch 214 under the operating principle of phase inverter and the above-mentioned decompression mode, when voltage drop that the negative circuit input end receives, the first phase inverter 213 is promoted to noble potential with the voltage that is about to the negative circuit output terminal, that is the voltage of negative circuit output terminal rises with the voltage drop of negative circuit input end.Therefore, the grid voltage V that the circuit for regulating and controlling control end 202c that is connected with the negative circuit output terminal senses
GAlso rise thereupon.As grid voltage V
GDuring rising, that is lock source voltage V
GSBecome large, according to aforesaid mathematical expression, drain current I
DThereby increase with output voltage V that compensating load is caused
OUTDecline, thereby so that output voltage V
OUTGo up to previous stable magnitude of voltage.Work as output voltage V
OUTWhen tendency rises, according to identical circuit operation principle, thus so that output voltage V
OUTReturn and fall.
With reference to figure 4, it shows according to another embodiment of the present invention, the circuit diagram of the low-pressure drop voltage-stabilizing circuit 200 of image display system 20.On the structure, Fig. 4 is similar to Fig. 2 B circuit structure, its difference is that the circuit for regulating and controlling 202 ' among Fig. 4 is P type thin film transistor (TFT), but not the N-type thin film transistor (TFT) 202 shown in Fig. 2 B, and provide another second identical phase inverter 213 ' to be connected in series mutually with the first phase inverter 213 among this embodiment.Moreover, in the circuit running, the low-pressure drop voltage-stabilizing circuit 200 of Fig. 4 also has step-down and two kinds of operating modes of voltage stabilizing, its difference is that the required polarity of voltage of P type thin film transistor (TFT) 202 ' running is opposite with N-type thin film transistor (TFT) 202, therefore the second phase inverter 213 ' that increases namely is used for reversal voltage polarity, so that the low-pressure drop voltage-stabilizing circuit 200 of Fig. 4 and Fig. 2 B is reached the effect of equal step-down and voltage stabilizing.The source electrode of P type thin film transistor (TFT) 202 ' couples circuit for regulating and controlling input end 202 ' a, and drain electrode couples circuit for regulating and controlling output terminal 202 ' b, and grid couples circuit for regulating and controlling control end 202 ' c.The 4th switch 214 is connected between the first phase inverter 213 input ends and the second phase inverter 213 ' output terminal.
According to embodiments of the invention, the low-pressure drop voltage-stabilizing circuit of the image display system that proposes falls mu balanced circuit compared to known low-pressure, has simple circuit design, and do not need error amplifier and bleeder circuit, thereby the characteristic that has low power consumption and stable output is provided.Therefore, this low-pressure drop voltage-stabilizing circuit is particularly suitable for the environment of low burning voltage and low power consuming, and for example this low-pressure drop voltage-stabilizing circuit is particularly suitable for the design of low temperature polycrystalline silicon (LTPS) panel.
The above embodiments are in order to describe the present invention, and right the present invention is not limited to the description of above specific embodiment, and claim of the present invention is intended to comprise modification and the variation of all spirit according to the invention and scope.
Symbol description
Mu balanced circuit 100 circuit for regulating and controlling (PMOS) 102 fall in known low-pressure
Resistance 110,112 image display systems 20
Low-pressure drop voltage-stabilizing circuit 200 display panels 201
Circuit for regulating and controlling (NTFT) 202 circuit for regulating and controlling input end 202a
Circuit for regulating and controlling output terminal 202b circuit for regulating and controlling control end 202c
Circuit for regulating and controlling (PTFT) 202 ' circuit for regulating and controlling input end 202 ' a
Circuit for regulating and controlling output terminal 202 ' b circuit for regulating and controlling control end 202 ' c
The first switch 204 second switches (NTFT) 206
The 3rd switch (the 2nd NTFT) 208 first electric capacity 210
Negative circuit 212,212 ' negative circuit input end 212a
Negative circuit output terminal 212b the first phase inverter 213
The second phase inverter 213 ' the 4th switch 214
N-type thin film transistor (TFT) 222 P type thin film transistor (TFT)s 224
The second electric capacity 232 the 3rd electric capacity 234.
Claims (10)
1. image display system comprises:
One low-pressure drop voltage-stabilizing circuit receives an input voltage, and an output voltage is provided, and described low-pressure drop voltage-stabilizing circuit comprises:
One circuit for regulating and controlling has a circuit for regulating and controlling input end receiving described input voltage, and a circuit for regulating and controlling output terminal is providing described output voltage, and a circuit for regulating and controlling control end;
One first switch is arranged between described circuit for regulating and controlling input end and the described circuit for regulating and controlling control end, the connection of corresponding described the first switch/cut-out, and described circuit for regulating and controlling control end optionally receives described input voltage;
One current source circuit; And
One negative circuit, has a negative circuit input end that couples with described circuit for regulating and controlling output terminal, and a negative circuit output terminal that couples with described circuit for regulating and controlling control end, described negative circuit receives described output voltage, to provide a control voltage to described circuit for regulating and controlling control end;
Wherein in one first period, described current source circuit is decided electric current and produce second between described circuit for regulating and controlling output terminal and ground connection to decide electric current in generation first between described circuit for regulating and controlling control end and the ground connection, and the described control voltage that described negative circuit provides equals described output voltage; And
Wherein in one second period, described current source circuit stops to provide described first, second to decide electric current, and described negative circuit is adjusted described control voltage for descending/rising in response to the rise/fall of described output voltage.
2. image display system according to claim 1, wherein said current source circuit comprises:
One second switch is arranged between described circuit for regulating and controlling control end and the ground connection, and the connection of corresponding described second switch/cut-out produces described first and decides electric current between described circuit for regulating and controlling control end and ground connection when connecting; And
One the 3rd switch is arranged between described circuit for regulating and controlling output terminal and the ground connection, and the connection of corresponding described the 3rd switch/cut-out produces described second and decides electric current between described circuit for regulating and controlling output terminal and ground connection when connecting.
3. image display system according to claim 1, wherein said negative circuit also comprises:
One first phase inverter has the one first phase inverter input end that couples with described negative circuit input end, and one first inverter output that couples with described negative circuit output terminal;
One first electric capacity has two nodes, and a node and described negative circuit input end couple, and another node and described the first phase inverter input end couple; And
One the 4th switch, be arranged between described the first phase inverter input end and described the first inverter output, the connection of corresponding described the 4th switch/cut-out optionally causes between described the first phase inverter input end and described the first inverter output and forms short/open.
4. image display system according to claim 3, wherein said circuit for regulating and controlling is a P type thin film transistor (TFT), and also comprises one second phase inverter that is connected in series with described the first phase inverter in described low-pressure drop voltage-stabilizing circuit.
5. image display system according to claim 3, wherein when described the first switch, described second switch, described the 3rd switch, described the 4th switch all are on-state in described the first period, cause the generation of circuit for regulating and controlling output terminal less than the output voltage of described input voltage; When described the first switch, described second switch, described the 3rd switch, described the 4th switch all are dissengaged positions in described the second period, cause described circuit for regulating and controlling control end to compensate the variation of described output voltage.
6. image display system according to claim 5, also comprise one first trigger pip and one second trigger pip, have respectively one first level and one second level, described the second trigger pip is depended in the connection of wherein said the first switch and the 4th switch/cut-out, and described the first trigger pip is depended in the connection of described second switch and the 3rd switch/cut-out.
7. image display system according to claim 6, wherein in described the first period, described the first trigger pip is described the first level, and described the second trigger pip is described the second level, and in described the second period, described the first trigger pip is described the second level, and described the second trigger pip is described the first level.
8. image display system according to claim 1 also comprises one second electric capacity, is coupled between described negative circuit output terminal and the ground connection, to avoid high frequency response.
9. image display system according to claim 1 also comprises a display panel that couples with described low-pressure drop voltage-stabilizing circuit, for receiving described output voltage.
10. image display system according to claim 1, wherein said image display system are mobile phone, digital camera, personal assistant, notebook computer, TV, vehicle display, aviation with display, GPS or Portable DVD player.
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|---|---|---|---|
| CN 200810145855 CN101645257B (en) | 2008-08-07 | 2008-08-07 | Image display system with low-voltage drop voltage stabilizing circuit |
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|---|---|---|---|
| CN 200810145855 CN101645257B (en) | 2008-08-07 | 2008-08-07 | Image display system with low-voltage drop voltage stabilizing circuit |
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| CN101645257B true CN101645257B (en) | 2013-03-06 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2136491Y (en) * | 1992-09-10 | 1993-06-16 | 陈连海 | Voltage controlled micro differential voltage linear regulated power supply |
| CN1870436A (en) * | 2005-05-25 | 2006-11-29 | 台湾积体电路制造股份有限公司 | Signal alignment circuit, drawing down circuit and pulling up circuit |
-
2008
- 2008-08-07 CN CN 200810145855 patent/CN101645257B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2136491Y (en) * | 1992-09-10 | 1993-06-16 | 陈连海 | Voltage controlled micro differential voltage linear regulated power supply |
| CN1870436A (en) * | 2005-05-25 | 2006-11-29 | 台湾积体电路制造股份有限公司 | Signal alignment circuit, drawing down circuit and pulling up circuit |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2002-366237A 2002.12.20 |
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