CN101877632B - Power output control circuit and link state control system - Google Patents
Power output control circuit and link state control system Download PDFInfo
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- CN101877632B CN101877632B CN201010207733.4A CN201010207733A CN101877632B CN 101877632 B CN101877632 B CN 101877632B CN 201010207733 A CN201010207733 A CN 201010207733A CN 101877632 B CN101877632 B CN 101877632B
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Abstract
The embodiment of the invention discloses a power output control circuit and a link state control system, and relates to the technical field of mobile communication. The invention is used for solving the problem of failure of accurately controlling the power output. The power output control circuit comprises a switching circuit, a voltage-regulator diode, an N-MOSE tube and a P-MOSE tube, wherein the input end of the switching circuit is connected with a signal input end, and signals input by the signal input end control the on-off state of the switching circuit; the output end of the switching circuit is connected with the grid of the N-MOSE tube; the drain of the N-MOSE tube is connected with a signal output end; the output end of the switching circuit is also connected with the positive pole of the voltage-regulator diode; the negative pole of the voltage-regulator diode is connected with the grid of the P-MOSE tube; the drain of the P-MOSE tube is connected with the signal output end; the negative pole of the voltage-regulator diode is also connected with a power supply; the source of the P-MOSE tube is connected with the power supply; and the source of the N-MOSE is grounded. The invention can accurately control the power output.
Description
Technical field
The present invention relates to mobile communication technology field, relate in particular to a kind of power supply output control circuit and Link State control system.
Background technology
Time division duplex (Time Division Duplexing, TDD) technology is one of duplex technology using at mobile communication technology.Under TDD mode of operation, uplink and downlink communication signal uses the different time-gap of same frequency channels, therefore necessary time-sharing work, and, in the work of downlink communication link, uplink communication link is in wait state; In the work of uplink communication link, downlink communication link is in wait state.In the handoff procedure of uplink and downlink communication signal, certainly exist the handoff procedure of signal and power supply, this just needs a set of perfect linkage circuit to coordinate this course of work.Traditional control mode is the radiofrequency signal that uplink and downlink communication link is switched in the baseband signal control that produced by baseband processor, controls the power supply of the key position of uplink and downlink communication link simultaneously.
Existing method needs baseband signal to be strictly synchronized with the transmitting-receiving sequential of TDD, if controlling sequential goes wrong, must cause uplink and downlink communication link to be worked simultaneously, be that radio frequency converting switch exists uplink and downlink signal of communication simultaneously, not only upset the communication sequential of TDD system, also increase the burden of radio frequency converting switch simultaneously, even had the possibility of damaging radio frequency converting switch.
Summary of the invention
The embodiment of the present invention provides a kind of power supply output control circuit, for improving the accuracy of controlling power supply output.
A kind of power supply output control circuit, this power supply output control circuit comprises: switching circuit, voltage stabilizing didoe, N-MOS pipe and P-MOS pipe;
The input of described switching circuit is connected with signal input part, the break-make of switching circuit described in the signal controlling of signal input part input; The output of described switching circuit is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switching circuit is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
The present invention utilizes described in the level signal control that power supply output control circuit receives voltage and the operating state of each components and parts in power supply output control circuit, and determines whether described power supply output control circuit carries out power supply output.Visible, can control accurately power supply output control circuit by the present invention and carry out the output of power supply.
The embodiment of the present invention also provides a kind of downlink status control system, for improving according to the accuracy of TDD transmitting-receiving sequencing control down link operating state.
A kind of downlink communication Link State control system, this downlink status control system comprises: baseband processor, above-mentioned power supply output control circuit and TDD communicating system descending link components and parts;
Described baseband processor is connected with the input of the switching circuit in described power supply output control circuit, and the P-MOS pipe in described power supply output control circuit is connected with TDD communicating system descending link components and parts with the drain electrode of N-MOS pipe.
The present invention utilizes described in the TDD up-downgoing control signal control of described baseband processor output voltage and the operating state of each components and parts in power supply output control circuit, and determine that this power supply output control circuit is whether to the power supply of downlink communication link, make the in running order or halted state of downlink communication link.Visible, can improve according to the accuracy of TDD transmitting-receiving sequencing control down link operating state by the present invention.
The embodiment of the present invention also provides a kind of power supply output control circuit, for providing another kind can accurately control the circuit of power supply output.
A kind of power supply output control circuit, this power supply output control circuit comprises: reverser, switching circuit, voltage stabilizing didoe, N-MOS pipe and P-MOS pipe;
The input of described reverser is connected with signal input part; The output of described reverser is connected with the input of described switching circuit, and the signal of described signal input part input is through the break-make of switching circuit described in described reverser control;
The output of described switching circuit is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switching circuit is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
The level signal that the present invention utilizes power supply output control circuit to receive, controls voltage and the operating state of each components and parts in described power supply output control circuit, and determines whether described power supply output control circuit carries out power supply output.Visible, can control accurately power supply output control circuit by the present invention and carry out the output of power supply.
The embodiment of the present invention also provides a kind of uplink link status control system, for improving according to the accuracy of TDD transmitting-receiving sequencing control up link operating state.
A kind of uplink link status control system, this uplink link status control system comprises: baseband processor, above-mentioned power supply output control circuit and TDD communication system up link components and parts;
Described baseband processor is connected with the input of the reverser in described power supply output control circuit; N-MOS pipe in described power supply output control circuit is connected with TDD communication system up link components and parts with the drain electrode of P-MOS pipe.
The present invention utilizes described in the TDD up-downgoing control signal control of described baseband processor output voltage and the operating state of each components and parts in power supply output control circuit, and determine that this power supply output control circuit is whether to the power supply of uplink communication link, make the in running order or halted state of uplink communication link.Visible, can improve according to the accuracy of TDD transmitting-receiving sequencing control down link operating state by the present invention.
Brief description of the drawings
Fig. 1 is the power supply output control circuit schematic diagram with switching circuit provided by the invention;
The power supply output control circuit schematic diagram with switch that Fig. 2 provides for the embodiment of the present invention;
The power supply output control circuit schematic diagram with CMOS pipe that Fig. 3 provides for the embodiment of the present invention;
The power supply output control circuit schematic diagram with triode that Fig. 4 provides for the embodiment of the present invention;
The power supply output control circuit schematic diagram with reverser and switching circuit that Fig. 5 provides for the embodiment of the present invention;
The power supply output control circuit schematic diagram with reverser and switch that Fig. 6 provides for the embodiment of the present invention;
The circuit diagram of the reverser that Fig. 7 provides for the embodiment of the present invention;
The power supply output control circuit schematic diagram with reverser and CMOS pipe that Fig. 8 provides for the embodiment of the present invention;
The power supply output control circuit schematic diagram with reverser and triode that Fig. 9 provides for the embodiment of the present invention;
The downlink communication Link State control system schematic diagram that Figure 10 provides for the embodiment of the present invention;
The uplink communication Link State control system schematic diagram that Figure 11 provides for the embodiment of the present invention;
The system schematic for the RF direct amplifying station of TDD by power supply output control circuit that Figure 12 provides for the embodiment of the present invention.
Embodiment
In order to solve the problem that cannot accurately control power supply output in mobile communication technology field, the embodiment of the present invention provides power supply output control circuit and Link State control system for addressing this problem, and below specifically introduces with embodiment.
Embodiment mono-
Referring to Fig. 1, the embodiment of the present invention provides the power supply output control circuit with switching circuit, and this circuit comprises switching circuit, voltage stabilizing didoe, N-MOS pipe and P-MOS pipe, and concrete annexation is as follows:
The input of described switching circuit is connected with signal input part, the break-make of switching circuit described in the signal controlling of signal input part input; The output of described switching circuit is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switch is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
In the time that described switching circuit receives low level signal, described switching circuit is in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and now described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and now described P-MOS pipe is in conducting state;
As can be seen here, in the time that the described power supply output control circuit with switching circuit receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the time that described switching circuit receives high level signal, described switching circuit is in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and now described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and now described P-MOS pipe is in cut-off state;
As can be seen here, in the time that the described power supply output control circuit with switching circuit receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the present embodiment, the output of switching circuit is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment bis-:
Referring to Fig. 2, the embodiment of the present invention provides the power supply output control circuit with switching circuit, and switching circuit is the switch that has on-off function in the present embodiment, specific as follows:
The input of described switch is connected with signal input part, the break-make of switch described in the signal controlling of signal input part input; The output of described switch is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switch is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
In the time that described switch receives low level signal, described switch is in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and now described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and now described P-MOS pipe is in conducting state;
As can be seen here, in the time that the described power supply output control circuit with switching circuit receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the time that described switch receives high level signal, described switch is in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and now described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and now described P-MOS pipe is in off state;
As can be seen here, in the time that the described power supply output control circuit with switching circuit receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the present embodiment, the output of switching circuit is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment tri-:
Referring to Fig. 3, the embodiment of the present invention provides the power supply output control circuit with switching circuit, and switching circuit is the CMOS pipe that has on-off function in the present embodiment, specific as follows:
The grid of described CMOS pipe is connected with signal input part, the break-make of CMOS pipe described in the signal controlling of signal input part input; The drain electrode of described CMOS pipe is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part; The source ground of described CMOS pipe;
The drain electrode of described CMOS pipe is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
In the time that described CMOS pipe receives low level signal, described CMOS pipe is in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in conducting state;
As can be seen here, in the time that the described power supply output control circuit with CMOS pipe receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the time that described CMOS pipe receives high level signal, described CMOS pipe is in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in cut-off state;
As can be seen here, in the time that the described power supply output control circuit with CMOS pipe receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the present embodiment, the grid of CMOS pipe is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment tetra-:
Referring to Fig. 4, the embodiment of the present invention provides the power supply output control circuit with switching circuit, and switching circuit is the triode that has on-off function in the present embodiment, specific as follows:
The base stage of described triode is connected with signal input part, the break-make of triode described in the signal controlling of signal input part input; The collector electrode of described triode is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part; The grounded emitter of described triode;
The collector electrode of described triode is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
In the time that described triode receives low level signal, described triode is in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in conducting state;
As can be seen here, in the time that the described power supply output control circuit with triode receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the time that described triode receives high level signal, described triode is in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in cut-off state;
As can be seen here, in the time that the described power supply output control circuit with triode receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the present embodiment, the collector electrode of triode is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment five:
Referring to Fig. 5, the embodiment of the present invention provides the power supply output control circuit with reverser and switching circuit, specific as follows:
The input of described reverser is connected with signal input part; The output of described reverser is connected with the input of described switching circuit; The signal of described signal input part input is by the break-make of switching circuit described in reverser control; The output of described switching circuit is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switching circuit is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
As shown in Figure 6, described reverser comprises the first resistance, triode and the second resistance to the circuit diagram of reverser in the present embodiment;
One end of described the first resistance is connected with signal input part, and the other end is connected with the base stage of described triode; The collector electrode of described triode is connected with one end of described the second resistance; The other end of described the second resistance is connected with the input of described switching circuit; The grounded emitter of described triode;
In the time that the input of described reverser receives low level signal, this low level signal is converted to high level signal and sends to the input of described switching circuit through the output of described reverser, make described switch in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in cut-off state;
As can be seen here, in the time that the described power supply output control circuit with reverser and switching circuit receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the time that the input of described reverser receives high level signal, this high level signal is converted to low level signal and passes to the input of described switching circuit through the output of described reverser, make described switch in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in conducting state;
As can be seen here, in the time that the described power supply output control circuit with reverser and switching circuit receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the present embodiment, the output of switching circuit is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering otiose clutter, to reduce the interference of signal.
Embodiment six:
Referring to Fig. 6, the embodiment of the present invention provides the power supply output control circuit with the switching circuit of reverser, and switching circuit is the switch that has on-off function in the present embodiment, and detailed process is as follows:
The input of described reverser is connected with signal input part; The output of described reverser is connected with the input of described switch; The signal of described signal input part input is by the break-make of switch described in reverser control; The output of described switch is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switch is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe;
As shown in Figure 7, described reverser comprises the first resistance, triode and the second resistance to the circuit diagram of reverser in the present embodiment;
One end of described the first resistance is connected with signal input part, and the other end is connected with the base stage of described triode; The collector electrode of described triode is connected with one end of described the second resistance; The other end of described the second resistance is connected with the input of described switching circuit; The grounded emitter of described triode;
In the time that the input of described reverser receives low level signal, this low level signal is converted to high level signal and passes to the input of described switch through the output of described reverser, make described switch in cut-off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in cut-off state;
As can be seen here, in the time that the power supply output control circuit with reverser and switch receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the time that the input of described reverser receives high level signal, this high level signal is converted to low level signal and passes to the input of described switch through the output of described reverser, make described switch in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in conducting state;
As can be seen here, in the time that the power supply output control circuit with reverser and switch receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the present embodiment, the output of switch is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment seven:
Referring to Fig. 8, the embodiment of the present invention provides the power supply output control circuit with reverser and switching circuit, and switching circuit is the CMOS pipe that has on-off function in the present embodiment, and detailed process is as follows:
The input of described reverser is connected with signal input part; The output of described reverser is connected with the grid of CMOS pipe, and the signal of described signal input part input is by the break-make of CMOS pipe described in described reverser control; The drain electrode of described CMOS pipe is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part; The source ground of described CMOS pipe;
The drain electrode of described CMOS pipe is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
As shown in Figure 6, described reverser comprises the first resistance, triode and the second resistance to the circuit diagram of reverser in the present embodiment;
One end of described the first resistance is connected with signal input part, and the other end is connected with the base stage of described triode; The collector electrode of described triode is connected with one end of described the second resistance; The other end of described the second resistance is connected with the input of described switching circuit; The grounded emitter of described triode.
In the time that the input of described reverser receives low level signal, this low level signal is converted to high level signal and passes to the grid of described CMOS pipe through the output of described reverser, make described CMOS pipe in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in cut-off state;
As can be seen here, in the time receiving high level signal with the power supply output control circuit of reverser and CMOS pipe, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the time that the input of described reverser receives high level signal, this high level signal is converted to low level signal and sends to the grid of described CMOS pipe through the output of described reverser, make described CMOS pipe in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in conducting state;
As can be seen here, in the time receiving low level signal with the power supply output control circuit of reverser and CMOS pipe, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the present embodiment, the drain electrode of CMOS pipe is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the voltage stabilizing value of voltage stabilizing didoe is less than the magnitude of voltage of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment eight:
Referring to Fig. 9, the embodiment of the present invention provides the power supply output control circuit with reverser and switching circuit, and switching circuit is the triode that has on-off function in the present embodiment, and detailed process is as follows:
The input of described reverser is connected with signal input part; The output of described reverser is connected with the base stage of described triode, and the signal of described signal input part input is by the break-make of triode described in described reverser control; The collector electrode of described triode is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part; The grounded emitter of described triode;
The collector electrode of described triode is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
As shown in Figure 6, described reverser comprises the first resistance, triode and the second resistance to the circuit diagram of reverser in the present embodiment;
One end of described the first resistance is connected with signal input part, and the other end is connected with the base stage of described triode; The collector electrode of described triode is connected with one end of described the second resistance; The other end of described the second resistance is connected with the input of described switching circuit; The grounded emitter of described triode.
In the time that the input of described reverser receives low level signal, this low level signal is converted to high level signal and passes to the base stage of described triode through the output of described reverser, make described triode in off state; 2.4V voltage stabilizing didoe cathode voltage is 2.6V, and cathode voltage is 5V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 2.6V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, and described N-MOS pipe is in conducting state;
The grid voltage of described P-MOS pipe is 5V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in cut-off state;
As can be seen here, in the time that the power supply output control circuit with reverser and triode receives high level signal, the voltage of output is 0V, now stops carrying power supply to downlink communication link, make downlink communication link in off state, now uplink communication link is in running order; Downlink communication link is now very important in off state, because only at downlink communication link during in off state, the work of uplink communication link could be reliable and stable.
In the time that the input of described reverser receives high level signal, this high level signal is converted to low level signal and sends to the base stage of described triode through the output of described reverser, make described triode in conducting state; 2.4V voltage stabilizing didoe cathode voltage is 0V, and cathode voltage is 2.4V; Now described N-MOS pipe is as follows with the state of described P-MOS:
The grid voltage of described N-MOS pipe is 0V, and due to the source ground of described N-MOS pipe, therefore the voltage of described source electrode is 0V, described N, and metal-oxide-semiconductor is in cut-off state;
The grid voltage of described P-MOS pipe is 2.4V, and the source electrode of described P-MOS pipe connects 5V power supply, and described P-MOS pipe is in conducting state;
As can be seen here, in the time that the power supply output control circuit with reverser and triode receives low level signal, the voltage of output is 5V, now can carry power supply to downlink communication link, makes downlink communication link in running order.
In the present embodiment, the collector electrode of triode is also connected with one end of resistance, the other end ground connection of described resistance, and this resistance can play the effect of stabilizing circuit;
In the present embodiment, can be circuit and select 2.4V voltage stabilizing didoe, also can select to have the voltage stabilizing didoe of other voltage stabilizing values, when selection, only need ensure that the magnitude of voltage of voltage stabilizing didoe is less than the voltage stabilizing value of the input power of this circuit, to reach the effect of stabilizing circuit voltage.
In the present embodiment, can be that circuit is selected the power supply of 5V, equally also can select 10V, 20V or other to be greater than arbitrarily the power supply of voltage stabilizing didoe magnitude of voltage.
In the present embodiment, in circuit, electric capacity has been added in relevant position, and the effect of described electric capacity is for filtering clutter, reduces the interference of signal.
Embodiment nine:
As shown in figure 10, the present embodiment provides a kind of downlink status control system, and detailed process is as follows: this downlink status control system comprises: power supply output control circuit and TDD communicating system descending link components and parts that in baseband processor, embodiment mono-to embodiment tetra-, arbitrary embodiment provides; Described power supply output control circuit comprises: switching circuit, voltage stabilizing didoe, P-MOS pipe and N-MOS pipe;
Described baseband processor is connected with the input of the described switching circuit in described power supply output control circuit, and described N-MOS pipe is connected with TDD communicating system descending link components and parts with the drain electrode of P-MOS pipe; The voltage of described power supply output control circuit output is for controlling the operating state of TDD communicating system descending link components and parts;
In the time that described baseband processor produces low level signal, power supply output control circuit provides power supply to each components and parts of downlink communication link, and each components and parts of downlink communication link are started working;
In the time that described baseband processor produces high level signal, power supply output control circuit stops providing power supply to each components and parts of downlink communication link, and each components and parts of downlink communication link are quit work; Now only has in the time that downlink communication link is off state the work that uplink communication link could be reliable and stable.
Embodiment ten:
As shown in figure 11, the present embodiment provides a kind of uplink link status control system, and detailed process is as follows: this downlink status control system comprises: the power supply output control circuit that in baseband processor, reverser, embodiment five to embodiment eight, arbitrary embodiment provides and TDD communication system up link components and parts; Described power supply output control circuit comprises reverser, switching circuit, voltage stabilizing didoe, P-MOS pipe and N-MOS pipe;
Described baseband processor is connected with the input of described reverser, and described N-MOS pipe is connected with TDD communication system up link components and parts with the drain electrode of P-MOS pipe; The voltage of described power supply output control circuit output is for controlling the state of TDD communication system up link components and parts;
In the time that described baseband processor produces low level signal, this low level signal is converted to high level signal by described reverser, now described power supply output control circuit stops providing power supply to each components and parts of downlink communication link, and each components and parts of downlink communication link are quit work; Now only has in the time that downlink communication link is off state the work that uplink communication link could be reliable and stable;
In the time that described baseband processor produces high level signal, this high level signal is converted to low level signal by described reverser, now described power supply output control circuit provides power supply to each components and parts of downlink communication link, and each components and parts of downlink communication link are started working.
Embodiment 11:
As shown in figure 12, the present embodiment provides corresponding power supply output control circuit that embodiment mono-to embodiment tetra-the is provided system for TDD RF direct amplifying station, this system comprises power supply output control circuit 120 for controlling downlink communication link working state and for controlling the power supply output control circuit 121 of uplink communication link working state, reverser and the each components and parts of uplink and downlink communication link; The each components and parts of described uplink and downlink communication link comprise: one or combination in any in power amplifier, filter, variable gain amplifier, low noise amplifier;
When described for control input signal that the input of power supply output control circuit 120 of downlink communication link working state receives for low level time; Describedly export 5V voltage for the power supply output control circuit 120 of controlling downlink communication link working state, make the each components and parts of downlink communication link in running order;
When described for control input signal that the input of power supply output control circuit 120 of downlink communication link working state receives for high level time; Describedly export 0V voltage for the power supply output control circuit 120 of controlling downlink communication link working state, make the each components and parts of downlink communication link in halted state; The each components and parts of this downlink communication link are very important in halted state, because only at the each components and parts of downlink communication link in halted state in the situation that, the each components and parts of guarantee uplink communication link are in stable operating state.
When the input signal receiving when the input of described reverser is high level signal, this high level signal is converted to low level signal by described reverser, and this low level signal is passed to described for controlling the power supply output control circuit 121 of uplink communication link working state; When described for control input signal that the input of power supply output control circuit 121 of uplink communication link working state receives for low level time; Describedly export 5V voltage for the power supply output control circuit 121 of controlling uplink communication link working state, make the each components and parts of uplink communication link in running order;
When the input signal receiving when the input of described reverser is low level signal, this low level signal is converted to high level signal by described reverser, and this high level signal is passed to described for controlling the power supply output control circuit 121 of uplink communication link working state; Described for controlling the output 0V voltage of power supply output control circuit 121 of uplink communication link working state, make the each components and parts of uplink communication link in halted state.
Certainly, the power supply output control circuit that the embodiment of the present invention provides also can be used in terminal or base station, with the operating state of the uplink downlink of control terminal or base station.
In sum, beneficial effect of the present invention is:
1, the present invention utilizes voltage and the operating state of each components and parts in the TDD up-downgoing control signal control power supply output control circuit of baseband processor output, and determine that this power supply output control circuit is whether to the power supply of upstream or downstream communication link, make the in running order or halted state of upstream or downstream communication link.Visible, can improve according to the accuracy of TDD transmitting-receiving sequencing control down link operating state by the present invention.
2, manage the pipe with N-MOS by P-MOS, ensure the orderly work of uplink and downlink communication link, reduced the pressure to radio frequency signal shift switch.
3, the generation of self-excitation in effectively minimizing system, due in time-sharing work state completely, there will not be crosstalking of signal between uplink and downlink communication link, namely, in receiving signal, the signal cross-talk of transmission can not entered to produce and block and self-excitation.
4, reliability is higher, simple and easy to control, reduces the pressure of baseband processor, only needs the control signal of a TDD just can complete.
5, be applicable to being used in the RF direct amplifying station of TDD, do not need baseband processor just can complete the covering of community TDD signal.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (13)
1. a power supply output control circuit, is characterized in that, this power supply output control circuit comprises: switching circuit, voltage stabilizing didoe, N-MOS pipe and P-MOS pipe;
The input of described switching circuit is connected with signal input part, the break-make of switching circuit described in the signal controlling of signal input part input;
The output of described switching circuit is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switching circuit is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
2. power supply output control circuit as claimed in claim 1, is characterized in that, described switching circuit is CMOS pipe, and the grid of described CMOS pipe is input, and the drain electrode of described CMOS pipe is output; The source ground of described CMOS pipe.
3. power supply output control circuit as claimed in claim 1, is characterized in that, described switching circuit is triode, and the base stage of described triode is input, very output of the current collection of described triode; The grounded emitter of described triode.
4. as the power supply output control circuit as described in arbitrary in claim 1-3, it is characterized in that, the output of described switching circuit is by a grounding through resistance.
5. a power supply output control circuit, is characterized in that, described power supply output control circuit comprises: reverser, switching circuit, voltage stabilizing didoe, N-MOS pipe and P-MOS pipe;
The input of described reverser is connected with signal input part; The output of described reverser is connected with the input of described switching circuit, and the signal of described signal input part input is by the break-make of switching circuit described in reverser control;
The output of described switching circuit is connected with the grid of N-MOS pipe; The drain electrode of described N-MOS pipe is connected with signal output part;
The output of described switching circuit is also connected with the positive pole of described voltage stabilizing didoe; The negative pole of described voltage stabilizing didoe is connected with the grid of P-MOS pipe; The drain electrode of described P-MOS pipe is connected with signal output part;
The negative pole of described voltage stabilizing didoe is also connected with power supply;
The source electrode of described P-MOS pipe is connected with power supply;
The source ground of described N-MOS pipe.
6. power supply output control circuit as claimed in claim 5, is characterized in that, the output of described switching circuit is by a grounding through resistance.
7. power supply output control circuit as claimed in claim 5, is characterized in that, described switching circuit is CMOS pipe, and the grid of described CMOS pipe is input, and the drain electrode of described CMOS pipe is output; The source ground of described CMOS pipe.
8. power supply output control circuit as claimed in claim 5, is characterized in that, described switching circuit is triode, and the base stage of described triode is input, very output of the current collection of described triode; The grounded emitter of described triode.
9. as the power supply output control circuit as described in arbitrary in claim 5-8, it is characterized in that, described reverser comprises the first resistance, triode and the second resistance;
One end of described the first resistance is connected with signal input part, and the other end is connected with the base stage of described triode; The collector electrode of described triode is connected with one end of described the second resistance; The other end of described the second resistance is connected with the input of described switching circuit; The grounded emitter of described triode.
10. one kind is utilized the downlink communication Link State control system of arbitrary described power supply output control circuit in claim 1-4, it is characterized in that, this downlink status control system comprises: arbitrary described power supply output control circuit and TDD communicating system descending link components and parts in baseband processor, claim 1-4;
Described baseband processor is connected with the input of the switching circuit in described power supply output control circuit, and the P-MOS pipe in described power supply output control circuit is connected with TDD communicating system descending link components and parts with the drain electrode of N-MOS pipe.
11. downlink communication Link State control system as claimed in claim 10, it is characterized in that, described TDD communicating system descending link components and parts comprise: one or combination in any in power amplifier, filter, variable gain amplifier, low noise amplifier.
12. 1 kinds are utilized the uplink communication Link State control system of arbitrary described power supply output control circuit in claim 5-9, it is characterized in that, this uplink link status control system comprises: arbitrary described power supply output control circuit and TDD communication system up link components and parts in baseband processor, claim 5-9;
Described baseband processor is connected with the input of the reverser in described power supply output control circuit; N-MOS pipe in described power supply output control circuit is connected with TDD communication system up link components and parts with the drain electrode of P-MOS pipe.
13. uplink communication Link State control system as claimed in claim 12, it is characterized in that, described TDD communication system up link components and parts comprise: one or combination in any in power amplifier, filter, variable gain amplifier, low noise amplifier.
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| CN1963707A (en) * | 2006-11-24 | 2007-05-16 | 北京中星微电子有限公司 | Apparatus for controlling power supply, method and electron system |
| CN101593016A (en) * | 2008-05-30 | 2009-12-02 | 鸿富锦精密工业（深圳）有限公司 | Power control circuit |
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| CN1963707A (en) * | 2006-11-24 | 2007-05-16 | 北京中星微电子有限公司 | Apparatus for controlling power supply, method and electron system |
| CN101593016A (en) * | 2008-05-30 | 2009-12-02 | 鸿富锦精密工业（深圳）有限公司 | Power control circuit |
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