CN101872767B - Silicon nitride trap layer olive-shaped energy band gap structure and manufacturing method thereof of SONOS (Silicon Oxide Nitride Oxide Semiconductor) component - Google Patents
Silicon nitride trap layer olive-shaped energy band gap structure and manufacturing method thereof of SONOS (Silicon Oxide Nitride Oxide Semiconductor) component Download PDFInfo
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- CN101872767B CN101872767B CN 200910057131 CN200910057131A CN101872767B CN 101872767 B CN101872767 B CN 101872767B CN 200910057131 CN200910057131 CN 200910057131 CN 200910057131 A CN200910057131 A CN 200910057131A CN 101872767 B CN101872767 B CN 101872767B
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Abstract
The invention discloses a silicon nitride trap layer olive-shaped energy band gap structure of an SONOS (Silicon Oxide Nitride Oxide Semiconductor) component. The SONOS component comprises a silicon substrate, a tunneling oxide layer, a silicon nitride trap layer, a high-temperature oxide layer and a polysilicon electrode subsequently from bottom to top; the silicon nitride trap layer energy band structure takes the shape of an olive, and the silicon nitride trap layer energy band gap which approaches to the tunneling oxide layer and the high-temperature oxide layer is narrower than the energy band gap in the middle. In addition, the invention also discloses a manufacturing method of the SONOS component structure. The invention can also improve the written/erased threshold voltage window at the same time of improving the SONOS flash memory data storage capacity.
Description
Technical field
The invention belongs to semiconductor integrated circuit and make the field, relate to a kind of SONOS flush memory device, relate in particular to a kind of silicon nitride trap layer olive-shaped band gap structure of SONOS device; In addition, the invention still further relates to the manufacture method of SONOS component structure.
Background technology
The SONOS flush memory device becomes one of at present main flash type because possess good scaled down characteristic and radiation-resisting performance.The ONO sandwich layer band structure of conventional SONOS flush memory device as shown in Figure 1, ONO sandwich layer comprises tunnel oxide 2, silicon nitride trap layer 3, thermal oxide 4.Silicon nitride, wherein is easier to reverse tunnel near the charge ratio of tunnel oxide layer segment and enters silicon substrate (back-tunneling) as charge storage media because a large amount of traps is arranged, and this can make the data hold capacity of SONOS flush memory device degenerate; And tunnelling also can occur and enter gate electrode in the electric charge that distributes near thermal oxide, thereby affects the threshold voltage window size behind the write/erase.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of silicon nitride trap layer olive-shaped band gap structure of SONOS device, when improving SONOS flash data hold capacity, also can improve the threshold voltage window behind the write/erase.For this reason, the present invention also provides a kind of manufacture method of SONOS component structure.
For solving the problems of the technologies described above, the invention provides a kind of silicon nitride trap layer olive-shaped band gap structure of SONOS device, this SONOS device comprises silicon substrate, tunnel oxide, silicon nitride trap layer, high temperature oxide layer and polysilicon electrode from bottom to up, described silicon nitride trap layer band structure is olive shape, and is narrow near the band gap width in the middle of the silicon nitride trap layer band gap Width of tunnel oxide and high temperature oxide layer.
Described silicon nitride trap layer comprises top layer silicon-rich silicon nitride trap layer, middle part silicon nitride trap layer, bottom silicon-rich silicon nitride trap layer.
The thickness of described top layer silicon-rich silicon nitride trap layer is the 10-40 dust, and the thickness of described bottom silicon-rich silicon nitride trap layer is the 10-40 dust, and the thickness of described middle part silicon nitride trap layer is the 20-120 dust.
In addition, the present invention also provides a kind of manufacture method of silicon nitride trap layer olive-shaped band gap structure of SONOS device, comprises the steps:
The first step, the preparation tunnel oxide;
Second step, the preparation silicon nitride trap layer forms silicon nitride trap layer olive-shaped band gap structure;
The 3rd step, the preparation thermal oxide;
The 4th step, the gate electrode preparation.
The first step adopts thermal oxidation technology deposit tunnel oxide on silicon substrate, and this process temperature is 700-900 ℃, and the time is 30-200 minute.
Second step is deposit silicon nitride trap layer on tunnel oxide, revise the band gap of silicon nitride by the content of adjusting silicon in the silicon nitride trap layer, form silicon nitride trap layer olive-shaped band gap structure, medium as stored charge, this process temperature is 600-800 ℃, and the time is 10-60 second.
The content of adjusting silicon in the silicon nitride trap layer described in the second step mainly is the flowrate proportioning by reacting gas source, and described reacting gas source comprises ammonia and dichloro-dihydro silicon.
The silicon nitride trap layer that second step forms comprises top layer silicon-rich silicon nitride trap layer, bottom silicon-rich silicon nitride trap layer and middle part silicon nitride trap layer; The thickness of described top layer silicon-rich silicon nitride trap layer is the 10-40 dust, and the gas flow ratio of described reacting gas source ammonia and dichloro-dihydro silicon is controlled between (1: 5) to (1: 2); The thickness of described bottom silicon-rich silicon nitride trap layer is the 10-40 dust, and the gas flow ratio of described reacting gas source ammonia and dichloro-dihydro silicon is controlled between (1: 5) to (1: 2); The thickness of described middle part silicon nitride trap layer is the 20-120 dust, and the gas flow ratio of described reacting gas source ammonia and dichloro-dihydro silicon is controlled between (3: 1) to (1: 1).
The 3rd step was adopted high temperature thermal oxidation metallization processes deposit thermal oxide on silicon nitride trap layer, and this process temperature is 600-900 ℃, and the time is 10-60 minute.
The 4th step was adopted low pressure chemical vapor deposition method deposit gate electrode on thermal oxide, and this process temperature is 600-900 ℃, and the time is 10-100 minute.
Be compared with existing technology, the present invention has following beneficial effect: the silicon nitride trap layer olive-shaped band gap structure that the present invention realizes is by improving the band gap of silicon nitride, improve electronics and hole apart from the distance of silica conduction band and valence band, thereby improve the storage capacity of electric charge and the threshold voltage window behind the write/erase.
Description of drawings
Fig. 1 is the band structure figure of conventional SONOS flush memory device;
Fig. 2 is band gap engineering SONOS device energy band diagram of the present invention;
Fig. 3 is SONOS device preparation method's of the present invention process chart, and wherein, Fig. 3 A is the sectional view of SONOS device after the first step is finished; Fig. 3 B is the sectional view of SONOS device after second step is finished among the present invention; Fig. 3 C be among the present invention the 3rd step finish after the sectional view of SONOS device; Fig. 3 D be among the present invention the 4th step finish after the sectional view of SONOS device;
Fig. 4 is the physical structure of olive shape band gap silicon nitride layer of the present invention.
In Fig. 4, Reference numeral specifically is expressed as at Fig. 1:
The 1st, silicon substrate
The 2nd, tunnel oxide
The 3rd, silicon nitride trap layer
3-T is top layer silicon-rich silicon nitride trap layer
3-M is the middle part silicon nitride trap layer
3-B is bottom silicon-rich silicon nitride trap layer
The 4th, high temperature oxide layer
The 5th, polysilicon electrode
A is the energy gap of silicon
B is that the silicon valence band is apart from the barrier height of silica valence band
C is that the silicon conduction band is apart from the barrier height of silica conduction band
D1, D2 are that the silicon nitride valence band is apart from the barrier height of silica valence band
E1, E2 are that the silicon nitride conduction band is apart from the barrier height of silica conduction band
F is the energy gap of silicon nitride
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
As shown in Figure 2, SONOS flush memory device of the present invention comprises silicon substrate 1, tunnel oxide 2, silicon nitride trap layer 3, high temperature oxide layer 4 and polysilicon electrode 5 from bottom to up, silicon nitride trap layer 3 band structures are olive shape, and are wherein narrow near the band gap width in the middle of the silicon nitride trap layer band gap Width of tunnel oxide 2 and high temperature oxide layer 4.The present invention is by adjusting silicon nitride trap layer olive-shaped band gap (band structure is referring to Fig. 2), when improving SONOS flash data hold capacity, also can improve the threshold voltage window behind the write/erase.
The main technological process of the present invention comprises the steps (as shown in Figure 3):
The first step, the tunnel oxide preparation.This step process adopts conventional thermal oxidation technology.As shown in Figure 3A, deposit tunnel oxide 2 on silicon substrate 1.This process temperature: 700-900 ℃, time 30-200Min.
Second step, silicon nitride trap layer olive-shaped band gap engineering.This step process is by adjusting the content of silicon in the silicon nitride trap layer, revises the band gap (mainly be near tunnel oxide with near thermal oxide) of silicon nitride, thereby improve the ability that electric charge is stored in medium.Reacting gas source commonly used comprises ammonia (NH
3) and dichloro-dihydro silicon (SiH
2CL
2), the adjustment of silicone content mainly is the flowrate proportioning by reacting gas source.Shown in Fig. 3 B, deposit silicon nitride trap layer 3 on tunnel oxide 2.This step process adopts the method for conventional low pressure chemical vapor deposition to prepare silicon nitride trap layer, as the medium of stored charge.This process temperature: 600-800 ℃, time 10-60Sec.As shown in Figure 4, silicon nitride trap layer 3 comprises top layer silicon-rich silicon nitride trap layer 3-T (near the silicon nitride trap layer of thermal oxide 4), bottom silicon-rich silicon nitride trap layer 3-B (near the silicon nitride trap layer of tunnel oxide 2) and middle part silicon nitride trap layer 3-M, wherein, the thickness of top layer silicon-rich silicon nitride trap layer 3-T is the 10-40 dust, ammonia (NH
3) and dichloro-dihydro silicon (SiH
2CL
2) gas flow ratio be controlled at (1: 5) between (1: 2), have higher silicone content; The thickness of bottom silicon-rich silicon nitride trap layer 3-B is the 10-40 dust, ammonia (NH
3) and dichloro-dihydro silicon (SiH
2CL
2) gas flow ratio be controlled at (1: 5) between (1: 2), have higher silicone content; The thickness of middle part silicon nitride trap layer 3-M is the 20-120 dust, ammonia (NH
3) and dichloro-dihydro silicon (SiH
2CL
2) gas flow ratio be controlled at (3: 1) between (1: 1), have lower silicone content.
The 3rd step, the preparation of thermal oxide.This step process adopts conventional high temperature thermal oxidation metallization processes.Shown in Fig. 3 C, deposit thermal oxide 4 on silicon nitride trap layer 3.This process temperature: 600-900 ℃, time 10-60Min.
The 4th step, the gate electrode preparation.Shown in Fig. 3 D, adopt conventional low pressure chemical vapor deposition method deposit gate electrode 5 on thermal oxide 4.This process temperature: 600-900 ℃, time 10-100Min.
Claims (8)
1. the silicon nitride trap layer olive-shaped band gap structure of a SONOS device, it is characterized in that, this SONOS device comprises silicon substrate, tunnel oxide, silicon nitride trap layer, high temperature oxide layer and polysilicon electrode from bottom to up, described silicon nitride trap layer band structure is olive shape, and is narrow near the band gap width in the middle of the silicon nitride trap layer band gap Width of tunnel oxide and high temperature oxide layer; Described silicon nitride trap layer comprises top layer silicon-rich silicon nitride trap layer, middle part silicon nitride trap layer, bottom silicon-rich silicon nitride trap layer.
2. the silicon nitride trap layer olive-shaped band gap structure of SONOS device as claimed in claim 1, it is characterized in that, the thickness of described top layer silicon-rich silicon nitride trap layer is the 10-40 dust, the thickness of described bottom silicon-rich silicon nitride trap layer is the 10-40 dust, and the thickness of described middle part silicon nitride trap layer is the 20-120 dust.
3. the manufacture method of the silicon nitride trap layer olive-shaped band gap structure of a SONOS device is characterized in that, comprises the steps:
The first step, the preparation tunnel oxide;
Second step, the preparation silicon nitride trap layer forms silicon nitride trap layer olive-shaped band gap structure; Second step is deposit silicon nitride trap layer on tunnel oxide, revise the band gap of silicon nitride by the content of adjusting silicon in the silicon nitride trap layer, form silicon nitride trap layer olive-shaped band gap structure, medium as stored charge, this process temperature is 600-800 ℃, and the time is 10-60 second;
The 3rd step, the preparation thermal oxide;
The 4th step, the gate electrode preparation.
4. the manufacture method of the silicon nitride trap layer olive-shaped band gap structure of SONOS device as claimed in claim 3, it is characterized in that: the first step adopts thermal oxidation technology deposit tunnel oxide on silicon substrate, this process temperature is 700-900 ℃, and the time is 30-200 minute.
5. the manufacture method of the silicon nitride trap layer olive-shaped band gap structure of SONOS device as claimed in claim 3, it is characterized in that: the content of adjusting silicon in the silicon nitride trap layer described in the second step mainly is the flowrate proportioning by reacting gas source, and described reacting gas source comprises ammonia and dichloro-dihydro silicon.
6. the manufacture method of the silicon nitride trap layer olive-shaped band gap structure of SONOS device as claimed in claim 5 is characterized in that: the silicon nitride trap layer that second step forms comprises top layer silicon-rich silicon nitride trap layer, bottom silicon-rich silicon nitride trap layer and middle part silicon nitride trap layer; The thickness of described top layer silicon-rich silicon nitride trap layer is the 10-40 dust, and the gas flow ratio of described reacting gas source ammonia and dichloro-dihydro silicon is controlled between (1: 5) to (1: 2); The thickness of described bottom silicon-rich silicon nitride trap layer is the 10-40 dust, and the gas flow ratio of described reacting gas source ammonia and dichloro-dihydro silicon is controlled between (1: 5) to (1: 2); The thickness of described middle part silicon nitride trap layer is the 20-120 dust, and the gas flow ratio of described reacting gas source ammonia and dichloro-dihydro silicon is controlled between (3: 1) to (1: 1).
7. the manufacture method of the silicon nitride trap layer olive-shaped band gap structure of SONOS device as claimed in claim 3, it is characterized in that: the 3rd step was adopted high temperature thermal oxidation metallization processes deposit thermal oxide on silicon nitride trap layer, this process temperature is 600-900 ℃, and the time is 10-60 minute.
8. the manufacture method of the silicon nitride trap layer olive-shaped band gap structure of SONOS device as claimed in claim 3, it is characterized in that: the 4th step was adopted low pressure chemical vapor deposition method deposit gate electrode on thermal oxide, this process temperature is 600-900 ℃, and the time is 10-100 minute.
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| CN102446862B (en) * | 2011-08-29 | 2014-04-02 | 上海华力微电子有限公司 | Novel double-bit line SONOS (silicon oxide nitride oxide silicon) unit structure and manufacturing method thereof |
| CN102420233A (en) * | 2011-11-02 | 2012-04-18 | 上海宏力半导体制造有限公司 | Method for improving data retention of SONOS (Silicon Oxide Nitride Oxide Semiconductor) and structure of SONOS |
| CN102610654A (en) * | 2012-03-14 | 2012-07-25 | 上海华力微电子有限公司 | Device with conical energy band silicon nitride layer SONOS (silicon oxide nitride oxide semiconductor) structure and high erasing speed |
| CN106449766A (en) * | 2016-11-09 | 2017-02-22 | 上海华力微电子有限公司 | SONOS (silicon-oxide-nitride-oxide-silicon) device and method for manufacturing same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518617B1 (en) * | 1996-12-31 | 2003-02-11 | Sony Corporation | Nonvolatile semiconductor memory device |
| CN101170135A (en) * | 2006-10-23 | 2008-04-30 | 海力士半导体有限公司 | Non volatile memory device possessing charge trapping layer and its manufacture method |
| CN101364615A (en) * | 2007-08-08 | 2009-02-11 | 旺宏电子股份有限公司 | Nonvolatile memory and forming method for the same |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6518617B1 (en) * | 1996-12-31 | 2003-02-11 | Sony Corporation | Nonvolatile semiconductor memory device |
| CN101170135A (en) * | 2006-10-23 | 2008-04-30 | 海力士半导体有限公司 | Non volatile memory device possessing charge trapping layer and its manufacture method |
| CN101364615A (en) * | 2007-08-08 | 2009-02-11 | 旺宏电子股份有限公司 | Nonvolatile memory and forming method for the same |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140115 |
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Effective date of registration: 20140115 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |