CN101872746A - Method for enhancing reliability of SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory by adopting ND3 annealing - Google Patents
Method for enhancing reliability of SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory by adopting ND3 annealing Download PDFInfo
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- CN101872746A CN101872746A CN200910057130A CN200910057130A CN101872746A CN 101872746 A CN101872746 A CN 101872746A CN 200910057130 A CN200910057130 A CN 200910057130A CN 200910057130 A CN200910057130 A CN 200910057130A CN 101872746 A CN101872746 A CN 101872746A
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Abstract
The invention discloses a method for enhancing the reliability of an SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory by adopting ND3 annealing. The method comprises the following steps of: firstly, preparing a tunneling oxidation layer; secondly, carrying out the ND3 annealing; thirdly, preparing a silicon nitride trap layer; fourthly, preparing a high-temperature heat oxidation layer; and fifthly, preparing a gate electrode. In the ND3 annealing process, a dangling bond positioned on an interface of the tunneling oxidation layer and a silicon substrate can be saturated by a silicon-deuterium bond, and the unstable silicon-hydrogen bond can be substituted by the silicon-deuterium bond, therefore, the electrology characteristics of the interface can be greatly enhanced, and further, the reliability of the SONOS flash memory can be enhanced.
Description
Technical field
The invention belongs to semiconductor integrated circuit and make the field, relate to a kind of method of manufacturing technology of SONOS flush memory device, relate in particular to the method that a kind of employing ND3 (ammonia, deuterated) annealing improves SONOS flush memory device reliability.
Background technology
SONOS flush memory device (with the flush memory device of silicon nitride as charge storage media) becomes one of at present main flash type because possess good scaled down characteristic and radiation-resisting performance.The integrity problem that the SONOS flush memory device faces mainly contains two: the one, and Endurance (durable) characteristic is weighed the SONOS device after program/erase repeatedly, the degeneration that the device property aspect is possible exactly.The 2nd, Data Retention (data maintenance) characteristic is exactly the data hold capacity of SONOS device.Existing SONOS flash technology normally prepares on silicon substrate after the tunnel oxide, just directly makes silicon nitride trap layer, and then makes thermal oxide.May there be the labile state of some dangling bonds and so in interface between tunnel oxide and the silicon substrate, and this can influence the reliability of SONOS device greatly.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of ND3 of employing and anneals and improve the method for SONOS flush memory device reliability, this method can improve tunnel oxide and silicon substrate electrology characteristic at the interface greatly, and then can improve the reliability of SONOS flush memory device.
For solving the problems of the technologies described above, the invention provides a kind of ND3 of employing and anneal and improve the method for SONOS flush memory device reliability, comprise the steps:
The first step, the preparation tunnel oxide;
Second step, ND3 annealing;
The 3rd step, the preparation silicon nitride trap layer;
The 4th step, the preparation thermal oxide;
The 5th step, the preparation gate electrode.
The first step adopts thermal oxidation technology deposit tunnel oxide on silicon substrate, and the technological temperature of this step is 700-900 ℃, and the time is 30-200 minute.
In second step, the temperature of ND3 annealing is 900-1100 ℃, and the time of ND3 annealing is 30-60 minute.
In second step, tunnel oxide and silicon substrate dangling bonds at the interface are saturated by silicon-deuterium key, and unsettled silicon-hydrogen bond is replaced by silicon-deuterium key simultaneously.
The 3rd step was adopted method deposit silicon nitride trap layer on tunnel oxide of low pressure chemical vapor deposition, and as the medium of stored charge, the technological temperature of this step is 600-800 ℃, and the time is 10-60 second.
The 4th step was adopted high temperature thermal oxidation metallization processes deposit thermal oxide on silicon nitride trap layer.
The 5th step was adopted conventional low pressure chemical vapor deposition method deposit gate electrode on thermal oxide.
Compare with prior art, the present invention has following beneficial effect: in the process of ND3 annealing, tunnel oxide and silicon substrate dangling bonds at the interface can be saturated by silicon-deuterium key, unsettled silicon-hydrogen bond can be replaced by silicon-deuterium key simultaneously, so just improve electrology characteristic at the interface greatly, and then can improve SONOS flush memory device reliability.
Description of drawings
Fig. 1 is the sectional view of SONOS flush memory device after the first step is finished among the present invention;
Fig. 2 be among the present invention second step finish after the sectional view of SONOS flush memory device;
Fig. 3 be among the present invention the 3rd step finish after the sectional view of SONOS flush memory device;
Fig. 4 be among the present invention the 4th step finish after the sectional view of SONOS flush memory device;
Fig. 5 be among the present invention the 5th step finish after the sectional view of SONOS flush memory device.
Embodiment
The present invention is further detailed explanation below in conjunction with drawings and Examples.
The main technological process of the present invention comprises the steps:
The first step, the tunnel oxide preparation.This step process adopts conventional thermal oxidation technology.As shown in Figure 1, deposit tunnel oxide 2 on silicon substrate 1.The technological temperature of this step: 700-900 ℃, the time is 30-200Min.
Second step, ND3 (ammonia, deuterated) annealing.The temperature range of ND3 annealing: 900-1100 ℃, the time of ND3 annealing: 30-60Min.As shown in Figure 2, in the process of ND3 annealing, tunnel oxide 2 and silicon substrate 1 dangling bonds at the interface can be saturated by silicon-deuterium key, unsettled silicon-hydrogen bond can be replaced by silicon-deuterium key simultaneously, so just improve electrology characteristic at the interface greatly, and then can improve SONOS flush memory device reliability.
The 3rd step, the silicon nitride trap layer preparation.This step process adopts the method for conventional low pressure chemical vapor deposition to prepare silicon nitride trap layer, as the medium of stored charge.As shown in Figure 3, deposit silicon nitride trap layer 3 on tunnel oxide 2.The technological temperature of this step: 600-800 ℃, the time is 10-60Sec.
The 4th step, the preparation of thermal oxide.This step process adopts conventional high temperature thermal oxidation metallization processes.
As shown in Figure 4, deposit thermal oxide 4 on silicon nitride trap layer 3.
The 5th step, the gate electrode preparation.As shown in Figure 5, this step process adopts conventional low pressure chemical vapor deposition method deposit gate electrode 5 on thermal oxide 4.
Claims (7)
1. a method that adopts ND3 to anneal to improve SONOS flush memory device reliability is characterized in that, comprises the steps:
The first step, the preparation tunnel oxide;
Second step, ND3 annealing;
The 3rd step, the preparation silicon nitride trap layer;
The 4th step, the preparation thermal oxide;
The 5th step, the preparation gate electrode.
2. employing ND3 according to claim 1 anneals and improves the method for SONOS flush memory device reliability, it is characterized in that: the first step adopts thermal oxidation technology deposit tunnel oxide on silicon substrate, the technological temperature of this step is 700-900 ℃, and the time is 30-200 minute.
3. employing ND3 according to claim 1 anneals and improves the method for SONOS flush memory device reliability, it is characterized in that: in second step, the temperature of ND3 annealing is 900-1100 ℃, and the time of ND3 annealing is 30-60 minute.
4. anneal according to claim 1 or 3 described employing ND3 and improve the method for SONOS flush memory device reliability, it is characterized in that: in second step, tunnel oxide and silicon substrate dangling bonds at the interface are saturated by silicon-deuterium key, and unsettled silicon-hydrogen bond is replaced by silicon-deuterium key simultaneously.
5. employing ND3 according to claim 1 anneals and improves the method for SONOS flush memory device reliability, it is characterized in that: the 3rd step was adopted method deposit silicon nitride trap layer on tunnel oxide of low pressure chemical vapor deposition, medium as stored charge, the technological temperature of this step is 600-800 ℃, and the time is 10-60 second.
6. employing ND3 according to claim 1 anneals and improves the method for SONOS flush memory device reliability, it is characterized in that: the 4th step was adopted high temperature thermal oxidation metallization processes deposit thermal oxide on silicon nitride trap layer.
7. employing ND3 according to claim 1 anneals and improves the method for SONOS flush memory device reliability, it is characterized in that: the 5th step was adopted low pressure chemical vapor deposition method deposit gate electrode on thermal oxide.
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| CN200910057130A CN101872746A (en) | 2009-04-24 | 2009-04-24 | Method for enhancing reliability of SONOS (Silicon Oxide Nitride Oxide Semiconductor) flash memory by adopting ND3 annealing |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486999A (en) * | 2010-12-01 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Forming method of grid oxidation layer |
| CN103718276A (en) * | 2011-07-21 | 2014-04-09 | 国际商业机器公司 | Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys |
| CN104347515A (en) * | 2013-08-01 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for flash memory |
| CN105552034A (en) * | 2016-03-01 | 2016-05-04 | 上海华力微电子有限公司 | Method for improving reliability of SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) flash memory instrument |
| CN106571296A (en) * | 2015-10-13 | 2017-04-19 | 上海新昇半导体科技有限公司 | Wafer forming method |
| CN109473439A (en) * | 2018-11-16 | 2019-03-15 | 上海华力微电子有限公司 | A kind of integrated technique of SONOS memory device preparation |
| WO2019241887A1 (en) * | 2018-06-19 | 2019-12-26 | National Research Council Of Canada | Lithography for editable atomic-scale devices and memories |
-
2009
- 2009-04-24 CN CN200910057130A patent/CN101872746A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486999A (en) * | 2010-12-01 | 2012-06-06 | 中芯国际集成电路制造(北京)有限公司 | Forming method of grid oxidation layer |
| CN103718276A (en) * | 2011-07-21 | 2014-04-09 | 国际商业机器公司 | Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys |
| CN103718276B (en) * | 2011-07-21 | 2016-05-18 | 国际商业机器公司 | Make the method for amorphous silicon hydride and amorphous silane alloy stabilisation |
| CN104347515A (en) * | 2013-08-01 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for flash memory |
| CN106571296A (en) * | 2015-10-13 | 2017-04-19 | 上海新昇半导体科技有限公司 | Wafer forming method |
| CN105552034A (en) * | 2016-03-01 | 2016-05-04 | 上海华力微电子有限公司 | Method for improving reliability of SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) flash memory instrument |
| WO2019241887A1 (en) * | 2018-06-19 | 2019-12-26 | National Research Council Of Canada | Lithography for editable atomic-scale devices and memories |
| US11557337B2 (en) | 2018-06-19 | 2023-01-17 | National Research Council Of Canada | Lithography for editable atomic-scale devices and memories |
| US11955172B2 (en) | 2018-06-19 | 2024-04-09 | National Research Council Of Canada | Lithography for editable atomic-scale devices and memories |
| CN109473439A (en) * | 2018-11-16 | 2019-03-15 | 上海华力微电子有限公司 | A kind of integrated technique of SONOS memory device preparation |
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