CN101872114A - Mask plate layout for manufacturing metal interconnecting wires - Google Patents
Mask plate layout for manufacturing metal interconnecting wires Download PDFInfo
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- CN101872114A CN101872114A CN200910049996A CN200910049996A CN101872114A CN 101872114 A CN101872114 A CN 101872114A CN 200910049996 A CN200910049996 A CN 200910049996A CN 200910049996 A CN200910049996 A CN 200910049996A CN 101872114 A CN101872114 A CN 101872114A
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- interconnecting wires
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Abstract
The invention provides a mask plate layout for manufacturing metal interconnecting wires. The mask plate layout comprises a plurality of line patterns and an open pattern, wherein the plurality of line patterns are used for forming the metal interconnecting wires; and the open pattern is arranged in the line patterns and is used for forming insulated isolation areas. The mask plate layout for manufacturing the metal interconnecting wires has the advantages of solving the problems of copper residues in the process of manufacturing the metal interconnecting wires, increasing the stability of the process, and improving the yield of products.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of mask plate layout that is used to make metal interconnecting wires.
Background technology
At present, make the field at integrated circuit, copper has replaced aluminium becomes the main flow interconnection technique of VLSI (very large scale integrated circuit) in making.As the substitute of aluminium, copper conductor can reduce interconnected impedance, reduces power consumption and cost, improves integrated level, device density and the clock frequency of chip.Therefore, generally adopt copper interconnecting line as metal interconnecting wires at present.In VLSI (very large scale integrated circuit), packaging density improves constantly and makes circuit component more and more closeer, therefore generally adopts the multiple layer metal interconnection line.
Because the etching to copper is very difficult, industry generally adopts Damascus technics (Damascene) at present, makes the multiple layer metal interconnection line.Specifically please refer to Figure 1A to Fig. 1 C, generally include following steps: at first deposit the certain thickness silicon dioxide that is mixed with impurity, then by exposing with needed interconnection line figure, be transferred on the wafer that deposits silicon dioxide from mask plate, and utilize etch step to form the metal interconnected line graph of ground floor, promptly form through hole and groove, carry out the electroplating technology of copper interconnecting line again, be cmp (CMP) at last, the copper electrodeposited coating is carried out planarization and cleaning, just formed ground floor metal interconnecting wires and insulation isolated area 10 shown in Figure 1A.
The ground floor metal interconnecting wires comprises metal interconnecting wires 21 and metal interconnecting wires 22, and wherein, the live width of metal interconnecting wires 21 is greater than 4um, and the live width of metal interconnecting wires 22 is between 0.5um to 3um.Yet, because employed lapping liquid has the ratio of selection in the process of lapping, it is for the grinding rate of the copper grinding rate much larger than silicon dioxide, therefore, some depressions have been formed in the middle of the metal interconnecting wires, and the grinding rate of the copper cash of different live widths is also inequality, so cause the sinking degree of metal interconnecting wires also inequality.Wherein, the depression that live width is caused greater than the metal interconnecting wires 21 of 4um, even more serious than live width less than the depression that the metal interconnecting wires 22 of 4um is caused.
Then, deposition is mixed with the silicon dioxide of impurity once more, forms insulation isolated area 30, and forms the second metal interconnected line structure, carries out the copper electroplating technology afterwards once more, forms the copper electrodeposited coating 40 shown in Figure 1B.
Next carry out chemical mechanical milling tech once more, copper electrodeposited coating 40 is carried out planarization and cleaning.But, shown in Fig. 1 C, having formed copper residual defects 41, the performance that this will have a strong impact on device causes device to be scrapped.
Cmp is an important process of finishing metal interconnecting wires, but in the chemical mechanical planarization process of copper interconnecting line, because employed lapping liquid has the selection ratio, it is to the etch rate of different materials difference to some extent, and the etch rate of metal interconnecting wires is greater than the etch rate of silicon dioxide.Therefore if be used for making the metal interconnecting wires domain, include the bargraphs of live width greater than 4um, then in the metal interconnecting wires manufacture process, its formed metal interconnecting wires is behind chemical mechanical milling tech, the copper residual defects that is produced is comparatively serious, cause the technology instability, the yield of product descends.By contrast, the metal interconnecting wires of live width between 0.5um to 3um then this kind defective can not occur.
Therefore, revising the mask plate layout be used to make metal interconnecting wires, avoid occurring the copper residual defects behind the chemical mechanical milling tech, is very necessary.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of mask plate layout that is used to make metal interconnecting wires, to solve in existing metal interconnecting wires manufacture process, the problem of copper residual defects occurs, improves the product yield.
For solving the problems of the technologies described above, the invention provides a kind of mask plate layout that is used to make metal interconnecting wires, comprising: bargraphs is used to form metal interconnecting wires; And opening figure, be arranged in the described bargraphs, be used to form the insulation isolated area.
Optionally, described bargraphs is a linear, and its live width is greater than 4um.
Optionally, described opening figure comprises a plurality of equally distributed strip gabs, and the live width of described strip gab is between 0.5um to 3um.
Optionally, the spacing between described a plurality of strip gab is between 0.5um to 3um.
Optionally, the distance at the described bargraphs of described opening figure distance edge is between 0.5um to 3um.
Optionally, described bargraphs is " L " shape, and it has a bending zone.
Optionally, described bending zone is square, and described square diagonal line is greater than 4um, and described opening figure is arranged in the described bending zone.
Optionally, described opening figure comprises a plurality of equally distributed square aperture, and the live width of described square aperture is between 0.5um to 3um.
Optionally, the spacing between described a plurality of square aperture is between 0.5um to 3um.
Optionally, the distance of the described bending edges of regions of described opening figure distance is between 0.5um to 3um.
Optionally, described bargraphs comprises: first bargraphs, and its live width is less than 4um; And second bargraphs, to intersect with described first bar pattern, its live width is greater than 4um.
Optionally, described opening figure is arranged in described second bargraphs, and it comprises a plurality of equally distributed strip openings, and the live width of described strip opening is between 0.5um to 3um.
Optionally, the spacing between described a plurality of strip opening is between 0.5um to 3um.
Optionally, the distance at the described second bargraphs edge of described opening figure distance is between 0.5um to 3um.
In sum, the invention provides a kind of mask plate layout that is used to make metal interconnecting wires, it comprises: a plurality of bargraphss are used to form metal interconnecting wires; Opening figure is arranged in the described bargraphs, is used to form the insulation isolated area.Solved in the metal interconnecting wires manufacture process, the problem of copper residual defects occurred, increased the stability of technology, improved the product yield.
Description of drawings
Figure 1A to Fig. 1 C is the structural representation in the metal interconnecting wires manufacturing process of prior art;
Fig. 2 is the synoptic diagram of mask plate layout that is used to make metal interconnecting wires of first embodiment of the invention;
Fig. 3 is the synoptic diagram of mask plate layout that is used to make metal interconnecting wires of second embodiment of the invention;
Fig. 4 is the synoptic diagram of mask plate layout that is used to make metal interconnecting wires of third embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Disposal route of the present invention can be widely applied in many application; and utilize many suitable material; be to be illustrated below by preferred embodiment; certainly the present invention is not limited to this specific embodiment, and the known general replacement of one of ordinary skilled in the art is encompassed in protection scope of the present invention far and away.
Secondly, the present invention utilizes synoptic diagram to describe in detail, and when the embodiment of the invention was described in detail in detail, for convenience of explanation, synoptic diagram was disobeyed the local amplification of general ratio, should be with this as limitation of the invention.
Along with device feature size is more and more littler, the improving constantly of chip integration, copper has replaced aluminium becomes the main flow interconnection technique of VLSI (very large scale integrated circuit) in making.As the substitute of aluminium, copper conductor can reduce interconnected impedance, reduces power consumption and cost, improves the integrated level, device density of chip and frequency all the time, therefore, generally adopts copper interconnecting line as metal interconnecting wires at present.
Usually the manufacturing process at metal interconnecting wires comprises the steps: at first to deposit certain thickness silicon dioxide, then by exposing with needed interconnection line figure, be transferred on the wafer that deposits silicon dioxide from mask plate, and utilize etch step to form the metal interconnected line graph of ground floor, carry out the electroplating technology of copper interconnecting line again, be cmp at last, to form ground floor metal interconnecting wires and ground floor insulation isolated area.Yet, because employed lapping liquid has the ratio of selection in the process of lapping, it is for the grinding rate of the copper grinding rate much larger than silicon dioxide, therefore, some depressions will have been formed in the middle of the metal interconnecting wires, because the grinding rate difference of the metal interconnecting wires of different live widths is so cause the sinking degree of metal interconnecting wires also inequality.Wherein, if metal interconnecting wires comprises the metal interconnecting wires of live width greater than 4um, its formed depression is especially serious.
Next deposition of silica once more, and after forming second layer metal interconnection line figure, carry out copper electroplating technology and chemical mechanical milling tech once more.But after chemical mechanical milling tech was finished, live width then caused having occurred the copper residual defects greater than the metal interconnecting wires of 4um, and this will have a strong impact on the performance of device, even cause device to be scrapped.Therefore, the invention provides a kind of mask plate layout that is used to make metal interconnecting wires, comprising: a plurality of bargraphss are used to form metal interconnecting wires; Opening figure is arranged in the described bargraphs, is used to form the insulation isolated area.
At the mask plate layout that is used for making metal interconnecting wires provided by the present invention, comprise opening figure, be arranged at and be used to make in the bargraphs of metal interconnecting wires,, make metal interconnecting wires be divided to form the insulation isolated area, the live width of the lines after it is divided is all in the scope of 0.5um to 3um, solved in the metal interconnecting wires manufacturing process, the problem of copper residual phenomena occurred, increased the stability of technology, improved the product yield, and manufacture craft is simple.
Specifically please refer to Fig. 2, it describes the first embodiment of the present invention for the synoptic diagram of mask plate layout that is used to make metal interconnecting wires of first embodiment of the invention in detail below in conjunction with Fig. 2.
As shown in Figure 2, mask plate layout 100 comprises bargraphs 110, be used to form metal interconnecting wires, detailed, bargraphs 110 is a rectilinear form, its live width is greater than 4um, if its inside is not provided with opening figure, then in metal interconnecting wires manufacturing process, the copper residual defects will occur, and influence properties of product.Therefore, mask plate layout 100 also comprises opening figure, is arranged in the bargraphs 110, is used to form the insulation isolated area, to guarantee the copper residual defects can not occur behind cmp.
Wherein, opening figure comprises a plurality of equally distributed strip gabs 120, and the live width 121 of described a plurality of strip gabs, spacing 122 and shape are all identical, are convenient to the processing and fabricating mask plate layout.Specifically, the live width 121 of strip gab 120 is arranged between the 0.5um to 3um, spacing 122 between described a plurality of strip gab is arranged between the 0.5um to 3um, and opening figure also is arranged between the 0.5um to 3um apart from the distance 123 at bargraphs 110 edges.
In the present embodiment, bargraphs 110 is divided, the live width of the lines after it is divided is all in the scope of 0.5um to 3um, then the live width of the metal interconnecting wires of its formation is also corresponding reduces, in the scope of 0.5um to 3um, avoid in metal interconnecting wires manufacturing process, the copper residual defects occurring, increase the stability of technology, improved the product yield.
Specifically please refer to Fig. 3, in second embodiment of the invention, mask plate layout 200 comprises bargraphs 210, be used to form metal interconnecting wires, it is " L " shape, has a bending zone 211 (shown in frame of broken lines among the figure), and described bending zone 211 is square, its diagonal line is greater than 4um, the live width of bargraphs 210 except that bending zone 211 is all less than 4um, and therefore, opening figure is arranged in the bending zone 211, to avoid in chemical mechanical milling tech, the copper residual defects appears.
Further, opening figure comprises a plurality of equally distributed square aperture 220, and the live width 221 of described a plurality of square aperture 220, spacing 222 and shape are all identical, are convenient to the processing and fabricating mask plate layout.Specifically, the live width 221 of square aperture 220 is arranged between the 0.5um to 3um, and the spacing 222 between a plurality of square aperture is arranged between the 0.5um to 3um, and opening figure also is arranged between the 0.5um to 3um apart from the distance 223 that bends regional 211 edges.Promptly make the bending zone of bargraphs 310 be divided, the live width of the lines after it is divided all is arranged in the scope of 0.5um to 3um, then the live width of the metal interconnecting wires of its formation is also corresponding reduces, promptly in the scope of 0.5um to 3um, avoid in metal interconnecting wires manufacturing process, occurring the copper residual defects, increase the stability of technology, improved the product yield.
Specifically please refer to Fig. 4, in third embodiment of the invention, mask plate layout 300 comprises bargraphs, is used to form metal interconnecting wires, and wherein bargraphs comprises: a plurality of first bargraphss 311 that are arranged in parallel, be rectilinear form, and its live width is less than 4um; And second bargraphs 312, be rectilinear form, intersect with first bar pattern 311, therefore its live width is greater than 4um,, then need add opening figure in second bargraphs 312, so that the live width of its formed metal interconnecting wires reduces, promptly in the scope of 0.5um to 3um, avoid in metal interconnecting wires manufacturing process, occurring the copper residual defects, increase the stability of technology, improved the product yield.
Further, opening figure comprises a plurality of equally distributed strip openings 320, and the live width 321 of described a plurality of strip openings 320 and spacing 322 are all identical, so that the processing and fabricating mask plate layout.Specifically, the live width 321 of strip opening 320 is arranged between the 0.5um to 3um, it is arranged in described second bargraphs 312, spacing 322 between a plurality of strip openings 320 is arranged between the 0.5um to 3um, and the distance 323 at opening figure distance second bargraphs 312 edges also is arranged between the 0.5um to 3um.Promptly make second bargraphs 312 be divided, the live width of the lines after it is divided is all in the scope of 0.5um to 3um, then the live width of the metal interconnecting wires of its formation is also corresponding reduces, and promptly in the scope of 0.5um to 3um, avoids occurring the copper residual defects in metal interconnecting wires manufacturing process.
In sum, the invention provides a kind of mask plate layout that is used to make metal interconnecting wires, it comprises: one or more bargraphss are used to form metal interconnecting wires; Opening figure is arranged in the corresponding bargraphs, is used to form the insulation isolated area.Solved in the metal interconnecting wires manufacture process, the problem of copper residual defects occurred, increased the stability of technology, improved the product yield.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (14)
1. a mask plate layout that is used to make metal interconnecting wires is characterized in that, comprising:
Bargraphs is used to form metal interconnecting wires; And
Opening figure is arranged in the described bargraphs, is used to form the insulation isolated area.
2. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 1 is characterized in that, described bargraphs is a linear, and its live width is greater than 4um.
3. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 2 is characterized in that, described opening figure comprises a plurality of equally distributed strip gabs, and the live width of described strip gab is between 0.5um to 3um.
4. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 3 is characterized in that, the spacing between described a plurality of strip gabs is between 0.5um to 3um.
5. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 4 is characterized in that, the distance at the described bargraphs of described opening figure distance edge is between 0.5um to 3um.
6. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 1 is characterized in that, described bargraphs is " L " shape, and it has a bending zone.
7. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 6 is characterized in that, described bending zone is square, and described square diagonal line is greater than 4um, and described opening figure is arranged in the described bending zone.
8. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 7 is characterized in that, described opening figure comprises a plurality of equally distributed square aperture, and the live width of described square aperture is between 0.5um to 3um.
9. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 8 is characterized in that, the spacing between described a plurality of square aperture is between 0.5um to 3um.
10. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 9 is characterized in that, the distance of the described bending edges of regions of described opening figure distance is between 0.5um to 3um.
11. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 1 is characterized in that, described bargraphs comprises: first bargraphs, and its live width is less than 4um; And second bargraphs, to intersect with described first bar pattern, its live width is greater than 4um.
12. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 11, it is characterized in that, described opening figure is arranged in described second bargraphs, and it comprises a plurality of equally distributed strip openings, and the live width of described strip opening is between 0.5um to 3um.
13. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 12 is characterized in that, the spacing between described a plurality of strip openings is between 0.5um to 3um.
14. the mask plate layout that is used to make metal interconnecting wires as claimed in claim 13 is characterized in that, the distance at the described second bargraphs edge of described opening figure distance is between 0.5um to 3um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100499964A CN101872114B (en) | 2009-04-24 | 2009-04-24 | Mask plate layout for manufacturing metal interconnecting wires |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100499964A CN101872114B (en) | 2009-04-24 | 2009-04-24 | Mask plate layout for manufacturing metal interconnecting wires |
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| Publication Number | Publication Date |
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| CN101872114A true CN101872114A (en) | 2010-10-27 |
| CN101872114B CN101872114B (en) | 2012-03-28 |
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| CN2009100499964A Active CN101872114B (en) | 2009-04-24 | 2009-04-24 | Mask plate layout for manufacturing metal interconnecting wires |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102749807A (en) * | 2011-04-19 | 2012-10-24 | 住友化学株式会社 | Photosensitive resin composition |
| CN103728827A (en) * | 2013-12-26 | 2014-04-16 | 深圳市华星光电技术有限公司 | Photomask, thin film transistor element and method of preparing thin film transistor element |
| CN112768457A (en) * | 2020-12-23 | 2021-05-07 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory structure and mask plate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100280035B1 (en) * | 1992-11-27 | 2001-03-02 | 기타지마 요시토시 | Phase Shift Photomask |
| KR970007174B1 (en) * | 1994-07-07 | 1997-05-03 | 현대전자산업 주식회사 | Method wiring method for semiconductor device |
| US5989754A (en) * | 1997-09-05 | 1999-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photomask arrangement protecting reticle patterns from electrostatic discharge damage (ESD) |
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2009
- 2009-04-24 CN CN2009100499964A patent/CN101872114B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102749807A (en) * | 2011-04-19 | 2012-10-24 | 住友化学株式会社 | Photosensitive resin composition |
| CN103728827A (en) * | 2013-12-26 | 2014-04-16 | 深圳市华星光电技术有限公司 | Photomask, thin film transistor element and method of preparing thin film transistor element |
| CN112768457A (en) * | 2020-12-23 | 2021-05-07 | 长江存储科技有限责任公司 | Method for forming three-dimensional memory structure and mask plate |
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| CN101872114B (en) | 2012-03-28 |
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