CN101866892B - Chip layout structure and method - Google Patents
Chip layout structure and method Download PDFInfo
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- CN101866892B CN101866892B CN2009101353300A CN200910135330A CN101866892B CN 101866892 B CN101866892 B CN 101866892B CN 2009101353300 A CN2009101353300 A CN 2009101353300A CN 200910135330 A CN200910135330 A CN 200910135330A CN 101866892 B CN101866892 B CN 101866892B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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Abstract
The invention relates to a chip layout structure and a method. The chip layout structure comprises a first conductive through hole, a second conductive through hole, a chip and eight joints. The first conductive through hole and the second conductive through hole pass through the chip, wherein the first conductive through hole comprises a first joint and a second joint; the second conductive through hole comprises a third joint and a fourth joint; a fifth joint is communicated with the third joint; a sixth joint is communicated with the second joint; a seventh joint is communicated with the first joint; the eighth joint is communicated with the fourth joint; and on the vertical direction of the chip, the first joint is partially or completely superposed with the second joint, the third joint is partially or completely superposed with the fourth joint, the sixth joint is partially or completely superposed with the fifth joint, and the eighth joint is partially or completely superposed with the seventh joint.
Description
Technical field
The present invention relates to a kind of layout structure and method of chip, particularly relate to the layout structure and the method for stacked chips.
Background technology
The technology that is manufactured in one chip at present transistor is in the development, by vertical direction layout stacked chips, can allow the chip of difference in functionality or different process technology reach the purpose of integration, solve the difficulty that difference in functionality or the manufacturing of variety classes transistor are integrated in one chip.Yet the layout type of signal link is in the stacked chips now, utilize circuit rerouting technology (Redistribution Layer in the chip front side or the back side, RDL) coiling is used and is changed the signal contact position, utilizes dimpling piece (Micro Bump) to use afterwards again to make to engage between the stacked chips.In view of the above, the signal between a plurality of chips just can pass through these coilings, contact, dimpling piece in proper order, and through-silicon-via (Through Silicon Via TSV) transmits up and down.
Generally speaking, like this technology at the transfer mode that may fix signal between the stacked chips on the connected mode.That is to say that if designing requirement changes the signal transfer mode of stacked chips, except needs changed the layout of dimpling piece, the RDL that then must all change chip front side and the back side on the other hand again wound the line, use and meet another designing requirement.Further, the redesign of RDL representative increases manufacturing cost.
Summary of the invention
The purpose of this invention is to provide a kind of chip layout structure, two conductive through hole is through chip, the chip both sides have four contacts and four leads, and at least one conductive projection is coupled to above-mentioned at least one contact, use to make four contacts have various interconnecting.
The purpose of this invention is to provide a kind of chip layout method, two conductive through hole runs through and is formed in the chip, the chip both sides form four contacts and four leads, and at least one conductive projection is formed at above-mentioned at least one contact, uses to make four contacts have various interconnecting.
For achieving the above object, the invention provides the layout structure of a chip, comprise the 1st conductive through hole, the 2nd conductive through hole, the 1st chip, and the 1st contact to the 8 contacts.The 1st conductive through hole is through the 1st chip, wherein the 1st conductive through hole comprises the 1st contact and the 2nd contact, the 1st contact is positioned at the 1st side of the 1st chip, and the 2nd contact is positioned at the 2nd side of the 1st chip, and the 1st contact and the 2nd contact are partly or entirely overlapping in the vertical direction of the 1st chip.The 2nd conductive through hole is through the 1st chip, wherein the 2nd conductive through hole comprises the 3rd contact and the 4th contact, the 3rd contact is positioned at the 1st side of the 1st chip, and the 4th contact is positioned at the 2nd side of the 1st chip, and the 3rd contact and the 4th contact are partly or entirely overlapping in the vertical direction of the 1st chip.The 5th contact is positioned at the 1st side of the 1st chip, the 5th contact and the 3rd contact conducting.The 6th contact is positioned at the 2nd side of the 1st chip, the 6th contact and the 2nd contact conducting, and the 6th contact and the 5th contact are partly or entirely overlapping in the vertical direction of the 1st chip.The 7th contact is positioned at the 1st side of the 1st chip, the 7th contact and the 1st contact conducting.The 8th contact is positioned at the 2nd side of the 1st chip, the 8th contact and the 4th contact conducting, and the 8th contact and the 7th contact are partly or entirely overlapping in the vertical direction of the 1st chip.
Example embodiment discloses the layout method of a chip, comprise: form the 1st conductive through hole in the 1st chip, the 1st conductive through hole is through the 1st chip, the 1st conductive through hole comprises the 1st contact and the 2nd contact, the 1st contact is positioned at the 1st side of the 1st chip, the 2nd contact is positioned at the 2nd side of the 1st chip, and the 1st contact and the 2nd contact are partly or entirely overlapping in the vertical direction of the 1st chip.Form the 2nd conductive through hole in the 1st chip, the 2nd conductive through hole is through the 1st chip, the 2nd conductive through hole comprises the 3rd contact and the 4th contact, the 3rd contact is positioned at the 1st side of the 1st chip, the 4th contact is positioned at the 2nd side of the 1st chip, and the 3rd contact and the 4th contact are partly or entirely overlapping in the vertical direction of the 1st chip.Form 1st side of the 5th contact, the 5th contact and the 3rd contact conducting in the 1st chip.Form 2nd side of the 6th contact in the 1st chip, the 6th contact and the 2nd contact conducting, and the 6th contact and the 5th contact are partly or entirely overlapping in the vertical direction of the 1st chip.Form 1st side of the 7th contact, the 7th contact and the 1st contact conducting in the 1st chip.Form 2nd side of the 8th contact in the 1st chip, the 8th contact and the 4th contact conducting, and the 8th contact and the 7th contact are partly or entirely overlapping in the vertical direction of the 1st chip.
Based on above-mentioned, component structure and the lead and the conductive projection configuration mode of conductive through hole proposed on the chip layout structure.Signal can be by transmitting in various leads and the formed path of conductive projection in stacked chips.When Renewal Design, only need upgrade the conductive projection configuration mode and can reach demand.
Description of drawings
Figure 1A is the schematic diagram of an example embodiment chip layout structure.
Figure 1B is the local amplification stereogram of Figure 1A.
Fig. 1 C is that another stereogram is amplified in the part of Figure 1A.
Fig. 1 D is that another stereogram is amplified in the part of Figure 1A.
Fig. 2 A is the schematic diagram of existing chip layout structure.
Fig. 2 B is another schematic diagram of existing chip layout structure.
Fig. 3 A figure is another schematic diagram of an example embodiment chip layout structure.
Fig. 3 B figure is another schematic diagram of an example embodiment chip layout structure.
Fig. 4 is that an example embodiment chip layout structure is in the schematic diagram that singly connects pattern.
Fig. 5 is that an example embodiment chip layout structure is in the schematic diagram of transmission mode
Fig. 6 is that an example embodiment chip layout structure is in the schematic diagram of broadcast mode.
Fig. 7 is that an example embodiment chip layout structure is in the schematic diagram of switch mode.
Fig. 8 is an example embodiment chip layout method.
The main element symbol description:
100: the chip layout structure
101～108,201～208: contact
115,215,125,225: chip
216,217: conductive projection
109,110,209,210,251: conductive through hole
241: output element
242,243: input element
111～114,211～214,231,232,233: lead
221,222,223: holding wire
Embodiment
For above-mentioned feature and advantage can be become apparent, example embodiment cited below particularly, and conjunction with figs. is described in detail below.
Figure 1A illustrates the schematic diagram of an example embodiment chip layout structure.Figure 1B illustrates the local amplification stereogram of Figure 1A.With reference to Figure 1A and Figure 1B, chip layout structure 100 comprises the 1st conductive through hole 109 and the 2nd conductive through hole 110, and wherein conductive through hole 109 and 110 is through chip 115.In this enforcement demonstration example, conductive through hole 109 and 110 can be through-silicon-via, and (Through Silicon Via TSV), and forms the component structure of bifilar through-silicon-via (Twisted TSV).Conductive through hole 109 comprises the 1st contact 101 and the 2nd contact 105, and above-mentioned two contacts lay respectively at chip 115 upper and lower sides.In addition, contact 101 and contact 105 present partly or entirely overlapping in the vertical direction of chip 115, and Figure 1A with all overlapping be example.On the other hand, conductive through hole 110 comprises the 3rd contact 104 and the 4th contact 108, and above-mentioned two contacts also lay respectively at chip 115 upper and lower sides.Further, contact 104 and contact 108 present partly or entirely overlapping in the vertical direction of chip 115, and Figure 1A also with all overlapping be example.
The upside of chip 115 disposes the 5th contact 102 and the 7th contact 103, wherein contact 102 and contact 104 conductings, and contact 103 and contact 101 conductings.The mode of conducting can utilize the 3rd lead 113 to connect contact 102 and contact 104, and other utilizes the 1st lead 111 to connect contact 103 and contact 101.On the other hand, the downside of chip 115 disposes the 6th contact 106 and the 8th contact 107, wherein contact 106 and contact 105 conductings, and contact 107 and contact 108 conductings.The mode of conducting can utilize the 2nd lead 112 to connect contact 106 and contact 105, the 4 leads 114 connection contacts 107 and contact 108.Further, contact 102 and contact 106 present partly or entirely overlapping in the vertical direction of chip 115, and that contact 103 and contact 107 present in the vertical direction of chip 115 is partly or entirely overlapping, shown in Figure 1A be with all overlapping be example.
In view of the above, by the formed various paths of a plurality of contacts, a plurality of conductive through hole and a plurality of lead, signal (not illustrating) can transfer to chip 115 downsides by chip 115 upsides.In addition, lead 111～lead 114 can have the mode of various layouts in the vertical direction of chip 115, uses to form various signal transmission paths.For example on the vertical direction of chip 115, lead 111 can become arbitrarily angled, non-parallel with lead 112 or 90 degree.Lead 113 and lead 114 also can be in the vertical direction of chip 115 according to the aforesaid way layouts.Further, on the vertical direction of chip 115, layout type can be also that lead 111 and lead are 112 vertical, lead 112 is vertical with lead 113, and lead 113 is vertical with lead 114.
Except the local amplification stereogram that Figure 1B illustrated, chip layout structure 100 also has other possible layout type.Fig. 1 C and Fig. 1 D illustrate the part of Figure 1A and amplify another stereogram.With reference to Fig. 1 C, contact 101～104 is at chip 115 upsides, and contact 105～108 is at chip 115 downsides, all with the mode layout of linear array, therefore lead 111 can adopt the mode of serpentine pattern to walk around contact 102, and lead 113 can utilize the mode of serpentine pattern to walk around contact 104.On the other hand, with reference to Fig. 1 D, contact 101～104 is at chip 115 upsides, and contact 105～108 is at chip 115 downsides, and all with the mode layout shown in Fig. 1 D, so lead 111～114 also has corresponding layout.Further, Fig. 1 C, Fig. 1 D can adopt identical design with Figure 1B in the vertical direction of chip 115.In other words, on the vertical direction of chip 115, contact 101 is partly or entirely overlapping with contact 105, and contact 104 is partly or entirely overlapping with contact 108, and contact 102 is partly or entirely overlapping with contact 106, and contact 103 is partly or entirely overlapping with contact 107.
According to above-mentioned the described chip layout structure of example embodiment, in the application of actual chips layout, can reduce the layout cost than prior art.Fig. 2 A illustrates the schematic diagram of existing chip layout structure.With reference to Fig. 2 A, chip 125 comprises output element 241, and wherein output element 241 can be the output circuit of chip 125 inside.Output element 241 will be sent the input element 243 of signal (not illustrating) to chip 225, and then signal can be sent to the downside of chip 125 by the holding wire in the chip 125 221, lead 231 and conductive through hole 251.Then, signal is sent to the upside of chip 225 with lead 233, and in the end is sent to input element 243 via holding wire 223 by lead 232, conductive projection 216 again.
Fig. 2 B illustrates another schematic diagram of existing chip layout structure.With reference to Fig. 2 B, in the process of circuit design, may need to upgrade design originally.Contrast Fig. 2 A and Fig. 2 B, being designed to output element 241 and will sending the input element 243 of signal at Fig. 2 A script to chip 225.The design such as Fig. 2 B that upgrade, this moment, output element 241 will be sent the input element 242 of signal to chip 225.Therefore the part that needs to upgrade comprises lead 232, lead 233 and conductive projection 216.Further, Renewal Design must change Fig. 2 A at the RDL coiling of lead 232 with lead 233, and upgrades the configuration of conductive projection 216, uses the layout that meets Fig. 2 B, increases manufacturing cost.
On the other hand, the described chip layout structure of this example embodiment can reduce manufacturing cost in the application of actual chips layout.Fig. 3 A illustrates another schematic diagram of an example embodiment chip layout structure.With reference to Fig. 3 A, chip 115 comprises illustrated as described above this example embodiment chip layout structure, and chip 215 comprises contact 205～208.Further, output element 241 will be sent the input element 243 of signal (not illustrating) to chip 215, and then signal can be sent to the downside of chip 115 by the holding wire in the chip 115 221, lead 231, contact 101, conductive through hole 109, contact 105 and contact 106.Then, signal is sent to input element 243 by conductive projection 216, contact 206 with holding wire 223 again.
Fig. 3 B illustrates another schematic diagram of an example embodiment chip layout structure.In the process of circuit design, may need to upgrade design originally, design originally as shown in Figure 3A, and the design of upgrading is shown in Fig. 3 B.Contrast Fig. 3 A and Fig. 3 B, this moment, output element 241 will be sent the input element 242 of signal to chip 215.Therefore the part that need upgrade only comprises the layout of conductive projection 216.Can reduce manufacturing cost than prior art.
According to aforementioned chip layout structure, when a plurality of chips pile up, in order to allow signal penetrate between the chip that piles up, therefore need to form conductive projection between each layer chip, and utilize conductive projection to be coupled to the contact of each layer chip, use making signal can have various paths to penetrate between stacked chips.Further, in the design of one chip, can adopt conductive projection to reach the purpose that couples contact.Be example to pile up up and down two chips 115 and 215 in this example embodiment, and the correspondence position in chip 115 and 215 dispose above-mentioned bifilar through-silicon-via structure (being chip layout structure 100) separately.Arrangement according to conductive projection is divided into following five kinds of connection modes.
Singly connect pattern
Fig. 4 illustrates an example embodiment chip layout structure in the schematic diagram that singly connects pattern.Singly connecing under the pattern, only utilizing a conductive projection to connect between two chips.With reference to Fig. 4, has conductive projection 216 between the upside of the downside of chip 115 and chip 215, wherein conductive projection 216 optionally is coupled between two contacts, for example between contact 106 and the 5th contact 202, or between contact 108 and the 3rd contact 204, or between contact 107 and the 7th contact 203.In this enforcement demonstration example, conductive projection 216 is coupled between contact 105 and the 1st contact 201.
Illustrate the pattern that singly connects according to Fig. 4, the contact 101,103,105,106 of chip 115 and the contact 201,203,205,206 of chip 215 interconnect, therefore the signal (not illustrating) at chip 115 can be sent to the contact 201 and 203 of chip 215 via conductive through hole 109 from contact 101 (or contact 103) with conductive projection 216, even is sent to the 2nd contact 205 and the 6th contact 206 via the 3rd conductive through hole 209 further.Further, be coupled between contact 106 and the contact 202 when only conductive projection 216 being changed, or change and be coupled between contact 107 and the contact 203, or change when being coupled between contact 108 and the contact 204, the path that above-mentioned coupling mode forms can be changed accordingly.
Transmission mode
Fig. 5 illustrates an example embodiment chip layout structure in the schematic diagram of transmission mode.Under transmission mode, utilize two conductive projections to connect between two chips, each conductive projection couples the conductive through hole of two chips.With reference to Fig. 5, have conductive projection 216 and conductive projection 217 between the upside of the downside of chip 115 and chip 215, wherein conductive projection 216 is coupled between the contact 201 of the contact 105 of conductive through hole 109 and conductive through hole 209, and conductive projection 217 is coupled between the contact 204 of the contact 108 of conductive through hole 110 and the 4th conductive through hole 210.In view of the above, the contact 101 of chip 115, contact 103, contact 105, contact 106 interconnect with contact 201, contact 203, contact 205, the contact 206 of chip 215.On the other hand, the contact 102 of chip 115, contact 104, contact 107, contact 108 interconnect with contact 202, contact the 204, the 8th contact the 207, the 4th contact 208 of chip 215.
Broadcast mode
Fig. 6 illustrates an example embodiment chip layout structure in the schematic diagram of broadcast mode.Under broadcast mode, utilize two conductive projections 216 to be connected between two chips with 217, wherein a conductive projection 216 is coupled between contact 105 and 201, and another conductive projection 217 then is coupled to and connects between 106 and 202.In view of the above, can be sent to the contact 201,202,203 and 204 of chip 215 with conductive projection 217 via conductive through hole 109, conductive projection 216 from contact 101 (or contact 103) at the signal of chip 115, even further via conductive through hole 209 and 210 and be sent to contact 205,206,207 and 208.
By changing the position of conductive projection 216 and 217, can realize different broadcast routes.For example, conductive projection 216 changed be disposed between contact 107 and 203, be disposed between contact 108 and 204 and conductive projection 217 changed, then can be sent to the contact 201,202,203 and 204 of chip 215 via conductive through hole 110 from contact 104 (or contact 102) at the signal of chip 115.Again for example, if conductive projection 216 is disposed between contact 105 and 201, be disposed between contact 107 and 203 and conductive projection 217 changed, then can be sent to the contact 105,106,107 and 108 of chip 115 from contact 205 (or contact 206) via conductive through hole 209 at the signal of chip 215, even further via conductive through hole 109 and 110 and be sent to contact 101,102,103 and 104.
Switch mode
Fig. 7 illustrates an example embodiment chip layout structure in the schematic diagram of switch mode.Under switch mode, utilize two conductive projections to connect between two chips, wherein two all contacts that couple of conductive projection are neither is the contact of conductive through hole.With reference to Fig. 7, conductive projection 216 is coupled between contact 106 and the contact 202, and conductive projection 217 is coupled between contact 107 and the contact 203, and wherein contact 106, contact 202, contact 107 and contact 203 are neither is the contact of conductive through hole.In view of the above, the contact 101 of chip 115, contact 103, contact 105, contact 106 interconnect with contact 202, contact 204, contact 207, the contact 208 of chip 215.In addition, the contact 102 of chip 115, contact 104, contact 107, contact 108 interconnect with contact 201, contact 203, contact 205, the contact 206 of chip 215.
Sky connects pattern
Consider that based on the chip layout structure Design sky connects pattern for there is not conductive projection between two chips.With reference to Fig. 4, sky connects pattern chips 115 and does not have conductive projection 216 with chip 215, so the contact of chip 115 just can not interconnect with the contact of chip 215.Further, the signal on the contact of chip 115 just can not transfer to chip 215.
Except above-mentioned various connection modes, the chip layout structure also can have other design.For example at least one conductive projection is coupled at least one contact of a chip.With Fig. 3 A is example, and chip 115 comprises a conductive projection 216, and further design then can couple at least one conductive projection at the contact on the chip 115 101～108.On the other hand, consider, can form at least one conductive projection between two chips, use coupling two at least one contacts of chip based on design.The chip layout structure of Fig. 4 only comprises a conductive projection, and the chip layout structure of Fig. 5～Fig. 7 can comprise two conductive projections.And further design can form three or four conductive projections between two chips, uses that the contact of two chips is coupled.
According to aforementioned chip layout structure, Fig. 8 illustrates an example embodiment chip layout method.With reference to Fig. 8, run through forming conductive through hole 109 in chip 115, conductive through hole 109 comprises contact 101 and contact 105, above-mentioned two contacts lay respectively at the upper and lower sides of chip 115, and at the vertical direction of chip 115 partly or entirely overlapping (step S600).Run through forming conductive through hole 110 in chip 115, conductive through hole 110 comprises contact 104 and contact 108, and above-mentioned two contacts lay respectively at chip 115 upper and lower sides, and at the vertical direction of chip 115 partly or entirely overlapping (step S602).Form contact 102 in chip 115 upsides, contact 102 and contact 104 conductings (step S604).Form contact 103 in chip 115 upsides, contact 103 and contact 101 conductings (step S606).
According to aforementioned chip layout structure, and the explanation of the various connection modes that form, on the Application Design of actual chips layout, can reduce the layout cost.With the transmission mode of Fig. 5 and the switch mode of Fig. 7 is example, and transmission mode forms different paths with switch mode.If chip layout structure originally adopts the transmission mode of Fig. 5, then contact 102 can pass through contact 104, contact 108, contact 204, contact 208, and then is connected to contact 208.If want Renewal Design this moment, make contact 102 be connected to contact 206, then prior art can make chip 115 and the front and the back side of chip 215 all carry out the RDL coiling again, and upgrades the layout of conductive projection, uses to meet the change designing requirement.According to the explanation of this enforcement demonstration example, the mode that then only need change the conductive projection configuration just can reach the requirement of Renewal Design.Know clearly it, as long as the conductive projection configuration of upgrading in Fig. 5 transmission mode, and the conductive projection that forms Fig. 7 switch mode disposes, this moment, contact 102 just can be by, contact 108, contact 107, contact 107, contact 203, contact 201, contact 205, and then be connected to contact 206, reach the requirement of Renewal Design.
In sum, above-mentioned chip layout structure provides component structure and the lead and the conductive projection configuration mode of conductive through hole.By the configuration of lead and the component structure of conductive through hole, signal has various transmission paths in chip.By chip layout structure and conductive projection configuration mode, signal can be by transmitting in the formed path of various connection modes in stacked chips.When Renewal Design, only need upgrade the conductive projection configuration mode and can reach demand.
Though openly as above with example embodiment; but it is not in order to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when the content that can instruct according to above-mentioned example embodiment, disclose or hint is done a little change and retouching, so scope of patent protection should be as the criterion with the scope that claim was defined.
Claims (19)
1. the layout structure of a chip is characterized in that, comprising:
One the 1st conductive through hole, through one the 1st chip, wherein the 1st conductive through hole comprises one the 1st contact and one the 2nd contact, the 1st contact is positioned at one the 1st side of the 1st chip, the 2nd contact is positioned at one the 2nd side of the 1st chip, and the 1st contact and the 2nd contact are partly or entirely overlapping in the vertical direction of the 1st chip;
One the 2nd conductive through hole, through the 1st chip, wherein the 2nd conductive through hole comprises one the 3rd contact and one the 4th contact, the 3rd contact is positioned at the 1st side of the 1st chip, the 4th contact is positioned at the 2nd side of the 1st chip, and the 3rd contact and the 4th contact are partly or entirely overlapping in the vertical direction of the 1st chip;
One the 5th contact is positioned at the 1st side of the 1st chip, the 5th contact and the 3rd contact conducting;
One the 6th contact is positioned at the 2nd side of the 1st chip, the 6th contact and the 2nd contact conducting, and the 6th contact and the 5th contact are partly or entirely overlapping in the vertical direction of the 1st chip;
One the 7th contact is positioned at the 1st side of the 1st chip, the 7th contact and the 1st contact conducting; And
One the 8th contact is positioned at the 2nd side of the 1st chip, the 8th contact and the 4th contact conducting, and the 8th contact and the 7th contact are partly or entirely overlapping in the vertical direction of the 1st chip.
2. the layout structure of chip according to claim 1 is characterized in that, more comprises at least one conductive projection, and above-mentioned conductive projection is coupled to the 1st contact at least one contact to the 8th contact.
3. the layout structure of chip according to claim 1 is characterized in that, more comprises:
One the 3rd conductive through hole, through one the 2nd chip, wherein the 3rd conductive through hole comprises one the 9th contact and one the 10th contact, the 9th contact is positioned at one the 1st side of the 2nd chip, the 10th contact is positioned at one the 2nd side of the 2nd chip, and the 9th contact and the 10th contact are partly or entirely overlapping in the vertical direction of the 2nd chip;
One the 4th conductive through hole, through the 2nd chip, wherein the 4th conductive through hole comprises one the 11st contact and one the 12nd contact, the 11st contact is positioned at the 1st side of the 2nd chip, the 12nd contact is positioned at the 2nd side of the 2nd chip, and the 11st contact and the 12nd contact are partly or entirely overlapping in the vertical direction of the 2nd chip;
One the 13rd contact is positioned at the 1st side of the 2nd chip, the 13rd contact and the 11st contact conducting;
One the 14th contact is positioned at the 2nd side of the 2nd chip, the 14th contact and the 10th contact conducting, and the 14th contact and the 13rd contact are partly or entirely overlapping in the vertical direction of the 2nd chip;
One the 15th contact is positioned at the 1st side of the 2nd chip, the 15th contact and the 9th contact conducting; And
One the 16th contact is positioned at the 2nd side of the 2nd chip, the 16th contact and the 12nd contact conducting, and the 16th contact and the 15th contact are partly or entirely overlapping in the vertical direction of the 2nd chip.
4. the layout structure of chip according to claim 3 is characterized in that, more comprises a conductive projection, and this conductive projection is coupled between the 2nd contact and the 9th contact.
5. the layout structure of chip according to claim 3 is characterized in that, more comprises a conductive projection, and this conductive projection is coupled between the 4th contact and the 11st contact.
6. the layout structure of chip according to claim 3 is characterized in that, more comprises a conductive projection, and this conductive projection is coupled between the 6th contact and the 13rd contact.
7. the layout structure of chip according to claim 3 is characterized in that, more comprises a conductive projection, and this conductive projection is coupled between the 8th contact and the 15th contact.
8. the layout structure of chip according to claim 3, it is characterized in that, more comprise at least one conductive projection, above-mentioned conductive projection be coupled to the 1st contact at least one contact of the 8th contact and the 9th contact between at least one contact of the 16th contact.
9. the layout structure of chip according to claim 1 is characterized in that, more comprises one the 1st lead and one the 2nd lead, and wherein the 7th contact and the 1st contact utilize the 1st lead conducting, and the 6th contact and the 2nd contact utilize the 2nd lead conducting.
10. the layout structure of chip according to claim 9 is characterized in that, wherein the 1st lead and the 2nd lead are non-parallel in the vertical direction of the 1st chip.
11. the layout structure of chip according to claim 10 is characterized in that, wherein vertical direction the 1st lead at the 1st chip is vertical mutually with the 2nd lead.
12. the layout structure of chip according to claim 9 is characterized in that, more comprises one the 3rd lead and one the 4th lead, wherein the 5th contact and the 3rd contact utilize the 3rd lead conducting, and the 8th contact and the 4th contact utilize the 4th lead conducting.
13. the layout structure of chip according to claim 12, it is characterized in that wherein on the vertical direction of the 1st chip, the 1st lead is vertical mutually with the 2nd lead, the 3rd lead is vertical mutually with the 4th lead, and the 2nd lead is vertical mutually with the 3rd lead.
14. the layout method of a chip is characterized in that, comprising:
Form one the 1st conductive through hole in one the 1st chip, the 1st conductive through hole is through the 1st chip, the 1st conductive through hole comprises one the 1st contact and one the 2nd contact, the 1st contact is positioned at one the 1st side of the 1st chip, the 2nd contact is positioned at one the 2nd side of the 1st chip, and the 1st contact and the 2nd contact are partly or entirely overlapping in the vertical direction of the 1st chip;
Form one the 2nd conductive through hole in the 1st chip, the 2nd conductive through hole is through the 1st chip, the 2nd conductive through hole comprises one the 3rd contact and one the 4th contact, the 3rd contact is positioned at the 1st side of the 1st chip, the 4th contact is positioned at the 2nd side of the 1st chip, and the 3rd contact and the 4th contact are partly or entirely overlapping in the vertical direction of the 1st chip;
Form 1st side of one the 5th contact, the 5th contact and the 3rd contact conducting in the 1st chip;
Form 2nd side of one the 6th contact in the 1st chip, the 6th contact and the 2nd contact conducting, and the 6th contact and the 5th contact are partly or entirely overlapping in the vertical direction of the 1st chip;
Form 1st side of one the 7th contact, the 7th contact and the 1st contact conducting in the 1st chip; And
Form 2nd side of one the 8th contact in the 1st chip, the 8th contact and the 4th contact conducting, and the 8th contact and the 7th contact are partly or entirely overlapping in the vertical direction of the 1st chip.
15. the layout method of chip according to claim 14 is characterized in that, more comprises:
Form one the 3rd conductive through hole in one the 2nd chip, the 3rd conductive through hole is through the 2nd chip, the 3rd conductive through hole comprises one the 9th contact and one the 10th contact, the 9th contact is positioned at one the 1st side of the 2nd chip, the 10th contact is positioned at one the 2nd side of the 2nd chip, and the 9th contact and the 10th contact are partly or entirely overlapping in the vertical direction of the 2nd chip;
Form one the 4th conductive through hole in the 2nd chip, the 4th conductive through hole is through the 2nd chip, the 4th conductive through hole comprises one the 11st contact and one the 12nd contact, the 11st contact is positioned at the 1st side of the 2nd chip, the 12nd contact is positioned at the 2nd side of the 2nd chip, and the 11st contact and the 12nd contact are partly or entirely overlapping in the vertical direction of the 2nd chip;
Form 1st side of one the 13rd contact, the 13rd contact and the 11st contact conducting in the 2nd chip;
Form 2nd side of one the 14th contact in the 2nd chip, the 14th contact and the 10th contact conducting, and the 14th contact and the 13rd contact are partly or entirely overlapping in the vertical direction of the 2nd chip;
Form 1st side of one the 15th contact, the 15th contact and the 9th contact conducting in the 2nd chip; And
Form 2nd side of one the 16th contact in the 2nd chip, the 16th contact and the 12nd contact conducting, and the 16th contact and the 15th contact are partly or entirely overlapping in the vertical direction of the 2nd chip.
16. the layout method of chip according to claim 15 is characterized in that, more comprises:
Form one the 1st conductive projection between the 1st side of the 2nd side of the 1st chip and the 2nd chip, use making the 2nd contact and the 9th contact conducting.
17. the layout method of chip according to claim 16 is characterized in that, more comprises:
Form one the 2nd conductive projection between the 1st side of the 2nd side of the 1st chip and the 2nd chip, use making the 4th contact and the 16th contact conducting, the 6th contact and the 13rd contact conducting or the 8th contact and the 15th contact conducting.
18. the layout method of chip according to claim 15 is characterized in that, more comprises:
Form one the 1st conductive projection between the 1st side of the 2nd side of the 1st chip and the 2nd chip, use making the 6th contact and the 13rd contact conducting.
19. the layout method of chip according to claim 18 is characterized in that, more comprises:
Form one the 2nd conductive projection between the 1st side of the 2nd side of the 1st chip and the 2nd chip, use making the 8th contact and the 15th contact conducting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101353300A CN101866892B (en) | 2009-04-20 | 2009-04-20 | Chip layout structure and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101353300A CN101866892B (en) | 2009-04-20 | 2009-04-20 | Chip layout structure and method |
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| Publication Number | Publication Date |
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| CN101866892A CN101866892A (en) | 2010-10-20 |
| CN101866892B true CN101866892B (en) | 2011-12-07 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2664198Y (en) * | 2003-08-18 | 2004-12-15 | 威盛电子股份有限公司 | Multi-chip packaging structure |
| CN1741270A (en) * | 2004-08-26 | 2006-03-01 | 财团法人工业技术研究院 | Stereo-stacking packaging structure |
| CN1819158A (en) * | 2005-01-28 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN101211903A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | RF module package structure and its forming method |
| CN101232008A (en) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | Multi-chips package and method of forming the same |
-
2009
- 2009-04-20 CN CN2009101353300A patent/CN101866892B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2664198Y (en) * | 2003-08-18 | 2004-12-15 | 威盛电子股份有限公司 | Multi-chip packaging structure |
| CN1741270A (en) * | 2004-08-26 | 2006-03-01 | 财团法人工业技术研究院 | Stereo-stacking packaging structure |
| CN1819158A (en) * | 2005-01-28 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device |
| CN101211903A (en) * | 2006-12-29 | 2008-07-02 | 育霈科技股份有限公司 | RF module package structure and its forming method |
| CN101232008A (en) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | Multi-chips package and method of forming the same |
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| CN101866892A (en) | 2010-10-20 |
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