CN101866883B - Manufacture method of CMOS (Complementary Metal Oxide Semiconductor) image sensor - Google Patents
Manufacture method of CMOS (Complementary Metal Oxide Semiconductor) image sensor Download PDFInfo
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- CN101866883B CN101866883B CN2009100495624A CN200910049562A CN101866883B CN 101866883 B CN101866883 B CN 101866883B CN 2009100495624 A CN2009100495624 A CN 2009100495624A CN 200910049562 A CN200910049562 A CN 200910049562A CN 101866883 B CN101866883 B CN 101866883B
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Abstract
The invention relates to a manufacture method of a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The method comprises the following steps of: providing a pixel unit territory comprising a photodiode active region, a transistor active region and a transistor gate region; carrying out manual optical proximity correction on the transistor gate region of the territory to obtain a pixel unit territory subjected to the correction of the gate region; optimizing the original territory according to the pixel unit territory subjected to the correction of the gate region, wherein the area of the photodiode active region of the optimized pixel unit territory is larger than that of the photodiode active region of the pixel unit territory; and preparing a pixel unit according to the optimized pixel unit territory. The prepared CMOS image sensor meets the requirement for technological parameters of devices, has high fill factor and effectively improves the image quality of the CMOS image sensor.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of manufacturing approach of cmos image sensor.
Background technology
Present charge coupled device (charge coupled device; CCD) be main practicability solid-state image sensing device; Have that the noise of reading is low, dynamic range is big, the response sensitivity advantages of higher; (Complementary-Metal-Oxide-Semiconductor, CMOS) the compatible mutually shortcoming of technology promptly is that the imageing sensor on basis is difficult to realize that single-chip is integrated with the charge coupled device but CCD has the complementary metal oxide semiconductors (CMOS) that is difficult to main flow simultaneously.And cmos image sensor (CMOS ImageSensor; CIS) owing to adopted identical CMOS technology; Can pel array and peripheral circuit be integrated on the same chip; Compare with charge coupled device, cmos image sensor has that volume is little, in light weight, low in energy consumption, convenient programming, be easy to control and advantage that average unit cost is low.
Cmos image sensor comprises pixel unit array, and each pixel cell has generally included photodiode (being generally) and transistor (being generally three or four).As shown in Figure 1, the pixel cell domain comprises photodiode active area a11, transistor active area a12, transistor gate area a13.Photodiode active area a11 and be defined as fill factor, curve factor with the corresponding total pixel cell area ratio of said photodiode active area a11, said fill factor, curve factor is one of most important factor of weighing cmos image sensor picture quality.
On the basis that the whole pixel unit array gross area can't change; One of approach that improves the cmos image sensor fill factor, curve factor is increase photodiode active area a11 area; And above-mentioned approach can make the interval of photodiode active area a11 and transistor gate area a13 or transistor gate area a13 width reduce; Make the reliability of device reduce, make yield of devices reduce.
The inventor finds; Pixel cell domain as shown in Figure 1 is when actual fabrication is on silicon substrate; Because the limitation (such as the drift of critical size and alignment precision) of lithographic process; As shown in Figure 2, transistor gate area is formed on that transistor gate area pattern a13 has certain radian on the pattern b13 contrast domain on the silicon substrate at the turning.Cause effective gate regions width W
EffGate regions width W less than reality
Total, and advanced optical adjacent calibration correction is with high costs owing to needing repeatedly pump back test, general can be applied in 90 nanometers and the following live width manufacturing process.So when the pixel cell layout design, consider the limitation of semiconductor technology processing procedure, in order to make the pixel cell of preparation can not lose efficacy, the width of gate regions can suitably relax and satisfies effective gate regions width W
EffIn fact actual demand has so just limited the area of photodiode active area.
Summary of the invention
The problem that the present invention solves provides a kind of manufacturing approach of cmos image sensor, can effectively improve the picture quality of cmos image sensor.
For addressing the above problem, the present invention provides a kind of manufacturing approach of cmos image sensor, comprises, the pixel cell domain is provided; Said pixel cell domain comprises photodiode active area, transistor active area, transistor gate area; Transistor gate area to said domain is carried out manual optical proximity correction, obtains revising the pixel cell domain after the gate regions; Pixel cell domain according to after the correction gate regions is optimized photodiode active area and transistor gate area, and the photodiode active area area of the pixel cell domain of said optimization is greater than the photodiode active area area of said pixel cell domain; Pixel cell domain according to after optimizing prepares pixel cell.
Compared with prior art, the present invention has the following advantages: the transistor gate area through to said domain is handled, the pixel cell domain of the cmos image sensor that is optimized; The photodiode active area area of the pixel cell domain of the cmos image sensor of said optimization is greater than the photodiode active area area of the pixel cell domain of said cmos image sensor; Utilize the pixel cell domain of the cmos image sensor of optimizing to prepare cmos image sensor.Make the cmos image sensor for preparing satisfy device technology parameter and fill factor, curve factor height, improve the picture quality of cmos image sensor effectively.
Description of drawings
Fig. 1 is a pixel cell domain sketch map;
Fig. 2 is the sketch map of pixel cell domain actual fabrication on silicon substrate shown in Figure 1;
Fig. 3 is the execution mode flow chart of the manufacturing approach of cmos image sensor;
Fig. 4 to Fig. 9 is the sketch map of embodiment of the manufacturing approach of cmos image sensor of the present invention.
Embodiment
The present invention provides a kind of execution mode of manufacturing approach of cmos image sensor as shown in Figure 3, comprises the steps:
Step S101 provides the pixel cell domain; Said pixel cell domain comprises photodiode active area, transistor active area, transistor gate area;
Step S102 carries out manual optical proximity correction to the transistor gate area of said domain, obtains revising the pixel cell domain after the gate regions;
Step S103; Pixel cell domain according to after the correction gate regions is optimized photodiode active area and transistor gate area, and the photodiode active area area of the pixel cell domain of said optimization is greater than the photodiode active area area of said pixel cell domain;
Step S104 prepares pixel cell according to the pixel cell domain after optimizing.
In the above-described embodiment, adopt manual optical proximity correction, make the turning radian distortion of transistor gate area reduce, make the developed width of gate regions greater than described gate regions width through transistor gate area to said domain; Correspondingly; Domain according to manual optical proximity correction; Photodiode active area and transistor gate area are optimized; The photodiode active area area of the feasible pixel cell domain of optimizing has improved the fill factor, curve factor of cmos image sensor greater than the photodiode active area area of said pixel cell domain, improves the picture quality of cmos image sensor effectively.
Do detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
With reference to figure 4, the pixel cell domain is provided; Said pixel cell can be the pixel cell of cmos image sensor; Said CMOMS image sensor pixel cells can comprise three transistors or four transistors; Said transistor gate area can or be a square for rectangle.
Present embodiment is that example is done exemplary illustrated with four transistorized pixel cells.Said pixel cell domain comprises photodiode active area a11, transistor active area a12, the first transistor gate regions a13 of parallel arranged, transistor seconds gate regions a14, the 3rd transistor gate area a15, independently the 4th transistor gate area a16.Said pixel cell domain is active area domain and gate regions domain stack sketch map.
Wherein, photodiode active area a11 width W 1 is 2.8 microns; The first transistor gate regions a13 length L 2 is 0.28 micron; Transistor seconds gate regions a14 length L 3 is 0.31 micron, and the 3rd transistor gate area a15 length L 4 is 0.28 micron, and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 width W 4 are 0.63 micron; Photodiode active area a11 and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 G3 at interval are 0.39 micron; The interval G1 of the first transistor gate regions a13 and transistor seconds gate regions a14 is 0.2 micron, and the interval G2 of transistor seconds gate regions a14 and the 3rd transistor gate area a15 is 0.2 micron; Transistor active area a12 width W 5 is 0.35 micron.
With reference to figure 5, Fig. 6, the transistor gate area of said domain is carried out manual optical proximity correction, obtain revising the pixel cell domain of the cmos image sensor after the gate regions.
Manually the optical proximity correction system adds auxiliary pattern b30 for said transistor gate area according to process conditions such as the transistor gate area b10 of said domain, exposure sources, photoresistance type, numerical aperture, exposure energy, the depths of focus.
If the transistor gate area b10 of said domain directly makes public; Because the limitation (such as the drift of critical size and alignment precision) of lithographic process; The figure c10 that exposure obtains can have certain distortion with respect to transistor gate area b10; Particularly; The figure that the right angle exposure of said transistor gate area b10 obtains has certain radian, and the width of definition rectangular crystal tube grid district b10 exposure distortion range is Z, and Z is the difference of the effective width Z2 of the transistor gate area layout width Z1 of original layout and the figure c10 that exposure obtains.
Manually the optical proximity correction system is a rectangle according to transistor gate area b10; Add the auxiliary pattern b30 of rectangle in the transistor gate area rectangular angular; The diagonal of said rectangle auxiliary pattern is centered close to the summit of transistor gate area rectangular angular; The length of said rectangle auxiliary pattern is X, and wide is Y, with reference to the figure of b20 among the figure 5.The auxiliary pattern b30 of different rectangles can obtain the width Z of different exposure distortion ranges.
According to photodiode active area a11 width W 1 is 2.8 microns; The first transistor gate regions a13 length L 2 is 0.28 micron; Transistor seconds gate regions a14 length L 3 is 0.31 micron, and the 3rd transistor gate area a15 length L 4 is 0.28 micron, and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 width W 4 are 0.63 micron; Photodiode active area a11 and brilliant the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 G3 at interval are 0.39 micron; The interval G1 of the first transistor gate regions a13 and transistor seconds gate regions a14 is 0.2 micron, and the interval G2 of transistor seconds gate regions a14 and the 3rd transistor gate area a15 is 0.2 micron; Transistor active area a12 width W 5 is 0.35 micron and waits the domain parameter; And exposure sources can be ASML 248nm DUV scan exposure equipment, and the photoresistance type can be Rohm HaasDUV2000, and numerical aperture can be 0.80; Exposure energy is that 38 millis are burnt; The depth of focus is a parameter such as 0.15 micron, and manually the optical proximity correction system obtains the long X of said rectangle auxiliary pattern, the scope of wide Y; 0.05 micron＜the X of length of said rectangle auxiliary pattern＜0.15 micron, the wide 0.045 micron＜Y of said rectangle auxiliary pattern＜0.145 micron.
With reference to figure 6, to the auxiliary pattern b30 of transistor gate area rectangular angular interpolation rectangle, and analogue exposure or actual exposure, measure the width Z that perhaps calculates rectangular crystal tube grid district b10 exposure distortion range.Specifically comprising according to the photoresistance type and choose the length X of auxiliary pattern b30 and the combination of width Y, in the present embodiment, is that Rohm Haas DUV2000 is an example with the photoresistance, and that chooses length X and width Y is combined as X=0.05 micron, Y=0.045 micron; The X=0.05 micron, the Y=0.065 micron; The X=0.05 micron, the Y=0.085 micron; The X=0.05 micron, the Y=0.105 micron; The X=0.05 micron, the Y=0.125 micron; The X=0.05 micron, the Y=0.145 micron; The X=0.07 micron, the Y=0.045 micron; The X=0.07 micron, the Y=0.065 micron; The X=0.07 micron, the Y=0.085 micron; The X=0.07 micron, the Y=0.105 micron; The X=0.07 micron, the Y=0.125 micron; The X=0.07 micron, the Y=0.145 micron; The X=0.09 micron, the Y=0.045 micron; The X=0.09 micron, the Y=0.065 micron; The X=0.09 micron, the Y=0.085 micron; The X=0.09 micron, the Y=0.105 micron; The X=0.09 micron, the Y=0.125 micron; The X=0.09 micron, the Y=0.145 micron; The X=0.11 micron, the Y=0.045 micron; The X=0.11 micron, the Y=0.065 micron; The X=0.11 micron, the Y=0.085 micron; The X=0.11 micron, the Y=0.105 micron; The X=0.11 micron, the Y=0.125 micron; The X=0.11 micron, the Y=0.145 micron; The X=0.13 micron, the Y=0.045 micron; The X=0.13 micron, the Y=0.065 micron; The X=0.13 micron, the Y=0.085 micron; The X=0.13 micron, the Y=0.105 micron; The X=0.13 micron, the Y=0.125 micron; The X=0.13 micron, the Y=0.145 micron; The X=0.15 micron, the Y=0.045 micron; The X=0.15 micron, the Y=0.065 micron; The X=0.15 micron, the Y=0.085 micron; The X=0.15 micron, the Y=0.105 micron; The X=0.15 micron, the Y=0.125 micron; The X=0.15 micron, the Y=0.145 micron; Difference analogue exposure or actual exposure, correspondence obtains the Z=0.12 micron; The Z=0.12 micron; The Z=0.13 micron; The Z=0.105 micron; The Z=0.105 micron; The Z=0.1 micron; The Z=0.103 micron; The Z=0.1 micron; The Z=0.125 micron; The Z=0.102 micron; The Z=0.102 micron; The Z=0.1 micron; The Z=0.09 micron; The Z=0.09 micron; The Z=0.095 micron; The Z=0.09 micron; The Z=0.085 micron; The Z=0.085 micron; The Z=0.08 micron; The Z=0.065 micron; The Z=0.07 micron; The Z=0.055 micron; The Z=0.053 micron; The Z=0.05 micron; The Z=0.065 micron; The Z=0.05 micron; The Z=0.065 micron; The Z=0.025 micron; The Z=0.035 micron; The Z=0.03 micron; The Z=0.065 micron; The Z=0.065 micron; The Z=0.05 micron; The Z=0.046 micron; The Z=0.035 micron; The Z=0.045 micron.The Z value of the minimum that obtains is 0.025 micron, and corresponding X value is 0.13 micron, and the Y value is 0.105 micron.
With length X is 0.13 micron; Width Y value is the transistor gate area that 0.105 micron auxiliary pattern adds the pixel cell domain; Obtain the pixel cell domain of the cmos image sensor after the manual optical proximity correction gate regions; With reference to figure 7, said domain comprises that photodiode active area a11 width W 1 is 2.8 microns; The first transistor gate regions a13 length L 2 is 0.28 micron; Transistor seconds gate regions a14 length L 3 is 0.31 micron, and the 3rd transistor gate area a15 length L 4 is 0.28 micron, and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 width W 4 are 0.63 micron; Photodiode active area a11 and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 G3 at interval are 0.39 micron; The interval G1 of the first transistor gate regions a13 and transistor seconds gate regions a14 is 0.2 micron, and the interval G2 of transistor seconds gate regions a14 and the 3rd transistor gate area a15 is 0.2 micron; Transistor active area a12 width W 5 is 0.35 micron.Wherein auxiliary pattern length d 1 is 0.13 micron, and width d2 is 0.105 micron, and d3 length is 0.07 micron at interval, and d4 length is 0.05 micron at interval, and d5 length is 0.09 micron at interval, and d6 length is 0.025 micron at interval, and d7 length is 0.04 micron at interval.
The first transistor gate regions a13 of figure, transistor seconds gate regions a14, the 3rd transistor gate area a15 exposure back aliasing reduce after the said manual optical proximity correction, and the gate regions effective width that the gate regions effective width ratio original layout of exposure is directly made public is big.
With reference to figure 8; Pixel cell domain according to after the correction gate regions is optimized photodiode active area and transistor gate area, and the photodiode active area area of the pixel cell domain of said optimization is greater than the photodiode active area area of said pixel cell domain.
In the present embodiment, said domain comprises that specifically photodiode active area a11 width W 1 is 2.8 microns; The first transistor gate regions a13 length L 2 is 0.28 micron; Transistor seconds gate regions a14 length L 3 is 0.31 micron, and the 3rd transistor gate area a15 length L 4 is 0.28 micron, and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 width W 4 are 0.63 micron; Photodiode active area a11 and brilliant the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 G3 at interval are 0.39 micron; The interval G1 of the first transistor gate regions a13 and transistor seconds gate regions a14 is 0.2 micron, and the interval G2 of transistor seconds gate regions a14 and the 3rd transistor gate area a15 is 0.2 micron; Transistor active area a12 width W 5 is 0.35 micron.
The domain that obtains after the optimization comprises that photodiode active area a11 width W 1 ' is 3.05 microns, and the first transistor gate regions a13 length L 2 is 0.28 micron; Transistor seconds gate regions a14 length L 3 is 0.31 micron, and the 3rd transistor gate area a15 length L 4 is 0.28 micron, and the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 width W 4 ' are 0.55 micron; Photodiode active area a11 and brilliant the first transistor gate regions a13, transistor seconds gate regions a14, the 3rd transistor gate area a15 G3 ' at interval are 0.2 micron; The interval G1 of the first transistor gate regions a13 and transistor seconds gate regions a14 is 0.2 micron, and the interval G2 of transistor seconds gate regions a14 and the 3rd transistor gate area a15 is 0.2 micron; Transistor active area a12 width W 5 is 0.35 micron; Wherein auxiliary pattern length d 1 is 0.13 micron, and width d2 is 0.105 micron, and d3 length is 0.07 micron at interval, and d4 length is 0.05 micron at interval, and d5 length is 0.09 micron at interval, and d6 length is 0.025 micron at interval, and d7 length is 0.04 micron at interval.
With reference to figure 9, prepare pixel cell according to the pixel cell domain after optimizing.Specifically comprise, the pixel cell domain after the said optimization is prepared into mask; According to mask patterns, exposure forms corresponding pixel cell.
Particularly, the pixel cell domain after the said optimization is prepared into mask.The technology of preparing of said mask can be known technology of preparing, specifically can for, said layout drawing is the cover needle drawing, specifically can be plotted on the graph paper for domain is amplified 100 times to 1000 times; Said alignment is desired to make money or profit with the needle drawing machine engraving on negative; Utilize plate-making technology to pass through processing procedures such as first minification, focusing, reduction magnification adjustment, exposure and chemical treatment successively, obtain the first minification domain of said domain.Through final minification such as figure alignment of orientation, the selection of stepping spacing technology, utilize final reaction system to prepare said mask said first minification domain.
The process of said exposure can be known exposure technique, specifically can for, said mask is positioned on the mask stage of exposure sources; Wafer to be made public is positioned on the wafer platform of exposure sources; With described mask and described wafer alignment; Described wafer is made public by photoresistance type, numerical aperture, exposure energy, the depth of focus set.
In the present embodiment; Said mask is positioned on the mask stage of exposure sources; Detection is positioned over the position of the mask on the mask stage; And when having exceeded preset site error scope in the position of said mask with respect to the skew of preset mask position, adjustment is placed on the position of the said mask on the mask stage, meets the requirement of preset mask position until the position of said mask.
Specifically, exposure sources can be ASML 248nm DUV scan exposure equipment.Can said mask accurately be positioned on the mask stage by first navigation system that is connected with mask stage.Specifically comprise; Said mask is positioned on the mask stage; The position of the said mask that first navigation system calculating primary importance transducer that is connected with mask stage detects is with respect to the skew of preset mask position; The skew of position and compares: if in preset error range, can think then that said mask aims at mask stage with preset site error scope; If the skew of position has exceeded preset error range, adjustment is placed on the position of the said mask on the mask stage, until the skew of the position of said mask in the error range of position.
Wafer to be made public is positioned on the wafer platform.Specifically comprise, survey the position be placed on the wafer on the wafer platform, and when having exceeded preset site error scope in the position of wafer with respect to the skew of preset wafer position, the position of adjustment wafer.In the present embodiment, can wafer accurately be positioned on the wafer platform by second navigation system that is connected with the wafer platform.
The position of the wafer that second navigation system calculating second place transducer that is connected with the wafer platform detects is with respect to the skew of preset wafer position; The skew of position and compares: if in preset error range, can think then that wafer aims at the wafer platform with preset site error scope; If the skew of position has exceeded preset error range, adjustment is placed on the position of the wafer on the wafer platform, until the skew of the position of wafer in the error range of position.
With described mask and described wafer alignment.First navigation system and second navigation system can accurately move mask stage and wafer platform or accurately move mask stage or wafer platform, with alignment mask and wafer according to the mask alignment mark of mask and the wafer alignment mark of wafer.
Described wafer is made public by photoresistance type, numerical aperture, exposure energy, the depth of focus set.Comprise that specifically the photoresistance type can be Rohm Haas DUV2000, numerical aperture can be 0.80, and exposure energy is that 38 millis are burnt, and the depth of focus is 0.15 micron.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (7)
1. the manufacturing approach of a cmos image sensor is characterized in that, comprising:
The pixel cell domain is provided; Said pixel cell domain comprises photodiode active area, transistor active area, transistor gate area;
Transistor gate area to said domain is carried out manual optical proximity correction, obtains revising the pixel cell domain after the gate regions;
Pixel cell domain according to after the correction gate regions is optimized photodiode active area and transistor gate area; Saidly photodiode active area is optimized step for according to the pixel cell domain of revising after the gate regions according to the pixel cell domain of revising after the gate regions; Reduction gate regions width, and increase the photodiode active area width accordingly; The photodiode active area area of the pixel cell domain of said optimization is greater than the photodiode active area area of said pixel cell domain;
Pixel cell domain according to after optimizing prepares pixel cell.
2. the manufacturing approach of cmos image sensor as claimed in claim 1 is characterized in that, said pixel cell domain is three transistorized pixel cells or four transistorized pixel cells.
3. the manufacturing approach of cmos image sensor as claimed in claim 1 is characterized in that, described transistor gate area is a rectangle.
4. the manufacturing approach of cmos image sensor as claimed in claim 1 is characterized in that, said manual optical proximity correction is used for the figure of a plurality of rectangle parallel arranged.
5. the manufacturing approach of cmos image sensor as claimed in claim 1; It is characterized in that; The transistor gate area of said domain is carried out manual optical proximity correction to be comprised; The width of definition rectangular crystal tube grid district's exposure distortion range is Z, and Z is the difference of the effective width of the transistor gate area layout width of original layout and the figure that exposure obtains; Manually the optical proximity correction system is a rectangle according to transistor gate area, and at the auxiliary pattern of transistor gate area rectangular angular interpolation rectangle, the diagonal of said rectangle auxiliary pattern is centered close to transistor gate area rectangle angle summit; The length of said rectangle auxiliary pattern is X, the wide Y of being; The auxiliary pattern of different rectangles obtains the width Z of different exposure distortion ranges; To the auxiliary pattern of transistor gate area rectangular angular interpolation rectangle, and analogue exposure or actual exposure, the width Z that perhaps calculates rectangular crystal tube grid district exposure distortion range measured; Choose the length X of auxiliary pattern and the combination of Y according to the photoresistance type, simulate respectively or actual exposure, thus the corresponding value that obtains Z; The transistor gate area of the auxiliary pattern adding pixel cell domain of the corresponding X value of the Z value of the minimum that selection obtains, Y value obtains the pixel cell domain of the cmos image sensor after the manual optical proximity correction gate regions.
6. the manufacturing approach of cmos image sensor as claimed in claim 5 is characterized in that, described auxiliary pattern is square or rectangle.
7. the manufacturing approach of cmos image sensor as claimed in claim 5; It is characterized in that the parameter of said auxiliary pattern is that manual optical proximity correction system generates according to original layout, exposure sources, photoresistance type, numerical aperture, exposure energy, the depth of focus.
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| CN1405634A (en) * | 2001-09-18 | 2003-03-26 | 联华电子股份有限公司 | Mask-pattern correction method |
| JP2006276491A (en) * | 2005-03-29 | 2006-10-12 | Toshiba Corp | Mask pattern correcting method and photomask manufacturing method |
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| CN1405634A (en) * | 2001-09-18 | 2003-03-26 | 联华电子股份有限公司 | Mask-pattern correction method |
| JP2006276491A (en) * | 2005-03-29 | 2006-10-12 | Toshiba Corp | Mask pattern correcting method and photomask manufacturing method |
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