CN101866880B - Method for separating base plate and semiconductor layer - Google Patents
Method for separating base plate and semiconductor layer Download PDFInfo
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Abstract
The invention relates to a method for separating a base plate and a semiconductor layer. The method is characterized in that a pattern silicon dioxide layer is formed between a temporary base plate and the semiconductor layer; then, the temporary base plate is separated from the pattern silicon dioxide layer by a secondary wet type etching way. The temporary base plate is removed by using the secondary wet type etching way, thereby avoiding damaging the structure of the semiconductor layer by using a the laser lift off (LLO) method. In addition, by utilizing the secondary wet type etching method, the manufacture process step is simpler, and the technical cost is decreased. On a vertical semiconductor element, the light emitting benefit of the element is increased due to the irregular surface formed by a manufacture process. In addition, by utilizing the wet type etching in the manufacture process, the batch amplification can be increased, and the cost of the manufacture process is decreased.
Description
Technical field
The present invention is the structure and the manufacturing approach thereof of relevant a kind of III group-III nitride semiconductor light-emitting component, particularly relevant for the method for separating base plate and semiconductor layer with formation III group-III nitride vertical light-emitting element.
Background technology
In recent years, LED mainly is placed on the LED (High-Power Light Emitting Diode) that lifting is the high luminous efficiency on basis with GaN to focus in research and development.Therefore, GaN LED extends on the field that is applied in high brightness rapidly, and the back light unit of various screens for example is to replace traditional cold-cathode tube or bulb gradually.
The luminous method of many LED of improvement is arranged, for example use reflector, alligatoring light-emitting area, flip chip technology (fct) of isotropic directivity etc.Every rising 10 degree of the temperature of element will reduce by 5% luminous efficiency.Because sapphire substrate is conductivity and the not good material of thermal conductivity, makes the luminous heat that produces of element to leave rapidly.For solving the problem of heat radiation, therefore derived and removed the method formation perpendicular elements of sapphire substrate with Laser.
Laser-stripping method (Laser Lift Off) is to arrive the interface between sapphire substrate and the GaN layer to launch high-octane laser, the high temperature of generation be enough to let GaN layer forming liquid attitude metal Ga and gaseous state N and be decomposed.Yet laser-stripping method (Laser lift off) has many shortcomings; For example the high temperature of laser is inhomogeneous in the branch of GaN layer; Make easily that the temperature in zone partly is too high and destroy structure; Or through after the laser lift-off, some metal Ga may remain on the GaN layer, must increase by one program again and remove metal Ga etc.
Figure 1A～1B is U.S. US6, and the substrate of 071, No. 795 patent separates sketch map.Shown in Figure 1A, on a sapphire substrate 102, form a Disengagement zone 104 and a silicon nitride layer 106 in regular turn earlier, then knitting layer 108 is coated the surface of silicon nitride layer 106.Through the adhesiveness of knitting layer 108, again that a silicon substrate 110 is bonding each other with the layered structure of aforementioned sapphire substrate 102.Utilize a laser beam 112 to penetrate sapphire substrate 102 surfaces, thereby make the material breakdown (Decomposition) of Disengagement zone 104 with sub irradiation abscission zone 104.Remove the material that remains in silicon nitride layer 106 after decomposing again, just can obtain the assembly of silicon substrate 110 and silicon nitride layer 106.Shown in Figure 1B, owing between silicon substrate 110 and the silicon nitride layer 106 nonconducting knitting layer 108 is arranged, therefore still can't be as the foundation structure of perpendicular elements.And knitting layer 108 can influence adhesion results if coating or material selection are good, even causes the silicon nitride layer 106 generation defectives of film.
Fig. 2 is that the substrate of 6,740, No. 604 patents of U.S. US separates sketch map.Prior art is similar among this prior art and Figure 1A～1B.First semiconductor layer 202 and second semiconductor layer 204 also shine interfaces through laser beam 206, thereby make second semiconductor layer 204 producing decomposition at the interface, can first semiconductor layer 202 be separated on second semiconductor layer 204 at last.This second semiconductor layer 204 can be the rete that is formed on the substrate, just replaces first semiconductor layer 202 with a substrate, again with this two separation.
Fig. 3 is the sketch map before the substrate of 6,746, No. 889 patents of U.S. US separates.Elder generation is a plurality of epitaxial loayers of growth on a substrate 302, and it comprises one first type conductor region, 304, one luminous PN junction district 306 and one second type conductor region 308.From the Cutting Road 312 of these a plurality of epitaxial loayers of the second type conductor region, 308 directions cutting, so on substrate 302, form the light-emitting diode nude film 310 of a plurality of separation.Again that the second type conductor region 308 is bonding with submounts (Submount) 314.With similar aforementioned prior art, penetrate substrate 302 surfaces with laser beam 316 equally, and make substrate 302 separate with the first type conductor region 304.The light-emitting diode nude film 310 that separates can take off on submounts 314, thereby carries out package fabrication process.Clearly, cut these a plurality of epitaxial loayers after, push each other because of external force easily when each light-emitting diode nude film 310 is bonded in submounts 314, so easily crystalline substance collapses (Die Crack) and causes damage.
Fig. 4 is that the substrate of 6,617, No. 261 patents of U.S. US separates sketch map.Form gallium nitride layer 404 at a sapphire substrate 402 earlier, form a plurality of irrigation canals and ditches 408 with the etching manufacturing process at gallium nitride layer 404 again.With viscose one silicon substrate 406 is bonded in gallium nitride layer 404 surfaces of these tool irrigation canals and ditches 408 then, and the laser beam 410 irradiation sapphire substrates 402 that send with ultraviolet PRK.Laser beam 410 passes transparent sapphire substrate 402, further contacts and decomposes gallium nitride layer 404, so just can obtain one have a gallium nitride layer 404 silicon substrate 406.Yet these gallium nitride layer 404 decomposition place also need with the remaining gallium of salt acid treatment, and repair this surface and just can carry out follow-up extension manufacturing process.
Fig. 5 A～5C is the sketch map of the laterally overgrown of 6,627, No. 974 patents of U.S. US.This prior art is utilized in the purpose that the repulsion between the different crystallographic system in the epitaxial process reaches structural design.See also shown in Fig. 5 A, on sapphire substrate 502, form an III-V group iii nitride layer 504 earlier.Formation one patterned silicon dioxide layer 506 and aforementioned pattern silicon dioxide layer 506 comprise a plurality of holes 508 on an aforementioned III-V group iii nitride layer 502.Then by shown in the 2B figure, the 2nd III-V group iii nitride layer 510 slowly forms a T type structure from the hole 508 of aforementioned patterned silicon dioxide layer.Because silicon dioxide layer is the characteristic of polycrystalline series, make monocrystalline system the III-V group iii nitride layer directly extension on the polycrystalline series surface, thereby produce a kind of epitaxial lateral overgrowth (Epitaxially Lateral Overgrowth; ELOG) phenomenon makes the time-delay outside of III-V group nitride material and earth silicon material can produce continuous situation and a space 514 occur.Get back to shown in the 2B figure; The 2nd III-V group-III nitride 510 of this prior art is connected an III-V group iii nitride layer 504 beginning epitaxial growths from the hole 508 of patterned silicon dioxide layer; Up to the 2nd III-V group iii nitride layer 510 grow to silicon dioxide layer 506 surfaces slowly change epitaxial lateral overgrowth into, stop when almost being covered in aforementioned silicon dioxide layer 506.This moment, the 2nd III-V group iii nitride layer 510 seemed the T type structure of a marshalling from tangent plane, and overlooking then is a discontinuous surface (not shown).Shown in 3C figure, then on aforementioned the 2nd III-V group iii nitride layer 510, form the 3rd III-V group iii nitride layer 512 again.Because the manufacturing process of present technique must pass in and out epitaxy machine platform by secondary, causes yields to descend easily.In addition, the control laterally overgrown and must not contact in the extension on both sides before promptly stop to be unusual difficulty at once, cause the instability of manufacturing process.
Fig. 6 A～6B is academic journal " The Fabrication of Vertical Light-Emitting DiodesUsing Chemical Lift-Off Process "; IEEE Photonics Techology Letters, Vol.20, NO.3; Feburary 1,2008.This method is to be formed on the sapphire substrate 602 as a resilient coating with CrN layer 604.Form GaN layer 616 at aforementioned CrN layer 604 then.Mode with Wet-type etching CrN layer 604 removes sapphire substrate 602 at last.Shown in Fig. 6 A, prior to forming a CrN layer 604 on the sapphire substrate 602.Then on aforementioned CrN layer 604, form GaN layer 616.Aforementioned GaN layer 616 comprises a n type GaN layer 606, an active layers 608, p type GaN layer 610 and a p type contact layer 612 in regular turn.On aforementioned GaN layer 616, form a metal substrate 614 then.Shown in Fig. 6 B, utilize CrN layer 604 as sacrifice layer, again with the mode etching CrN layer 604 of Wet-type etching to remove sapphire substrate 602.Though can directly utilize Wet-type etching directly to remove sapphire substrate 602 from CrN layer 604; Number is not higher but the lattice between CrN layer 604 and the GaN layer 616 matches; Directly on the CrN layer, be prone to the GaN extension to cause the bad of extension, also influence luminous benefit simultaneously.
Therefore, the present invention obtains the higher perpendicular elements of extension quality except improving above-mentioned shortcoming, and surface coarsening capable of using is to promote light extraction benefit.
Summary of the invention
In view of in the above-mentioned background of invention, in order to meet the demand of industry interests, the present invention provides the method for a kind of separating base plate and semiconductor layer.Its method comprises the following step: a temporary substrate is provided; Forming a patterned silicon dioxide layer is positioned on the aforementioned temporary substrate; The growth semi-conductor layer is positioned on the aforementioned pattern silicon dioxide layer; Etching aforementioned pattern silicon dioxide layer for the first time, and for the second time the interface of the aforementioned temporary substrate of etching and this semiconductor layer to remove aforementioned temporary substrate.
The present invention provides the method for a kind of separating base plate and semiconductor layer in addition; Its method comprises the following step: a temporary substrate is provided; The patterned silicon dioxide layer that formation one comprises hole is positioned on this temporary substrate, forms a hole repairing layer and is positioned on this patterned silicon dioxide layer that comprises hole, forms semi-conductor layer and is positioned on this hole repairing layer; This comprises the patterned silicon dioxide layer of hole etching for the first time, and this hole repairing layer of etching for the second time is to remove this temporary substrate.
Be etched to Wet-type etching the first time of the present invention, with the above-mentioned patterned silicon dioxide layer of BOE chemical etching liquor etching.
Be etched to Wet-type etching the second time of the present invention, with the interface of KOH, H2SO4 or this temporary substrate of H3PO4 chemical etching liquor etching and this semiconductor layer.
Hole repairing layer of the present invention is the III-V group-III nitride.
Method of the present invention also comprises formation one metallic mirror surface on the aforesaid semiconductor layer, forms a conductive material layer on the aforementioned metal minute surface.
Semiconductor layer of the present invention comprises a n type conductting layer, a luminescent layer and a p type conductting layer, and an electronic barrier layer is between aforementioned light emission layer and aforementioned p type conductting layer.
Patterned silicon dioxide layer of the present invention is continuous or partly continuous pattern, and its figure is cylindrical grooves, polygonal cylindrical recesses or strip groove.
Patterned silicon dioxide layer thickness of the present invention is between 0.05 μ m～2.0 μ m, and its width is between 0.1 μ m～10.0 μ m.
The present invention removes temporary substrate with the etched mode of chemical wet and can avoid semiconductor layer because of laser-stripping method (Laser Lift Off; LLO) destroy structure.In addition, the etched mode of chemical wet can let manufacturing technology steps simpler, and technical costs reduces.On the vertical semiconductor element, because the irregular surface that manufacturing process forms more increases the luminous benefit of element.In addition, in manufacturing process, use Wet-type etching also can increase a batch amplification, reduce the cost of manufacturing process.
Description of drawings
Figure 1A～1B is that the substrate of 6,071, No. 795 patents of U.S. US separates sketch map;
Fig. 2 is that the substrate of 6,740, No. 604 patents of U.S. US separates sketch map;
Fig. 3 is the sketch map before the substrate of 6,746, No. 889 patents of U.S. US separates;
Fig. 4 is that the substrate of 6,617, No. 261 patents of U.S. US separates sketch map;
Fig. 5 A～5C is the epitaxial lateral overgrowth sketch map of 6,627, No. 974 patents of U.S. US;
Fig. 6 A～6B is that the substrate of academic journal IEEE Photonics Techology Letters separates sketch map (direction of arrow is the etching direction among Fig. 6 B);
Fig. 7 is substrate of the present invention and semiconductor layer method flow diagram;
Fig. 8 A～8I is that substrate of the present invention and semi-conductive each step form sketch map (direction of arrow is the etching direction among Fig. 8 F and Fig. 8 G, and the direction of arrow is light emission direction among Fig. 8 I); And
Fig. 9 A～9D is the various pattern sketch map of silicon dioxide layer of the present invention.
Wherein, description of reference numerals is following:
(prior art)
102 sapphire substrates, 406 silicon substrates
104 Disengagement zone, 408 irrigation canals and ditches
106 silicon nitride layers, 410 laser beams
108 knitting layers, 502 sapphire substrates
110 silicon substrates 504 an III-V family nitrogen compound layer
112 laser beams, 506 silicon dioxide layers
202 first semiconductor layers, 508 holes
204 second semiconductor layers 510 the 2nd III-V family nitrogen compound layer
206 laser beams, 512 IIIIII-V family nitrogen compound layers
302 substrates, 514 spaces
304 first type conductor regions, 602 sapphire substrates
306 luminous PN junction districts, 604 CrN layers
308 second type conductor regions, 606 n type GaN layers
310 light-emitting diode nude films, 608 active layers
312 Cutting Roads, 610 p type GaN layers
314 submounts, 612 p type contact layers
316 laser beams, 614 metal substrates
402 sapphire substrates, 616 GaN layers
404 gallium nitride layers
(the present invention)
802 temporary substrates, 818 n type conductting layers
804 silicon dioxide layers, 820 luminescent layers
806 thickness (T), 822 electronic barrier layers
808 recess width (W), 824 p type conductting layers
810 grooves, 826 metallic mirror surfaces
812 resilient coatings, 828 conductive material layers
814 spaces, 830 columns
816 semiconductor layers, 832 silicon dioxide sheaf spaces
Embodiment
The method that the present invention is a kind of separating base plate and semiconductor layer in this direction of inquiring into.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention is not defined in the specific details that the those of ordinary skill of semiconductor optoelectronic manufacturing process is known.On the other hand, well-known composition or step are not described in the details, with the restriction of avoiding causing the present invention unnecessary.Preferred embodiment meeting of the present invention is described in detail as follows, yet except these detailed descriptions, the present invention can also be implemented among other the embodiment widely, and scope of the present invention constrained not, and its scope with claim is as the criterion.
A purpose of the present invention is with simple manufacturing process separating base plate and semiconductor layer and obtains the higher luminous III group-III nitride semiconductor light-emitting component of an extension quality.
Another object of the present invention makes technical costs reduce for oversimplifying the manufacturing process of vertical semiconductor light-emitting component.
A purpose more of the present invention is for increasing the light extraction benefit of perpendicular elements.
For achieving the above object, the present invention provides the method for a kind of separating base plate and semiconductor layer.Its method comprises the following step: a temporary substrate is provided; Forming a patterned silicon dioxide layer is positioned on the aforementioned temporary substrate; The growth semi-conductor layer is positioned on the aforementioned pattern silicon dioxide layer; The silicon dioxide layer of etching aforementioned patternization for the first time, and for the second time the interface of the aforementioned temporary substrate of etching and this semiconductor layer to remove aforementioned temporary substrate.
The present invention provides the method for a kind of separating base plate and semiconductor layer in addition; Its method comprises the following step: a temporary substrate is provided; The patterned silicon dioxide layer that formation one comprises hole is positioned on this temporary substrate, forms a hole repairing layer and is positioned on this patterned silicon dioxide layer that comprises hole, forms semi-conductor layer and is positioned on this hole repairing layer; This comprises the patterned silicon dioxide layer of hole etching for the first time, and this hole repairing layer of etching for the second time is to remove this temporary substrate.
Be etched to Wet-type etching the first time of the present invention, with the above-mentioned patterned silicon dioxide layer of BOE chemical etching liquor etching.
Be etched to Wet-type etching the second time of the present invention, with the interface of KOH, H2SO4 or this temporary substrate of H3PO4 chemical etching liquor etching and this semiconductor layer.
Hole repairing layer of the present invention is an III-V family nitrogen compound.
Method of the present invention also comprises formation one metallic mirror surface on the aforesaid semiconductor layer, forms a conductive material layer on the aforementioned metal minute surface.
Semiconductor layer of the present invention comprises a n type conductting layer, a luminescent layer and a p type conductting layer, and an electronic barrier layer is between aforementioned light emission layer and aforementioned p type conductting layer.
Luminescent layer of the present invention is single heterojunction structure, double-heterostructure, single quantum well layer or multiple quantum trap layer structure.
Semiconductor layer of the present invention is AlxInyGa1-x-yN, wherein 0≤x≤1 and 0≤y≤1.
Metal mirror material of the present invention is silver (Ag) or an aluminium silver alloy (Al/Ag alloy), conductive material layer type of being diamond, copper (Cu), copper-tungsten (Cu/W alloy) or nickel (Ni).
Temporary substrate of the present invention is sapphire (Al2O3), carborundum (SiC), silicon, zinc oxide (ZnO), magnesia (MgO) or GaAs (GaAs).
Patterned silicon dioxide layer of the present invention is continuous or partly continuous pattern, and its figure is cylindrical grooves, polygonal cylindrical recesses or strip groove.
Patterned silicon dioxide layer thickness of the present invention is between 0.05 μ m～2.0 μ m, and its width is between 0.1 μ m～10.0 μ m.
Please refer to Fig. 7, be main formation method flow diagram of the present invention.First step forms a patterned silicon dioxide layer on a temporary substrate.With chemical vapour deposition technique (Chemical VaporDeposition; CVD) or the method for low temperature sputter (Sputtering) is deposited on earth silicon material on one temporary substrate and forms skim.Mode plated film with low temperature can reduce the injury to element, and is also more stable to the deposition quality of silicon dioxide layer.Aforementioned low temperature is between 100 ℃ to 300 ℃, and preferable temperature is about 150 ℃.Form the photoresistance film then in the surface of aforementioned silicon dioxide layer, again with photoetching process (Photolithography) with the photoresistance film patterning, make and estimate that etching partly appears.Aforesaid photoresistance film can be selected positive photoresistance or negative photoresistance according to the demand of manufacturing process.At last with (the Inductively coupled plasma etcher of Wet-type etching, dry-etching or inductance type electric paste etching system; ICP) carry out the patterning manufacturing process to obtain a patterned silicon dioxide layer.
Second step forms semi-conductor layer on the patterned silicon dioxide layer.For improving the extension quality of semiconductor layer, form an III group-III nitride resilient coating earlier on the silicon dioxide layer of patterning.Because silicon dioxide layer belongs to polycrystalline series, make monocrystalline system the III group iii nitride layer directly extension on the polycrystalline series surface, thereby produce a kind of epitaxial lateral overgrowth (Epitaxially Lateral Overgrowth; ELOG) phenomenon.In epitaxial process, III group iii nitride layer and silicon dioxide layer can produce discontinuous space.The III group nitride material that from hole, begins to grow up can form a plane resilient coating up to the III group nitride material that is connected the other end with the mode that side direction is grown up after arriving the silicon dioxide laminar surface.Then on aforementioned III group-III nitride resilient coating, form semi-conductor layer.Organic metal vapour deposition process capable of using (Metal OrganicChemical Vapor Deposition; MOCVD) or molecular beam epitaxy (Molecular BeamEpitaxy; MBE) etc. technology is deposited on semiconductor light emitting structure on the aforementioned resilient coating.The aforesaid semiconductor layer comprises a n type conductting layer, a luminescent layer, an electronic barrier layer and a p type conductting layer.
Third step forms a metallic mirror surface on semiconductor layer.Utilize vapor deposition (Evaporation) or the method for sputter (Sputtering) forms a thin metal layer on the aforesaid semiconductor layer, the light in order to the reflective semiconductor layer is launched increases the gain of light of light-emitting area.
The 4th step forms a conductive material layer on metallic mirror surface.Utilize vapor deposition (Evaporation) or the method for sputter (Sputtering) forms a conductive material layer on metallic mirror surface, or provide a conductive material layer to be bonding on the aforementioned metal minute surface.But the heat radiation of aforementioned conductive material layer accelerated semiconductor layer and raising conductivity.
The 5th step, the etched pattern silicon dioxide layer.The present invention removes silicon dioxide layer with the chemical wet etching method.Selection can and be allocated to proper proportion with the chemical solution of oxide reaction, and silicon dioxide layer is immersed in the chemical solution, utilizes chemical solution and earth silicon material generation chemical reaction to remove silicon dioxide layer.After accomplishing the removing of silicon dioxide layer, can stay column III group-III nitride is connected with temporary substrate.
The 6th step, the interface of etching semiconductor layer and temporary substrate is to remove temporary substrate.Chemical wet etching for the second time then select can with the chemical solution of III group-III nitride reaction.When chemical solution infiltrates the interface of III group-III nitride and temporary substrate, can temporary substrate and semiconductor layer be separated.Corrode part through chemical solution this moment and can produce irregular surface, can increase the luminous benefit of semiconductor layer.
Above-mentioned its implementation content of the inventive method flow chart with the structural representation of collocation diagram with each step, is introduced the generation type of structure of the present invention and each step in detail.
Please refer to shown in Fig. 8 A, a temporary substrate 802 is provided, on aforementioned temporary substrate 802, form a patterned silicon dioxide layer 804.Aforementioned temporary substrate 802 can be sapphire (Al2O3), carborundum (SiC), silicon, zinc oxide (ZnO), magnesia (MgO) or GaAs (GaAs).Utilize chemical vapour deposition technique (Chemical Vapor Deposition again; CVD) or the method for low temperature sputter (Sputtering) is deposited on earth silicon material on one temporary substrate 802 and forms skim 804.Mode plated film with low temperature can reduce the injury to element, and also more stable to the quality of silicon dioxide layer 804.Next form the photoresistance film in the surface of aforementioned silicon dioxide layer 804, with photoetching process (Photolithography) the photoresistance film patterning is made again and estimate that etching partly appears.At last with (the Inductively coupled plasma etcher of Wet-type etching, dry-etching or inductance type electric paste etching system; ICP) carry out the patterning manufacturing process to obtain a patterned silicon dioxide layer 804.Aforementioned pattern silicon dioxide layer 804 can be continuously or the pattern of partial continuous.Please refer to Fig. 9 A～9D, be the various pattern sketch map of silicon dioxide layer.Like Fig. 9 A is the column type groove pattern, and Fig. 9 B is a hexagonal column type groove pattern, and Fig. 9 C is a quadrangular prism type groove pattern, and Fig. 9 D is the strip groove pattern.Except aforesaid pattern, do not limit other various patterns yet.Aforementioned the 9A～9C figure belongs to continuous pattern, and earlier figures 9D is the pattern of partial continuous.In addition, get back to shown in Fig. 8 A the thickness (Thickness that aforementioned silicon dioxide layer 804 is preferable; T) 806 between 0.05 μ m～2.0 μ m, preferable recess width (Width; W) 808 between 0.1 μ m～10.0 μ m.
Then please refer to shown in Fig. 8 B,, form an III group-III nitride resilient coating 812 earlier on patterned silicon dioxide layer 804 for improving the extension quality of semiconductor layer.Silicon dioxide layer belongs to polycrystalline series because that lattice is unworthy of number is too high, make monocrystalline system the III group iii nitride layer directly extension on the polycrystalline series surface, mat and produce a kind of epitaxial lateral overgrowth (Epitaxially Lateral Overgrowth; ELOG) phenomenon.Therefore, from epitaxial process, III group-III nitride resilient coating 812 can produce discontinuous space 814 with patterned silicon dioxide layer 804.The present invention utilizes aforesaid characteristic, utilizes chemical vapour deposition technique (ChemicalVapor Deposition; CVD) the method III group nitride material that from groove 810, begins to grow up; After arriving silicon dioxide layer 804 surfaces; Aforementioned III group nitride material can form a resilient coating plane up to the III group-III nitride that is attached to the other end with the mode that side direction is grown up, and produces one space 814 with silicon dioxide layer 804.It is discontinuous that aforementioned interspace 814 makes that silicon dioxide layer and III group-III nitride resilient coating 812 cause, and can increase the response area of follow-up Wet-type etching, removes silicon dioxide layer 804 sooner.Aforementioned III group-III nitride resilient coating 812 can be AlxInyGa1-x-yN, wherein 0≤x≤1 and 0≤y≤1.
Moreover, please refer to shown in Fig. 8 C, form semi-conductor layer 816 on aforementioned III group-III nitride resilient coating 812.Aforesaid semiconductor layer 816 comprises a n type conductting layer 818, a luminescent layer 820, an electronic barrier layer 822 and a p type conductting layer 824.Organic metal vapour deposition process capable of using (Metal OrganicChemical Vapor Deposition; MOCVD) or molecular beam epitaxy (Molecular BeamEpitaxy; MBE) etc. technology is deposited on above-mentioned semiconductor layer 816 on the aforementioned III group-III nitride resilient coating 812.At first mix the atom of four families to form n type conductting layer 818 on III group-III nitride resilient coating 812.Be silicon atom (Si) in the present embodiment, and the precursor of silicon can silicomethane (SiH4) or silicon ethane (Si2H6) in the Metalorganic chemical vapor deposition board.The generation type of n type conductting layer 818 is mixed the gallium nitride layer (GaN) of silicon atom (Si) or gallium nitride layer or the aluminium gallium nitride alloy layer (AlGaN) that aluminium gallium nitride alloy layer (AlGaN) to low concentration mixes silicon atom (Si) by high concentration in regular turn.Gallium nitride layer (GaN) or aluminium gallium nitride alloy layer (AlGaN) that high concentration is mixed silicon atom (Si) can provide preferable conductive effect between the n type electrode.
Then be to form a luminescent layer 820 on n type conductting layer 818.Wherein luminescent layer 820 can be single heterojunction structure, double-heterostructure, single quantum well layer or multiple quantum trap layer structure.At present multiple quantum trap layer structure, just structures of multiple quantum trap layer/barrier layer of adopting more.The quantum well layer can use InGaN (InGaN), and barrier layer can use the ternary structural of aluminium gallium nitride alloy (AlGaN) etc.In addition, also can adopt quad arrangement, just use aluminum indium gallium nitride (AlxInyGa1-x-yN) simultaneously as quantum well layer and barrier layer.The ratio of wherein adjusting aluminium and indium makes the ability rank of aluminum indium gallium nitride lattice can become the barrier layer on high energy rank and the quantum well layer on low energy rank respectively.Luminescent layer 820 can the Doped n-type or the impurity (dopant) of p type, can be the impurity of Doped n-type and p type simultaneously, also can undope fully.And, can be that the quantum well layer mixes and barrier layer undopes, the quantum well layer undopes and barrier layer mixes, quantum well layer and barrier layer all mixes or quantum well layer and barrier layer all undope.Moreover, also can carry out the doping (delta doping) of high concentration in the part zone of quantum well layer.
Afterwards, on luminescent layer 820, form the electronic barrier layer 822 of a p type conducting.The electronic barrier layer 822 of p type conducting comprises first kind of III-V family semiconductor layer, and second kind of III-V family semiconductor layer.The energy gap of these two kinds of III-V family semiconductor layers is different; And has periodically repeated deposition on above-mentioned luminescent layer 820; Before periodically repeated deposition action can form the higher electronic barrier layer of energy barrier (energy barrier is higher than the energy barrier of active illuminating layer), in order to stop polyelectron (e-) overflow luminescent layer 820.Aforementioned first kind of III-V family semiconductor layer can be aluminum indium nitride gallium (AlxInyGa1-x-yN) layer, and aforementioned second kind of III-V family semiconductor layer can be aluminum indium nitride gallium (AluInvGa1-u-vN) layer.Wherein, 0＜x≤1,0≤y＜1, x+y≤1,0≤u＜1,0≤v≤1 and u+v≤1.When x=u, y ≠ v.In addition, aforementioned III-V family semiconductor layer also can be gallium nitride (GaN), aluminium nitride (AlN), indium nitride (InN), aluminium gallium nitride alloy (AlGaN), InGaN (InGaN), aluminum indium nitride (AlInN).
At last, mix the atom of two families to form p type conductting layer 824 on electronic barrier layer 822.Be magnesium atom in the present embodiment.And the precursor of magnesium can be CP2Mg in the Metalorganic chemical vapor deposition board.The generation type of p type conductting layer 824 is mixed the gallium nitride layer (GaN) of magnesium atom (Mg) or gallium nitride layer or the aluminium gallium nitride alloy layer (AlGaN) that aluminium gallium nitride alloy layer (AlGaN) to high concentration is mixed magnesium atom (Mg) by low concentration in regular turn.Gallium nitride layer (GaN) or aluminium gallium nitride alloy layer that high concentration is mixed magnesium atom (Mg) can provide preferable conductive effect between the p type electrode.
Shown in Fig. 8 D, form a metallic mirror surface 826 on aforesaid semiconductor layer 816.Light to the light-emitting area that metallic mirror surface 826 main refraction semiconductor layers 816 are sent is to increase the light efficiency benefit of light-emitting area.The method of vapor deposition capable of using (Evaporation) or sputter (Sputtering) forms a thin metal layer on aforesaid semiconductor layer 816.Aforementioned metal minute surface 826 materials can be silver (Ag) or aluminium silver alloy (Al/Agalloy).
Shown in Fig. 8 E, form a conductive material layer 828 on aforementioned metal minute surface 826.Utilization utilizes vapor deposition (Evaporation) or the method for sputter (Sputtering) forms a conductive material layer 828 on metallic mirror surface 826, or provides a conductive material layer 828 to be bonding on the aforementioned metal minute surface 826.But the heat radiation of aforementioned conductive material layer 828 accelerated semiconductor layers and raising conductivity.Aforementioned conductive material layer 828 type of can be diamonds, copper (Cu), copper-tungsten (Cu/W alloy) or nickel (Ni).
Next the mode with the secondary Wet-type etching removes aforementioned temporary substrate 802.For the first time Wet-type etching please refer to shown in Fig. 8 F, through the choosing and allocating of chemical solution, silicon dioxide layer 804 is immersed in the aforementioned chemical solution.The mode that adds UV irradiation raising solution temperature with the ultrasonic waves concussion is quickened the chemical reaction between aforementioned chemical solution and the aforementioned silicon dioxide layer.The temperature of aforementioned chemical solution is approximately high to about 150 ℃.Aforesaid chemical solution can be selected buffered oxide etch liquid (Buffer Oxide Etcher; BOE), its main etch silicon dioxide (Silicon Dioxide; SiO2) or silicon nitride (SiliconNitride; Si3N4).Aforementioned buffered oxide etch liquid is the mixed liquor of amine fluoride (NH4F) solution and hydrofluoric acid (HF); Its compound method can be amine fluoride (NH4F) solution of about 40% percentage by weight of preparation, prepares the buffered oxide etch liquid of written treaty 10% percent by volume again with hydrofluoric acid (HF) solution of about 49% percentage by weight of concentration.More careful explanation, the about 90 g of deionized water for stirring of pouring about 135ml into of amine fluoride (NH4F) solid of taking out the transparent grain shape are dissolved.Amine fluoride (NH4F) solution that takes out about 180ml with measuring bottle is got about 49% the about 20ml of hydrofluoric acid (HF) solution in addition again and is poured into and be mixed together the preparation of promptly accomplishing buffered oxide etch liquid to even in the aforementioned container to a container.When chemical solution corrodes the inside to silicon dioxide layer; Owing between III group-III nitride resilient coating 812 and the silicon dioxide layer 804 space 814 is arranged; Aforementioned interspace 814 can increase the contact area of chemical solution and aforementioned silicon dioxide layer, quickens the speed that silicon dioxide layer is corroded by chemical solution.Remaining a plurality of III group-III nitride columns 830 were connected with temporary substrate 802 after last silicon dioxide layer was etched and accomplishes.
Then be the Wet-type etching second time.Please refer to shown in Fig. 8 G, chemical solution is infiltrated in the structure through the space 832 of original silicon dioxide layer, to corrode the aforementioned temporary substrate 802 of interfacial separation of a plurality of III group-III nitride columns 830 and temporary substrate 802.Chemical solution can be potassium hydroxide (PotassiumHydroxide; KOH), sulfuric acid (Sulfuric Acid; H2SO4) or phosphoric acid (Phosphoric Acid; H3PO4).In the process of the Wet-type etching second time, still add that with the ultrasonic waves concussion mode of UV irradiation raising solution temperature increases the chemical reaction rate between aforementioned chemical solution and the aforementioned III group-III nitride column 830.At last, please refer to shown in 8I figure and Fig. 8 H, when aforementioned temporary substrate 802 separated with a plurality of III group-III nitride columns 830, the surface of III group-III nitride resilient coating 812 can form irregular, and this irregular surface can increase the luminous benefit of semiconductor layer.
The explanation of to sum up stating, the present invention are removed temporary substrate with the etched mode of chemical wet and can be avoided semiconductor layer because of laser-stripping method (Laser Lift Off; LLO) destroy structure.In addition, the etched mode of chemical wet can let manufacturing technology steps simpler, and technical costs reduces.On the vertical semiconductor element, because the irregular surface that manufacturing process forms more increases the luminous benefit of element.In addition, in manufacturing process, use Wet-type etching also can increase a batch amplification, reduce the cost of manufacturing process.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need in the scope of its additional claim, understand, except above-mentioned detailed description, the present invention can also implement in other embodiment widely.Above-mentionedly being merely preferred embodiment of the present invention, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being accomplished under the disclosed spirit and changes or modification, all should be included in the claim.
Claims (10)
1. the method for separating base plate and semiconductor layer comprises the following step:
One temporary substrate is provided;
Forming a patterned silicon dioxide layer is positioned on this temporary substrate;
Epitaxial lateral overgrowth growth semi-conductor layer on this patterned silicon dioxide layer so that form discontinuous space between this semiconductor layer and the patterned silicon dioxide layer;
This patterned silicon dioxide layer of etching for the first time; And
The interface of this temporary substrate of etching and this semiconductor layer is to remove this temporary substrate for the second time.
2. the method for separating base plate and semiconductor layer comprises the following step:
One temporary substrate is provided;
The patterned silicon dioxide layer that formation one comprises hole is positioned on this temporary substrate;
Forming a hole repairing layer is positioned on this patterned silicon dioxide layer that comprises hole;
Epitaxial lateral overgrowth forms semi-conductor layer on this hole repairing layer so that the discontinuous space of formation between this semiconductor layer and the patterned silicon dioxide layer that contains hole;
This comprises the patterned silicon dioxide layer of hole etching for the first time; And
This hole repairing layer of etching for the second time is to remove this temporary substrate.
3. the method for separating base plate according to claim 1 and 2 and semiconductor layer, wherein this is etched to Wet-type etching for the first time, with this patterned silicon dioxide layer of BOE chemical etching liquor etching.
4. the method for separating base plate according to claim 1 and semiconductor layer, wherein this etching second time is with KOH, H2SO4 or this temporary substrate of H3PO4 chemical etching liquor etching.
5. the method for separating base plate according to claim 2 and semiconductor layer, wherein this etching second time is with KOH, H2SO4 or this hole repairing layer of H3PO4 chemical etching liquor etching.
6. the method for separating base plate according to claim 5 and semiconductor layer, wherein this hole repairing layer is an III-V family nitrogen compound.
7. the method for separating base plate according to claim 1 and 2 and semiconductor layer wherein also comprises formation one metallic mirror surface on this semiconductor layer, forms a conductive material layer on this metallic mirror surface.
8. the method for separating base plate according to claim 7 and semiconductor layer, wherein this metal mirror material is silver or aluminium silver alloy, this conductive material layer type of being diamond, copper, copper-tungsten or nickel.
9. the method for separating base plate according to claim 1 and 2 and semiconductor layer, wherein this patterned silicon dioxide layer is continuous or partly continuous pattern, and is cylindrical grooves, polygonal cylindrical recesses or strip groove.
10. the method for separating base plate according to claim 9 and semiconductor layer, wherein this patterned silicon dioxide layer thickness is between 0.05 μ m～2.0 μ m, and the recess width of this patterned silicon dioxide layer is between 0.1 μ m～10.0 μ m.
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| CN102456778B (en) * | 2010-10-26 | 2014-11-05 | 展晶科技(深圳)有限公司 | Manufacturing method for light-emitting diode chips |
| KR101105868B1 (en) * | 2010-11-08 | 2012-01-16 | 한국광기술원 | Method for preparing group iii-nitride substrate using chemical lift off |
| CN102117869B (en) | 2011-01-21 | 2013-12-11 | 厦门市三安光电科技有限公司 | Method for stripping substrate of LED |
| US9263255B2 (en) * | 2012-03-19 | 2016-02-16 | Seoul Viosys Co., Ltd. | Method for separating epitaxial layers from growth substrates, and semiconductor device using same |
| CN103633194A (en) * | 2012-08-22 | 2014-03-12 | 联胜光电股份有限公司 | Light-emitting diode and growth substrate separation method |
| CN104993023B (en) * | 2015-05-29 | 2018-06-05 | 上海芯元基半导体科技有限公司 | A kind of method that method using chemical attack removes growth substrates |
| CN105047769B (en) * | 2015-06-19 | 2017-12-29 | 安徽三安光电有限公司 | A kind of light-emitting diodes tube preparation method that substrate desquamation is carried out using wet etching |
| CN109103091B (en) * | 2018-07-11 | 2021-11-09 | 西安电子科技大学 | Ga2O3Epitaxial layer transfer method of base MOSFET device |
| CN109244026B (en) * | 2018-07-23 | 2022-02-18 | 西安电子科技大学 | Transfer method of epitaxial layer of semiconductor device |
| CN109119531B (en) * | 2018-08-13 | 2020-01-07 | 武汉大学 | Method for manufacturing flexible sensor |
| CN109192670A (en) * | 2018-08-17 | 2019-01-11 | 中国科学院上海微系统与信息技术研究所 | Flexible semiconductor laminated film and preparation method thereof |
| CN111115563A (en) * | 2019-12-23 | 2020-05-08 | 湖南大学 | Method for stripping functional material by full-dry method |
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