CN101866877A - Through hole forming method - Google Patents
Through hole forming method Download PDFInfo
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- CN101866877A CN101866877A CN200910049284A CN200910049284A CN101866877A CN 101866877 A CN101866877 A CN 101866877A CN 200910049284 A CN200910049284 A CN 200910049284A CN 200910049284 A CN200910049284 A CN 200910049284A CN 101866877 A CN101866877 A CN 101866877A
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Abstract
The invention discloses a through hole forming method, which comprises the following steps: providing a silicon substrate; forming a medium layer and an anti-reflection layer on the silicon substrate in sequence; etching the anti-reflection layer and the medium layer in sequence, and forming through holes in the anti-reflection layer and the medium layer; and sputtering and cleaning the through holes. In the through hole forming method, a sputtering and cleaning step is added after a main through hole etching step so as to remove redundant polymers generated in the etching process and byproducts generated by etching light resistors to ensure that the side walls of the through holes are smooth and the edges thereof are clear, and thereby, the resistance distribution of the through holes is even.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of through hole formation method.
Background technology
Along with the development of semiconductor fabrication process technology, the precision of semiconductor integrated circuit has reached the deep-submicron size, makes the integrated level of semiconductor device and the complexity of manufacturing process also constantly increase.Wherein through hole is as the passage that is connected between multiple layer metal layer interconnection and semiconductor device active area and the external circuitry, because its important function in semiconductor device structure, therefore the required precision to the via etch process technology is also improving constantly.
In the prior art; in forming the technology of through hole, when particularly forming the small-bore through hole, can utilize the polymer that produces in the etching through hole process to realize protection to through-hole side wall; with the through hole that formation has smaller aperture due, satisfy the precision requirement of semiconductor device.
See also Fig. 2, it is depicted as the method that the prior art through hole forms, and may further comprise the steps:
S210: silicon substrate is provided;
S220: metallization medium layer on above-mentioned silicon substrate;
S230: on above-mentioned dielectric layer, form anti-reflecting layer.Be used for forming through-hole pattern thereon.
S240: utilize photoresistance on described anti-reflecting layer surface, to define through-hole pattern.Wherein because receive the restriction of the exposure limit, the aperture of the through hole that form this moment may in order to form the through hole in scheduled target aperture, require to produce more polymer when subsequent etching greater than the aperture of setting, and protection is on the sidewall of through hole.
S250: the anti-reflecting layer that etching is not covered by photoresistance.Make and form through-hole pattern on the anti-reflecting layer, for next step etching dielectric layer provides masking layer.
S260: the etching dielectric layer forms through hole.In order to produce more polymer, the etching gas of the plasma etching that the etching dielectric layer is adopted need have high carbon/fluorine ratio.This polymer that is produced on the sidewall attached to through hole, can reduce the lateral etching of sidewall, thereby reaches the purpose of reduced bore.Yet the polymer that produces in etching process is too much and uneven sidewall and the edge that is distributed in through hole of meeting, causes the through hole blur margin clear, and sidewall is coarse, and then makes the distribution of resistance of through hole inhomogeneous.
S270: remove photoresistance.A undesirable influence is avris or the surface that residue is deposited on etching pattern in the plasma etching, residue is from photoresistance and photoresistance residual accessory substance after etching, many violent chemical reactions are arranged in the plasma etching environment, hydrogen-oxygen group and halide gas in the photoresistance react, to form stable metal halide and oxide, be difficult to remove, remain on the edge of through hole, influence the accurate formation of through-hole pattern, the distribution of resistance of more having aggravated through hole is inhomogeneous.
Yet, see also Fig. 1, it is the vertical view that forms through hole in the prior art, as can be seen because the existence of number of polymers, the sidewall of the through hole that etching forms is comparatively coarse, and when microscopically was observed the through hole that forms, the blur margin of through hole was clear, the distribution of polymer inequality, this just causes the distribution of resistance of through hole inhomogeneous.
In addition, because what form the via etch employing is the plasma etching of dry etching, have avris or surface that etch residue is deposited on etching through hole, residue is from photoresistance and photoresistance residual accessory substance after etching, many violent chemical reactions are arranged in the plasma etching environment, hydrogen-oxygen group and halide gas in the photoresistance react, to form stable metal halide (as AlF
3, WF
5, WF
6) and oxide (as TiO
3, TiO etc.), these accessory substances produce pollution problem, influence the formation of etching through hole, and then influence the quality of etching through hole, destroy the electrical characteristic of through hole.
Therefore, because above-mentioned factor, the through hole that prior art forms is because the distribution of polymer that produces in the etching process is uneven and the pollution of accessory substance, cause through-hole side wall coarse, blur margin is clear, the distribution of resistance inequality, the electrical characteristic instability that further causes semiconductor device, off quality, therefore can not satisfy requirement, and then can influence the quality of related application product device performance.
Summary of the invention
The present invention is intended to solve in the prior art; form in the technology of through hole; owing to produce more polymer protection through-hole side wall in the etching through hole process; the distribution of polymer inequality; and the pollution of the accessory substance that etching produced; cause the through hole blur margin clear, problem such as sidewall is coarse, and the distribution of resistance of through hole is inhomogeneous.
In view of this, a kind of through hole of the present invention formation method may further comprise the steps:
One silicon substrate is provided;
On described silicon substrate, form dielectric layer and anti-reflecting layer successively;
Etching anti-reflecting layer and dielectric layer form through hole in anti-reflecting layer and dielectric layer successively;
The described through hole of sputter clean.
Optionally, described sputter clean step specifically comprises adding a high voltage source, and reaction chamber is vacuumized, and feeds argon gas and oxygen mixed gas, carries out sputter.
Optionally, described high voltage source power is 100 to 500W.
Optionally, the air pressure that vacuumizes of described reaction chamber is at 10 to 50 millitorrs.
Optionally, described argon flow amount is 50 to 500 mark condition milliliter per minutes.
Optionally, described oxygen flow is 5 to 100 mark condition milliliter per minutes.
Optionally, the time of sputter was 8 to 10 seconds.
Optionally, described dielectric layer is a silicon oxide layer.
Optionally, in described etching dielectric layer step, used etching gas is CF
4, CH
2F
2, CHF
3Or C
4F
8
In sum, the method that through hole provided by the invention forms is to increase the sputter clean step behind the main etching through hole, to remove the accessory substance that the unnecessary polymer that produces in the etching process and etching photoresistance produce, the assurance through-hole side wall is smooth, and edge clear makes the distribution of resistance of through hole even.
Description of drawings
Figure 1 shows that the vertical view of through hole in the prior art;
Figure 2 shows that the method that the prior art through hole forms;
Figure 3 shows that the method for the through hole formation that one embodiment of the invention provides.
Embodiment
For purpose of the present invention, feature are become apparent, provide preferred embodiment also in conjunction with the accompanying drawings, the invention will be further described.
See also Fig. 3, the method that the through hole that it is depicted as one embodiment of the invention provides forms.This method may further comprise the steps:
S310: silicon substrate is provided;
S320: on described silicon substrate, form dielectric layer and anti-reflecting layer successively; Form one deck dielectric layer and be used to form through hole on silicon substrate, this dielectric layer that is used to form through hole is a silicon oxide layer in the present embodiment, and its thickness exists
Extremely
Between, for example be
On above-mentioned dielectric layer, form anti-reflecting layer, be used for forming pattern thereon, utilize photoresistance on described anti-reflecting layer surface, to define through-hole pattern.Wherein because receive the restriction of the exposure limit, the aperture of the through hole that form this moment may in order to form the through hole in scheduled target aperture, require to produce more polymer when subsequent etching greater than the aperture of setting, and protection is on the sidewall of through hole.
S330: etching anti-reflecting layer and dielectric layer successively form through hole in anti-reflecting layer and dielectric layer.The anti-reflecting layer that etching is not covered by photoresistance.Make and form through-hole pattern on the anti-reflecting layer, for the etching dielectric layer provides masking layer.The etching dielectric layer forms through hole.In order to produce more polymer, the etching gas of the plasma etching that the etching dielectric layer is adopted need have high carbon/fluorine ratio, and in the present embodiment, this etching gas comprises CF at least
4, CH
2F
2, CHF
3Or C
4F
8In a kind of.This polymer that is produced on the sidewall attached to through hole, can reduce the lateral etching of sidewall, thereby reaches the purpose of reduced bore.Yet the polymer that fecund is given birth in etching process is too much and uneven sidewall and the edge that is distributed in through hole of meeting, causes the through hole blur margin clear, and sidewall is coarse, and then makes the distribution of resistance of through hole inhomogeneous.
S340: the described through hole of sputter clean.This sputter clean is to remove the accessory substance that the unnecessary polymer that produces in the above-mentioned etching process and etching photoresistance are produced, and guarantees that through-hole side wall is smooth, and the edge distribution of resistance is even.
Specifically comprise adding a high voltage source, reaction chamber is vacuumized, feed argon gas and oxygen mixed gas, carry out sputter.In the present embodiment, described high voltage source power is 100 to 500W.The air pressure that described reaction chamber vacuumizes is at 10 to 50 millitorrs.Described argon flow amount is 50 to 500 mark condition milliliter per minutes.Described oxygen flow is 5 to 100 mark condition milliliter per minutes.The time of sputter was 8 to 10 seconds.
Argon gas and oxygen produce high energy ion under the intensifying of high voltage source, the bombardment more than polymer and accessory substance, to reach the cleaning through hole, remove the unnecessary polymer and the purpose of accessory substance, make through-hole side wall smooth, edge clear, distribution of resistance is even, has guaranteed to form the quality of through hole.
Contrast prior art and the present invention; in the prior art; form in the technology of through hole; owing to produce more polymer protection through-hole side wall in the etching through hole process; distribution of polymer inequality, and the pollution of the accessory substance that etching produced cause the through hole blur margin clear; problems such as sidewall is coarse, and the distribution of resistance of through hole is inhomogeneous.
And the through hole formation method that the embodiment of the invention provides, be to form in the process of through hole in prior art, behind etching through hole, increased the sputter clean step, to remove the accessory substance that the unnecessary polymer that produces in the etching process and etching photoresistance produce, the assurance through-hole side wall is smooth, and the edge distribution of resistance is even.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (9)
1. through hole formation method may further comprise the steps:
One silicon substrate is provided;
On described silicon substrate, form dielectric layer and anti-reflecting layer successively;
Etching anti-reflecting layer and dielectric layer form through hole in anti-reflecting layer and dielectric layer successively;
The described through hole of sputter clean.
2. the method that through hole according to claim 1 forms is characterized in that described sputter clean step specifically comprises adding a high voltage source, and reaction chamber is vacuumized, and feeds argon gas and oxygen mixed gas, carries out sputter.
3. the method that through hole according to claim 2 forms is characterized in that, described high voltage source power is 100 to 500W.
4. the method that through hole according to claim 2 forms is characterized in that the air pressure that described reaction chamber vacuumizes is at 10 to 50 millitorrs.
5. the method that through hole according to claim 2 forms is characterized in that, described argon flow amount is 50 to 500 mark condition milliliter per minutes.
6. the method that through hole according to claim 2 forms is characterized in that, described oxygen flow is 5 to 100 mark condition milliliter per minutes.
7. the method that through hole according to claim 2 forms is characterized in that the time of sputter was 8 to 10 seconds.
8. the method that through hole according to claim 1 forms is characterized in that wherein said dielectric layer is a silicon oxide layer.
9. the method that through hole according to claim 1 forms is characterized in that in described etching dielectric layer step, used etching gas is CF
4, CH
2F
2, CHF
3Or C
4F
8
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910049284A CN101866877A (en) | 2009-04-14 | 2009-04-14 | Through hole forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910049284A CN101866877A (en) | 2009-04-14 | 2009-04-14 | Through hole forming method |
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| Publication Number | Publication Date |
|---|---|
| CN101866877A true CN101866877A (en) | 2010-10-20 |
Family
ID=42958525
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102651370A (en) * | 2012-01-04 | 2012-08-29 | 京东方科技集团股份有限公司 | TFT (Thin Film Transistor) array substrate, manufacturing method and display device |
| CN105470104A (en) * | 2014-09-09 | 2016-04-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
-
2009
- 2009-04-14 CN CN200910049284A patent/CN101866877A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102651370A (en) * | 2012-01-04 | 2012-08-29 | 京东方科技集团股份有限公司 | TFT (Thin Film Transistor) array substrate, manufacturing method and display device |
| WO2013102370A1 (en) * | 2012-01-04 | 2013-07-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor and display device |
| CN102651370B (en) * | 2012-01-04 | 2014-12-10 | 京东方科技集团股份有限公司 | TFT (Thin Film Transistor) array substrate, manufacturing method and display device |
| US9123775B2 (en) | 2012-01-04 | 2015-09-01 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same and display device |
| CN105470104A (en) * | 2014-09-09 | 2016-04-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
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Open date: 20101020 |