CN101860365B - Reference clock source switching method and device - Google Patents
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Abstract
The invention discloses reference clock source switching method and device, wherein the reference clock source switching method comprises the following steps of: detecting a first phase difference between a local oscillator output clock of a system and a first reference clock source currently used by the system; acquiring the maximal phase difference between pairwise reference clock sources of a plurality of reference clock sources of the currently detected system; controlling the local oscillator output clock through the sum of the first phase difference and N/M times of the maximal phase difference; detecting a second phase difference between the local oscillator output clock and a second reference clock source when the system is switched to the second reference clock source; and controlling the local oscillator output clock through the difference of the second phase difference and (M-N)/M times of the maximal phase difference, wherein the plurality of reference clock sources include the first reference clock source and the second reference clock source, M and N are natural numbers, and M is larger than N. The invention can be used for effectively preventing anomalous events of the system clocks from happening after switching.
Description
Technical field
Invention relates to field of wireless communication, relates in particular in the base station system a kind of reference clock source switching method and device.
Background technology
In existing wireless telecommunication system, the clock source that need there be an outside base station uses it to the local clock frequency is proofreaied and correct as a reference.In system, be used for the clock source of correcting local clock and be called reference clock source.
Adopt global positioning system (Global PositionSystem abbreviates GPS as) to come the correction reference clock as reference clock source at present in the wireless synchronization net mostly; PP1S (pulse per second (PPS)) clock of reference clock element keeps track GPS receiver output, utilize digital phase-locked loop that local oscillator output clock is followed the tracks of control, it is synchronous to export the PP1S clock up to oscillator output clock and GPS receiver, thereby makes in the system other nodal clock and primary resource clock synchronous.
Under some application conditions, need to use simultaneously a plurality of reference clock sources in the wireless synchronization net, for example, and the Big Dipper, line clock source, 1588 clock sources etc., system can formulate rational handover mechanism according to the operating state of each reference clock source.At special time period, the at first preferential reference clock source of selecting to use wherein is as the reference of local clock, controls to reach system synchronization; If the reference clock source of current use occurs unusual, then system can switch to the another one reference clock source and follow the tracks of according to fixed handover mechanism, so that system continues normal the tracking, is stabilized on the new reference clock source.
In correlation technique, system is when with some reference clock sources serving as reference control local clock, phase difference according to this reference clock source and local clock is adjusted, therefore, in above-mentioned handoff procedure, when the clock skew of two reference clock source outputs exceeds certain limit, system will cause system's output clock generation one or many unusual after switching to another reference clock source, even the interdependent node hardware cell resets in causing netting, and causes communication system soft handover failure in the short time.
Summary of the invention
Main purpose of the present invention is to provide a kind of reference clock source switching method and device, to solve at least in the correlation technique owing to reference clock source switches the problem that causes the failure of communication system soft handover.
According to an aspect of the present invention, provide a kind of reference clock source switching method method, having comprised: first phase difference between first reference clock source of detection system local oscillator output clock and the current use of system; Obtain current detection to a plurality of reference clock sources of system in the maximal phase potential difference between reference clock source in twos; With first phase difference and N/M times of maximal phase potential difference sum local oscillator output clock is controlled; System switches to second reference clock source, detects second phase difference between local oscillator output clock and second reference clock source; With second phase difference with (M-N)/difference of M times maximal phase potential difference controls local oscillator output clock; Wherein, above-mentioned a plurality of reference clock sources comprise first reference clock source and second reference clock source, and M and N are natural number, and M＞N.
According to a further aspect in the invention, provide a kind of reference clock source switching device shifter, having comprised: state detection unit is used for the state of a plurality of each reference clock sources of reference clock source of detection in real time; Select and switch control unit, be used for according to default reference clock source selection strategy, normal first reference clock source of selection mode is as the reference clock source input of digital phase-locked loop unit from above-mentioned a plurality of reference clock sources, and occur when unusual at first reference clock source, normal second reference clock source of selection mode is as the reference clock source input of digital phase-locked loop unit from above-mentioned a plurality of reference clock sources; Phase detection unit is used for detecting above-mentioned a plurality of reference clock sources phase difference of reference clock source in twos in real time, and detected maximal phase potential difference is input to the digital phase-locked loop unit; The digital phase-locked loop unit, be used for when the reference clock source of input is first reference clock source, detect first phase difference between local oscillator output clock and first reference clock source, with first phase difference and N/M times of maximal phase potential difference sum local oscillator output clock is controlled, when reference clock source second reference clock source of input, detect second phase difference between local oscillator output clock and second reference clock source, with second phase difference with (M-N)/difference of M times maximal phase potential difference exports clock to local oscillator and controls; Wherein, M and N are natural number, and M＞N.
By the present invention, improved the phase difference factor of control local oscillator output clock, cause netting interior system clock generation in the reference clock source handoff procedure that exists in the prior art unusually thereby overcome, cause the problem of communication system soft handover failure in the short time.Thereby can effectively avoid switching the generation of back system clock anomalous event, improve the reliability of reference clock unit output clock, effectively guarantee the system communication quality.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used for explaining the present invention, do not constitute improper restriction of the present invention.In the accompanying drawings:
Fig. 1 is the structural representation according to the reference clock source switching device shifter of the embodiment of the invention one;
Fig. 2 is the structural representation according to the preferred reference clock source switching device shifter of the embodiment of the invention one;
Fig. 3 is the flow chart according to the reference clock source switching method of the embodiment of the invention two;
Fig. 4 is the phase diagram according to each clock of system of the embodiment of the invention three;
Fig. 5 is the flow chart according to the reference clock source switching method of the embodiment of the invention three.
Embodiment
Hereinafter will describe the present invention with reference to the accompanying drawings and in conjunction with the embodiments in detail.Need to prove that under the situation of not conflicting, embodiment and the feature among the embodiment among the application can make up mutually.
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated.
Embodiment one
Fig. 1 is the structural representation according to the reference clock source switching device shifter of the embodiment of the invention one, and this device can be arranged in the synchronization processing apparatus that digital communication equipment is used for the synchronised clock output signal.
As shown in Figure 1, be used for the synchronization processing apparatus of synchronised clock output signal in the digital communication equipment, receive a plurality of reference clock source inputs, be i.e. the S of reference source 101 outputs shown in Figure 1
IN1, reference source 102 output S
IN2, up to the reference source S of reference source 107 outputs
INn(n is greater than 2).This device comprises: state detection unit 103 is used for the state of a plurality of each reference clock sources of reference clock source of detection in real time, and the result is input to selection and switch control unit 104; Selection and switch control unit 104 are connected with state detection unit 103, be used for the testing result according to state detection unit 103 inputs, select mechanism to select the normal reference clock source of one of them state as the reference clock source S of digital phase-locked loop unit 106 according to default reference source
INInput; Phase detection unit 105 is used for detecting a plurality of reference clock sources phase difference of reference clock source in twos in real time, and detected maximal phase potential difference is inputed to digital phase-locked loop unit 106; Digital phase-locked loop unit 106 is connected with phase detection unit 105 with selection and switch control unit 104 respectively, for detection of the reference clock source S of local oscillator output time and selection and switch control unit 104 inputs
INBetween phase difference, utilize the maximal phase potential difference sum of this phase difference and N/M times phase detection unit 105 input that the output clock of local oscillator is controlled, i.e. the output clock of corrective system local oscillator, final stable output and reference source clock S
INSynchronous clock S
OutWherein, M and N are natural number, M＞N.
And, when the reference clock source that the testing result indication is selected and switch control unit 104 is selected of state detection unit 103 input occurs when unusual, selection and switch control unit 104 also are used for the testing result according to state detection unit 103, reselect the normal reference clock of state as the reference clock source S of digital phase-locked loop unit 106 from above-mentioned a plurality of reference clock sources
INInput; And digital phase-locked loop unit 106 is also for detection of the phase difference between local oscillator output clock and this reference clock source, with this phase difference with (M-N)/ maximal phase potential difference sum that M times phase detection unit 105 is imported controls the output clock of local oscillator.
Because in the correlation technique, system is when with some reference clock sources serving as reference control local clock, phase difference according to this reference clock source and local clock is adjusted, in handoff procedure, when the clock skew of two reference clock source outputs exceeds certain limit, system will cause system's output clock generation one or many unusual after switching to another reference clock source, even the interdependent node hardware cell resets in causing netting, and causes communication system soft handover failure in the short time.And in the above-mentioned reference clock source switching device shifter that the embodiment of the invention provides, normally control the stage in system, digital phase-locked loop unit 106 is according to reference clock source and the output of the maximal phase potential difference correcting local oscillator between a plurality of reference clock source clock of input, when switching in the system reference source, digital phase-locked loop unit 106 detects the phase difference between local clock and switching back reference source clock, and obtain new phase difference according to the maximal phase potential difference between this phase difference and a plurality of reference clock source, with new phase difference correction local oscillator output clock, thereby can realize taking over seamlessly of reference clock source, avoid switching the generation of back system clock anomalous event, improve the reliability of reference clock unit output clock, effectively guaranteed the system communication quality.
Preferably, as shown in Figure 2, in embodiments of the present invention, the quantity of the reference clock source of input is 2, and, M=2, N=1.In this case, because
With
Value identical, therefore, 106 inputs can not be detected maximal phase potential difference to phase detection unit 105 to the digital phase-locked loop unit, and with detected maximal phase potential difference 1/2 as differing enter factor input, digital phase-locked loop unit 106 no longer needs to calculate N/M times of maximal phase potential difference or (M-N)/M times maximal phase potential difference before and after reference clock source switches like this, and directly according to the enter factor that differs of the reference clock source of selecting and switch selected cell 104 to import and phase detection unit 105 inputs the output clock of local oscillator is controlled, namely before reference clock source switches, differing the enter factor sum with the phase difference between the reference clock source of local oscillator output clock and input and this controls the output clock of local oscillator, when reference clock source switches, with the phase difference between the reference clock source of local oscillator output clock and input and this difference that differs enter factor local oscillator output clock is controlled.Thereby can reduce amount of calculation.As shown in Figure 2, the reference clock source switching device shifter comprises reference source 101, reference source 102, state detection unit 103, selection and switch control unit 104, phase detection unit 105 and digital phase-locked loop unit 106.This device receives two external reference source clock inputs, finally exports a stable clock S synchronous with the reference input
OutWherein, state detection unit 103 detects the state of each reference clock source in real time, and the result is sent to selects and switch control unit 104, select and switch control unit 104 selects mechanism to select the normal reference source of one of them state as the reference clock source input of digital phase-locked loop unit 106 according to default source; Phase detection unit 105 detects the phase difference P1 between two reference clock sources in real time, and P1/2 gives digital phase-locked loop unit 106 with this phase difference; Digital phase-locked loop unit 106 will utilize the reference clock source S of input
INWith P1/2 corrective system local clock source, final stable output and reference source clock S
INSynchronous clock S
Out
By reference clock source switching device shifter as shown in Figure 2, in the time of can having 2 reference clock sources in system, be implemented in taking over seamlessly between these two reference clock sources.
In actual applications, reference source 101, reference source 102 ..., reference source 107 is generally the PP1S clock signal of receiver output, owing to there is various application scenario, receiver includes but not limited to: GPS receiver, GLONASS receiver or Big Dipper receiver, can receive the signal of gps satellite system, GLONASS satellite system or big-dipper satellite system respectively, the PP1S clock signal of output long-term stability better performances.In specific application scenario, system requirements uses two kinds of reference sources to backup each other simultaneously, and namely there are two kinds of different reference clock source inputs simultaneously in system.Certain application cases is more arranged, and system also must satisfy circuit class reference source or the 1588 system reference sources supported, therefore can have the situation of two above reference sources, namely has reference source n (n is greater than 2).
With M=2, N=1 is example below, further introduces the operation principle according to each unit in the reference clock source switching device shifter of the embodiment of the invention.
State detection unit 103 detect in real time reference sources 101, reference source 102 ..., the state of reference source 107, and testing result exported to selects and switch control unit 104.
Selection and switch control unit 104 receive the input of reference clock sources, if the equal operate as normal of different reference clock sources, then the predefined preferred reference source of selective system is exported to back stages of digital phase locked-loop unit 106; If different reference clock source operating states has difference, then select the best reference clock source of operating state, export to back stages of digital phase locked-loop unit 106; If the reference source of current use occurs unusual, and other reference source state is normal, then according to the normal reference source priority of state, initiatively switches to the normal reference source of state, and export to the digital phase-locked loop unit 106 of back level.
Phase detection unit 105 detect in real time reference sources 101, reference source 102 ..., in the reference source 107 in twos between phase difference, draw maximal phase potential difference P1, if the current running status of each reference source is normal, P1 gives digital phase-locked loop unit 106 with this phase difference.
Digital phase-locked loop unit 106 receives the S that selection and switch control unit 104 are exported
INThe phase signal P1 of reference clock source signal and phase detection unit 105 outputs; Use S
INSignal detects clock and the S of local oscillator output as clock reference
INPhase difference between the clock adds P1/2 on this phase difference basis, obtains new phase difference, with new phase difference the clock of local oscillator output is followed the tracks of control then, final output and reference source clock signal S
INClock signal synchronous.If switch in system reference clock source, i.e. the S of selection and switch control unit 104 outputs
INVariation has taken place in the reference clock source signal, digital phase-locked loop unit 106 uses new reference clock source, and detect phase difference between the clock of new reference clock source and local oscillator output, deduct P1/2 on this phase difference basis, obtain new phase difference, with this new phase difference the clock of local oscillator output is followed the tracks of control then, final output and reference source clock signal S
INClock signal synchronous.Thereby effectively realize taking over seamlessly of multiple reference clock source.
Embodiment two
Fig. 3 is the flow chart according to the reference clock source switching method of the embodiment of the invention two, and this method can realize by Fig. 1 or device shown in Figure 2.This method mainly may further comprise the steps (step S302-step S310):
Step S302, first phase difference between first reference clock source of digital phase-locked loop unit 106 detection system local oscillators output clock and the current use of system;
For example, a plurality of reference clock source states of state detection unit 103 real-time detecting systems, and the result that will detect exports to selection and switch control unit 104, selection and switch control unit 104 therefrom select first reference clock source of normal condition as the reference clock source of current use according to each reference clock source state, and this reference clock source is input to digital phase-locked loop unit 106.For example, if the equal operate as normal of each reference clock source is then selected and the predefined preferred reference source of switch control unit 104 selective systems, export to back stages of digital phase locked-loop unit 106; If each reference clock source operating state has difference, then select and the best reference clock source of switch control unit 104 selection operating states, export to back stages of digital phase locked-loop unit 106;
Step S304, phase detection unit 105 detect in a plurality of reference clock sources the phase difference of reference clock source in twos in real time, and wherein maximal phase potential difference P1 is exported to digital phase-locked loop unit 106;
If the quantity in the available reference clock source of system is 2, i.e. the quantity of the PP1S clock signal of receiver output is 2, and then maximal phase potential difference P1 is the phase difference between these two reference clock sources.
Step S306, digital phase-locked loop unit 106 is controlled local oscillator output clock with above-mentioned first phase difference and N/M times of P1 sum;
For example, M=2, N=1.
Step S308 selects and switch control unit 104 switches to second reference clock source with reference clock source, and digital phase-locked loop unit 106 detects second phase difference between local oscillator output clock and second reference clock source;
For example, state detection unit 103 detects above-mentioned first reference clock source and occurs unusual, selection and switch control unit 104 are according to the testing result of state detection unit 103 inputs, priority according to normal each reference clock source of state in a plurality of reference clock sources, normal second reference clock source of selection mode is input to digital phase-locked loop unit 106 with second reference clock source as current reference clock source from a plurality of reference clock sources.
Step S310, digital phase-locked loop unit 106 with above-mentioned second phase difference with (M-N)/difference of M times P1 controls local oscillator output clock.
Because in the correlation technique, system is when with some reference clock sources serving as reference control local clock, phase difference according to this reference clock source and local clock is adjusted, in handoff procedure, when the clock skew of two reference clock source outputs exceeds certain limit, system will cause system's output clock generation one or many unusual after switching to another reference clock source, even the interdependent node hardware cell resets in causing netting, and causes communication system soft handover failure in the short time.And in the above-mentioned reference clock source switching method that the embodiment of the invention provides, normally control the stage in system, digital phase-locked loop unit 106 is according to reference clock source and the output of the maximal phase potential difference correcting local oscillator between a plurality of reference clock source clock of input, when switching in the system reference source, digital phase-locked loop unit 106 detects the phase difference between local clock and switching back reference source clock, and obtain new phase difference according to the maximal phase potential difference between this phase difference and a plurality of reference clock source, with new phase difference correction local oscillator output clock, thereby can realize taking over seamlessly of reference clock source, avoid switching the generation of back system clock anomalous event, improve the reliability of reference clock unit output clock, effectively guaranteed the system communication quality.
Embodiment three
Present embodiment is that example describes with each clock shown in Figure 4, and in the present embodiment, the reference clock source of system is reference source 1 and reference source 2, and, M=2, N=1.
Fig. 5 is the flow chart that reference clock source in the present embodiment switches, and mainly may further comprise the steps:
Step S501, the startup stage of system, reference source 1, reference source 2 ..., reference source n (n=2 in the present embodiment) all normal initialization and starting finish;
Step S502, in the system warm-up stage, system detects the state of each reference clock source in real time, if the reference source state is all normal, then execution in step S503 and step S506;
Step S503, the phase difference of two reference clock sources of detection;
Step S504 preserves the value of detected phase difference divided by 2, namely preserve phase value P1/2;
Step S505, with P1/2 as differing enter factor input digit phase locked-loop unit 106;
Step S506 selects one of them reference clock source as the input of digital phase-locked loop unit 106, in the present embodiment, supposes that the used reference clock source of current reality is reference source 2;
Step S507, digital phase-locked loop unit 106 detects the phase difference P0 between local clock and reference source 2 output clocks;
Step S508, digital phase-locked loop unit 106 adds that 1/2 phase difference between two reference sources is P1/2 differing the P0 basis, draws new phase difference P0+P1/2, follows the tracks of control with the new local clock of phase difference P0+P1/2.
Step S509 judges whether reference source 2 occurs unusually, if, then execution in step S510 and step S511, otherwise, execution in step S508 continued;
Step S510, reference source 2 occurs unusual, and the system reference source switches to reference source 1;
Step S511, select and switch control unit 104 to the digital phase-locked loop unit 106 input reference sources 2, digital phase-locked loop unit 106 detects local clocks and reference source 1 and exports and differ P0 ' between clock;
Step S512, digital phase-locked loop unit 106 is P1/2 differing 1/2 phase difference that P0 ' basis deducts between two reference sources, draws new phase difference P0 '-P1/2, follows the tracks of control with the new local clock of phase difference P0 '-P1/2.
As seen in Figure 4, switch front and back in system, the digital phase-locked loop unit 106 actual reference clock sources that use are the virtual reference source shown in the figure, can effectively realize taking over seamlessly of multiple reference clock source by the method.
From above description, as can be seen, in embodiments of the present invention, normally control the stage in system, with the phase difference between local clock and the current reference source clock that is using, differ the basis at this and add in detected a plurality of reference source the N/M between reference source times of maximal phase potential difference in twos, draw new phase difference, with new phase difference as control local oscillator output clock.When switching in the system reference source, system detects local clock and switches differing between the reference source clock of back, differ the basis at this and deduct (M-N)/M times of maximal phase potential difference, draw new phase difference, with new phase difference control local oscillator output clock, thereby realize taking over seamlessly of a plurality of reference clock sources, thereby can effectively avoid switching the generation of back system clock anomalous event, improve the reliability of reference clock unit output clock, effectively guaranteed the system communication quality.
Obviously, those skilled in the art should be understood that, above-mentioned each module of the present invention or each step can realize with the general calculation device, they can concentrate on the single calculation element, perhaps be distributed on the network that a plurality of calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in the storage device and be carried out by calculation element, and in some cases, can carry out step shown or that describe with the order that is different from herein, perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. a reference clock source switching method is characterized in that, comprising:
First phase difference between first reference clock source of detection system local oscillator output clock and the current use of described system;
Obtain current detection to a plurality of reference clock sources of described system in the maximal phase potential difference between reference clock source in twos;
With described first phase difference and N/M doubly described maximal phase potential difference sum described local oscillator output clock is controlled;
Described system switches to second reference clock source, detects second phase difference between described local oscillator output clock and described second reference clock source;
With described second phase difference with (M-N)/M doubly the difference of described maximal phase potential difference described local oscillator output clock is controlled;
Wherein, described a plurality of reference clock sources comprise described first reference clock source and described second reference clock source, and M and N are natural number, and M＞N.
2. method according to claim 1, it is characterized in that, obtain current detection to a plurality of reference clock sources of described system in twos the maximal phase potential difference between reference clock source comprise: detect in described a plurality of reference clock source the phase difference between reference clock source in twos in real time, select maximum as described maximal phase potential difference.
3. method according to claim 1 and 2 is characterized in that, the quantity of described a plurality of reference clock sources is 2, and described maximal phase potential difference is the phase difference between these two reference clock sources.
4. method according to claim 1 and 2 is characterized in that, the equal operate as normal of described a plurality of reference clock sources, and described first reference clock source is the predefined preferred reference clock source of described system.
5. method according to claim 1 and 2 is characterized in that, the operating state difference of described a plurality of reference clock sources, and described first reference clock source is the best reference clock source of operating state in described a plurality of reference clock source.
6. method according to claim 1 and 2 is characterized in that, described system switches to second reference clock source and comprises:
Described first reference clock source occurs unusual;
According to the priority of normal each reference clock source of state in described a plurality of reference clock sources, select and switch to described second reference clock source.
7. method according to claim 1 and 2 is characterized in that, described M=2, N=1.
8. a reference clock source switching device shifter is characterized in that, comprising:
State detection unit is used for the state of a plurality of each reference clock sources of reference clock source of detection in real time;
Select and switch control unit, be used for according to default reference clock source selection strategy, normal first reference clock source of selection mode is as the reference clock source input of digital phase-locked loop unit from described a plurality of reference clock sources, and occur when unusual at described first reference clock source, normal second reference clock source of selection mode is as the reference clock source input of described digital phase-locked loop unit from described a plurality of reference clock sources;
Phase detection unit is used for detecting described a plurality of reference clock sources phase difference of reference clock source in twos in real time, and detected maximal phase potential difference is input to described digital phase-locked loop unit;
Described digital phase-locked loop unit, when being used for reference clock source in input and being described first reference clock source, detect first phase difference between local oscillator output clock and described first reference clock source, with described first phase difference and N/M doubly described maximal phase potential difference sum described local oscillator output clock is controlled, when described second reference clock source of reference clock source of input, detect second phase difference between local oscillator output clock and described second reference clock source, with described second phase difference with (M-N)/M doubly the difference of described maximal phase potential difference described local oscillator exported clock control;
Wherein, M and N are natural number, and M＞N.
9. device according to claim 8 is characterized in that, the quantity of described a plurality of reference clock sources is 2, and described maximal phase potential difference is the phase difference between these two reference clock sources.
10. according to Claim 8 or 9 described devices, it is characterized in that described M=2, N=1.
11. device according to claim 10, it is characterized in that, described phase detection unit is input to described digital phase-locked loop unit with 1/2 described maximal phase potential difference as differing enter factor, when described digital phase-locked loop unit is described first reference clock source at the reference clock source of input, with described first phase difference and the described enter factor sum that differs described local oscillator output clock is controlled,, with the described difference that differs enter factor described local oscillator is exported clock with described second phase difference and control when being described second reference clock source at the reference clock source of input.
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| CN110690894B (en) * | 2019-09-20 | 2023-05-12 | 上海励驰半导体有限公司 | Clock failure safety protection method and circuit |
| CN110781121B (en) * | 2019-11-07 | 2022-01-04 | 江苏芯盛智能科技有限公司 | Reference clock source configuration method and end equipment |
| CN112558018B (en) * | 2020-12-08 | 2021-09-03 | 深圳市虹远通信有限责任公司 | Method, processor and system for aligning clock and pulse per second between multiple systems with high precision |
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| US6392462B2 (en) * | 2000-04-04 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Multiphase clock generator and selector circuit |
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