CN101860076A - Multifunctional electric energy quality monitoring and analyzing system - Google Patents

Multifunctional electric energy quality monitoring and analyzing system Download PDF

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Publication number
CN101860076A
CN101860076A CN 201010151916 CN201010151916A CN101860076A CN 101860076 A CN101860076 A CN 101860076A CN 201010151916 CN201010151916 CN 201010151916 CN 201010151916 A CN201010151916 A CN 201010151916A CN 101860076 A CN101860076 A CN 101860076A
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China
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input
pin
circuit
connects
output terminal
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CN 201010151916
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CN101860076B (en
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鲍喜荣
王明全
佘黎煌
张石
王顼
钱若函
李在林
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东北大学
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Abstract

The invention relates to a multifunctional electric energy quality monitoring and analyzing system which belongs to the technical field of electric energy quality monitoring. The multifunctional electric energy quality monitoring and analyzing system comprises a plurality of multifunctional electric energy quality monitoring analyzers, a timing subsystem and a server computer, wherein the multifunctional electric energy quality monitoring analyzers are respectively communicated with a global positioning system timing module and the server computer by Ethernet or a CAN (Controller Area Network) bus interface or an RS232 communication interface or an RS485 interface; and each multifunctional electric energy quality monitoring analyzer comprises a signal connecting module 1, a signal analyzing and dispatching module 2, a power supply module 3, a server 4 and a global positioning system 5. The invention has simple hardware circuit, easy expansion and convenient installation and debugging, not only can be used as a node of the whole electric energy quality analyzing and fault recording network but also can be used as a single portable instrument.

Description

Multifunctional electric energy quality monitoring and analyzing system

Technical field

The invention belongs to the electric energy quality monitoring technical field, particularly a kind of multifunctional electric energy quality monitoring and analyzing system.

Background technology

Electric power quality monitoring analysis instrument is that electric power system is broken down and can self registering a kind of device when vibrating, it can write down system power, voltage and the derived quantity thereof that causes because of big disturbance such as short trouble, system oscillation, frequency collapse, voltage collapse, as the overall process variation phenomenon of meritorious, idle and system frequency;

At present, electric power quality monitoring analysis instrument uses the structure of uniprocessor for core more, or the structure of dual processor: adopt uniprocessor generally to be to use digital signal processor (DSP) or arm processor; The benefit of this structure is that system hardware structure is simple, be convenient to debugging and upgrading, but be to use DSP or ARM, but can exist the extension storage space little, communication interface is few, the data dispatch ability, man-machine interaction father complexity, arithmetic speed is slower, is difficult to use the algorithm of accurate strictness to carry out a large amount of real time data processings, does not satisfy the requirement of electric power monitoring and failure wave-recording; Adopt the structure of biplate double-core, normally a dsp processor and an arm processor, DSP is responsible for operation of data and processing, and arm processor is responsible for the scheduling and the storage of data, man-machine interaction etc., two processors connect with the dual port random access memories; Though this structure can well be finished the various functions of power quality analyzer, this constructional hardware circuit complexity costs an arm and a leg, and equipment is installed and debug very difficult, and the upgrading in later stage and maintenance are very difficult.

On the connected mode, domestic product or can only be as a node of whole power quality analysis and failure wave-recording network, when whole electric energy network is carried out the record of real-time analysis and fault, must a plurality of power quality analyzers and server use jointly, can not singlely use; Can only be as an independent portable instrument, power line to single-phase or three-phase carries out the real-time analysis and the record of fault, and real-time data transmission capabilities is not arranged specifically, promptly can not use jointly, whole electric energy network is carried out the real-time analysis and the record of fault with a plurality of power quality analyzers and server.

Summary of the invention

In order to remedy the deficiency of above electric capacitor protection structure, of the present inventionly provide a kind of multifunctional electric energy quality monitoring and analyzing system that adopts the monolithic dual core processor, with reach hardware circuit simply, easily expand, be convenient to the purpose of installing and debugging.

Technical scheme of the present invention be achieved in that multifunctional electric energy quality monitoring and analyzing system of the present invention comprise a plurality of multifunctional electric energy quality monitoring analyzers, to the time subsystem and server computer; A plurality of multifunctional electric energy quality monitoring analyzers respectively by Ethernet or CAN bus interface or RS232 communication interface or RS485 interface and global positioning system to the time module and server computer carry out communication;

Described multifunctional electric energy quality monitoring analyzer is made up of signal acquisition module 1, signal analysis scheduler module 2 and power module 3, server 4 and global positioning system 5; Described tested three-phase alternating voltage, three-phase alternating current are input to the voltage signal input and the current signal input of signal acquisition module 1 respectively, and switching value is input to the digital signal input end of signal acquisition module 1; The input/output terminal of the parallel bus interface circuit of signal acquisition module 1 connects the input/output terminal of the parallel bus interface circuit of signal analysis scheduler module 2; Second input/output terminal of second input/output terminal of second input/output terminal of the ethernet interface circuit of the band insulation blocking of signal analysis scheduler module 2, RS232 communication interface circuit and RS485 communication interface circuit is first input/output terminal, second input/output terminal and the 3rd input/output terminal of Connection Service device 4 respectively, and second input/output terminal of the CAN communication interface circuit of signal analysis scheduler module 2 connects the input/output terminal of global positioning system 5; First circuit output end of pressure-stabilizing of power module 3 connects the power input of signal acquisition module 1, and second circuit output end of pressure-stabilizing of power module 3 connects the power input of signal acquisition module 1 and the power supply signal input of signal analysis scheduler module 2;

Described signal acquisition module 1 includes: voltage protection circuit 1-1, voltage modulate circuit 1-2, the first analog to digital converter 1-3, current protecting circuit 1-4, current regulating circuit 1-5, the second analog to digital converter 1-6, pull-up resistor circuit 1-7, isolation protective circuit 1-8, buffer 1-9 and CPLD 1-10; Three-phase alternating voltage connects the voltage input end of voltage protection circuit 1-1, the output of voltage protection circuit 1-1 connects the input of voltage modulate circuit 1-2, the output of voltage modulate circuit 1-2 connects the input end of analog signal of the first analog to digital converter 1-3, and the digital signal input/output terminal of the first analog to digital converter 1-3 connects the first digital signal input/output terminal of the analog to digital converter controller of CPLD 1-10; Three-phase alternating current connects the alternating current input of current protecting circuit 1-4, the output of current protecting circuit 1-4 connects the input that exchanges modulate circuit 1-5, the output of current regulating circuit 1-5 connects the input end of analog signal of the second analog to digital converter 1-6, and the digital signal input/output terminal of the second analog to digital converter 1-6 connects the second digital signal input/output terminal of the analog to digital converter controller of CPLD 1-10; The switching value signal connects the end of pull-up resistor 1-7, the other end of pull-up resistor circuit 1-7 connects the input of isolation protective circuit, the output of isolation protective circuit 1-8 connects the input of buffer, and the input/output terminal of buffer 1-9 connects the input/output terminal of the switch acquisition controller of complex programmable controller 1-10;

Described signal analysis scheduler module 2 includes: dual core processor 2-1, clock circuit 2-2, real time clock circuit 2-3, USB memory circuit 2-4, ethernet physical layer circuit 2-5, the ethernet interface circuit 2-6 of band insulation blocking, RS232 conversion buffer circuit 2-7, RS232 communication interface circuit 2-8, RS485 conversion buffer circuit 2-9, RS485 communication interface circuit 2-10, touch-screen 2-11, liquid crystal display screen 2-12, the CAN physical layer circuit 2-13 of band insulation blocking, CAN interface circuit 2-14, NANDFLASH built-in storage 2-15, Synchronous Dynamic Random Access Memory 2-16; The input/output terminal of the parallel bus interface of described dual core processor 2-1, the input of phase-locked loop circuit, the input of real time clock circuit, the input/output terminal of USB controller, the data/address bus address bus input/output terminal of ethernet controller, the input/output terminal of the first universal asynchronous reception/dispensing device UART1 interface circuit, the input/output terminal of the second universal asynchronous reception/dispensing device UART2 interface circuit, the input of touch screen controller, the data address bus output of liquid crystal display screen controller, the input/output terminal of CAN controller, the input/output terminal of the data address bus of first memory controller A, the data address bus input/output terminal of second memory controller B connects the input/output terminal of the parallel bus interface of signal acquisition module 1, the output of clock circuit 2-2 successively, the output of real time clock circuit 2-3, the input/output terminal of USB memory circuit 2-4, the input/output terminal of the data address bus of ethernet physical layer circuit 2-5, first input/output terminal of RS232 conversion buffer circuit 2-7, first input/output terminal of RS485 conversion buffer circuit 2-9, the output of touch-screen 2-11, the data address bus input of liquid crystal display screen 2-12, first input/output terminal of the CAN physical layer circuit 2-13 of band insulation blocking, the input/output terminal of the data address bus of NANDFLASH built-in storage 2-15 and the input/output terminal of Synchronous Dynamic Random Access Memory 2-16; First input/output terminal of the ethernet interface circuit 2-6 of the input/output terminal connecting band insulation blocking of ethernet physical layer circuit 2-5; Second input/output terminal of RS232 conversion buffer circuit 2-7 connects first input/output terminal of RS232 communication interface circuit 2-8; Second input/output terminal of RS485 conversion buffer circuit 2-9 connects first input/output terminal of RS485 communication interface circuit 2-10; Second input/output terminal of the CAN physical layer circuit 2-13 of band insulation blocking connects first input/output terminal of CAN interface circuit 2-14;

Described power module 3 includes: DC-DC switch voltage-stabilizing circuit 3-1, power transfer module 3-2 and AC-DC transformer 3-3, line voltage connects the voltage input end of AD-DC transformer 3-3, the power output end of AD-DC transformer 3-3 connects the input of power transfer module 3-2, and the output of power transfer module 3-2 connects the input of DC-DC switch voltage-stabilizing circuit 3-1; The voltage modulate circuit power output end of power module 3, the first analog to digital converter power output end of power module 3, the second analog to digital converter power output end of power module 3, the isolation protective circuit power input of power module 3, the buffer power output end of power module 3 connects the voltage modulate circuit power input of signal acquisition module 1 successively, the first analog to digital converter power input, the second analog to digital converter power input, the isolation protective circuit power input, the buffer power input; The USB memory circuit output of power module 3, the ethernet physical layer circuit power output of power module 3, the band insulation blocking ethernet interface circuit power output end of power module 3, the RS232 conversion buffer circuit power output end of power module 3, the RS232 communication interface circuit power output of power module 3, the RS485 conversion buffer circuit power output end of power module 3, the RS485 communication interface circuit power output of power module 3, the touch-screen power output end of power module 3, the liquid crystal display screen power output end of power module 3, the CAN physical layer circuit power output end of the band insulation blocking of power module 3, the CAN interface circuit power output end of power module 3, the NANDFLASH built-in storage power output end of power module 3, the Synchronous Dynamic Random Access Memory power output end of power module 3 connects USB memory circuit input successively, Ethernet physical circuit power input, the ethernet interface circuit power input of band insulation blocking, RS232 conversion buffer circuit power input, RS232 communication interface circuit power input, RS485 conversion buffer circuit power input, RS485 communication interface circuit power input, the touch-screen power input, the liquid crystal display screen power input, the CAN physical layer circuit power input of band insulation blocking, CAN interface circuit power input, NANDFLASH built-in storage power input, the Synchronous Dynamic Random Access Memory power input;

Dispose instrument method to set up, method of real-time and failure wave-recording method of operation in the dual core processor of multifunctional electric energy quality monitoring and analyzing system of the present invention;

Wherein, the instrument method to set up may further comprise the steps:

Step 1: operational system is provided with module;

Step 2: the mode of operation of system is set, and is unit work or as a node of monitoring network, if jump to step 3 as unit, if jump to step 6 as a node of monitoring network;

Step 3: the instrument time is set by hand;

Step 4: the number of phases of instrument monitoring is set, and single-phase, three-phase or four phases jump to step 12;

Step 5: when real-time monitoring is set, whether carry out this locality storage;

Step 6: from the GPS reading system time, and is set the cost machine time by the CAN bus;

Step 7: the number of phases of instrument monitoring is set, single-phase, three-phase or four phases;

Step 8: the communication mode that system is set: ethernet communication, RS485 communication or RS232 communication, if ethernet communication then jumps to step 9, if the RS485 communication then jumps to step 10, if the RS232 communication then jumps to step 11;

Step 9: the ethernet communication parameter is set, jumps to step 12;

Step 10: the RS485 messaging parameter is set, jumps to step 12;

Step 11: the RS232 messaging parameter is set;

Step 12: the configuration file of writing system as a result will be set;

Step 13: end is set;

Method of real-time may further comprise the steps:

Step 1: beginning;

Step 2: gather required voltage, electric current and switching value according to system configuration;

Step 3: the data of gathering are analyzed, calculate parameters of electric power and power quality index, parameters of electric power comprises voltage, current effective value, active power, reactive power, apparent power and power factor, and power quality index comprises positive sequence, negative phase-sequence and zero-sequence component, mains frequency and the harmonic wave of voltage deviation, tri-phase unbalance factor, voltage;

Step 4: according to system configuration is single cpu mode, still is as a node of monitoring network, if a node of network jumps to step 7;

Step 5: with the initial data that collects with calculate parameters of electric power and power quality index, show at local LCD;

Step 6: according to configuration file, judge whether to carry out this locality storage,, jump to step 2 if storage just deposits in the local USB storage;

Step 7: the communication pattern that is provided with according to configuration file with the initial data that collects with calculate parameters of electric power and power quality index sends to server, jumps to step 2;

The failure wave-recording method of operation may further comprise the steps:

Step 1: beginning;

Step 2: gather required voltage, electric current and switching value according to system configuration;

Step 3: the data of gathering are analyzed, calculate parameters of electric power and power quality index, parameters of electric power comprises voltage, current effective value, active power, reactive power, apparent power and power factor, and power quality index comprises positive sequence, negative phase-sequence and zero-sequence component, mains frequency and the harmonic wave of voltage deviation, tri-phase unbalance factor, voltage;

Step 4: judge whether to break down, comprise that mainly analog quantity is judged and switching value is judged, according to as follows:

(1) analog quantity starts

It is the most important startup amount of failure wave-recording that analog quantity starts, it is to judge, start the record ripple according to the analog data that failure wave-recording is gathered through system's operational analysis, preserve the data before the fault, the data of record trouble, vibration overall process have different entry conditions according to the different characteristic of analog quantity:

(a) by three-phase voltage, electric current and positive sequence, negative phase-sequence and residual voltage, the sudden change amount of electric current is judged startup;

(c) differential criterion: send out the big poor start-up criterion of change unit; Generator differential current criterion; Main transformer differential current criterion;

(d) the sudden change amount starts: comprise that voltage jump amount and jump-value of current start, startups that whether suddenly change of the voltage of can adjusting, current analog amount passage can be set its definite value as startup, and voltage is generally rated value 5%, and electric current is generally rated value 10%;

(e) voltage, electric current out-of-limit (high limit, lower bound) starts: adjust by passage, can setting more, the upper limit starts and lower limit startup more, the voltage channel higher limit is generally at more than 110% of rated value, lower limit is generally at below 90% of rated value, when voltage greater than 0.5 times rated voltage and when surpassing 3s continuous time, should withdraw from voltage automatically and get over the lower bound start-up criterion, to prevent to record continuously fault data, its set point of current channel is generally greater than rated value;

(f) triple-frequency harmonics starts: dedicated tunnel is carried out triple-frequency harmonics calculate, the triple-frequency harmonics rejection ratio is greater than 100;

(g) generator low is encouraged, loss of excitation starts: by the machine end measure impedance with idle advance to judge mutually start;

(h) the preface component starts: comprise negative sequence voltage, electric current is out-of-limit and residual voltage, the out-of-limit startup of electric current;

(i) overexcitation starts: judged by the ratio of generator terminal voltage and frequency to start;

(j) inverse probability starts: judged by generator active power to start;

(k) open-phase operation and three-phase load are uneven starts: judged by the negative-sequence current steady-state quantity to start;

(l) frequency starts: judged by the generating set frequency to start, contain high frequency, low-frequency start and frequency change rate and start;

(m) direct current signal starts: other forms of physical quantity is transformed into the direct voltage amount through transducer, and entry condition comprises excessive and the amount of owing starts;

(2) switching value start-up criterion: be used to detect auxiliary contact, protective relaying devices (electric, non-electric) such as the hydraulic turbine, boiler, generator, transformer, short-circuiting device and wait each switching value state whether to change, the Starting mode of switching value may be selected to be the switch closure startup or switch disconnects startup, and any one or more switching value all can be provided as enabling signal;

If have any one fault to jump to step 5, do not jump to step 2;

Step 5: according to system configuration is single cpu mode, still is as a node of monitoring network, if a node jumps to step 7;

Step 6: with the initial data that collects with calculate parameters of electric power and power quality index, the LCD in this locality shows;

Step 6: with the initial data that collects with calculate parameters of electric power and power quality index,, deposit in the USB storage of this locality, jump to step 2 according to " 220~500kV electric power system fault dynamically recording technical criteria ";

Step 7: the communication pattern that is provided with according to configuration file, with the initial data that collects with calculate parameters of electric power and power quality index,, send to server according to " 220~500kV electric power system fault dynamically recording technical criteria ", jump to step 2;

Advantage of the present invention: the hardware circuit of multifunctional electric energy quality monitoring and analyzing system of the present invention simply, easily expand, be convenient to install and debugging, the present invention both can be used as a node of whole power quality analysis and failure wave-recording network, use jointly with a plurality of power quality analyzers and server, whole electric energy network is carried out the real-time analysis and the record of fault; Also can be used as an independent portable instrument, the power line of single-phase or three-phase is carried out the real-time analysis and the record of fault, whole electric energy network is carried out the real-time analysis and the record of fault.

Description of drawings

Fig. 1 is a multifunctional electric energy quality monitoring analyzer general structure block diagram of the present invention;

Fig. 2 is a multifunctional electric energy quality monitoring analyzer hardware circuit block diagram of the present invention;

Fig. 3 is multifunctional electric energy quality monitoring analyzer single-phase voltage protective circuit of the present invention, voltage modulate circuit and analog-digital converter circuit schematic diagram;

Fig. 4 is multifunctional electric energy quality monitoring analyzer monophase current protective circuit of the present invention, current regulating circuit and analog-digital converter circuit schematic diagram;

Fig. 5 is multifunctional electric energy quality monitoring analyzer pull-up resistor circuit of the present invention, isolation protective circuit and buffer circuits schematic diagram;

Fig. 6 is the catenation principle figure of multifunctional electric energy quality monitoring analyzer analog to digital converter of the present invention, CPLD and dual core processor;

Fig. 7 is multifunctional electric energy quality monitoring analyzer clock circuit of the present invention, real time clock circuit schematic diagram;

Fig. 8 is multifunctional electric energy quality monitoring analyzer USB circuit of the present invention and peripheral circuit schematic diagram;

Fig. 9 is the ethernet interface circuit schematic diagram of multifunctional electric energy quality monitoring analyzer ethernet physical layer circuit of the present invention, band insulation blocking;

Figure 10 is multifunctional electric energy quality monitoring analyzer RS232 conversion buffer circuit of the present invention and RS232 communication interface circuit theory diagrams;

Figure 11 is a multifunctional electric energy quality monitoring analyzer touch screen circuitry schematic diagram of the present invention;

Figure 12 is multifunctional electric energy quality monitoring analyzer liquid crystal display screen circuit theory diagrams of the present invention;

Figure 13 is the CAN physical layer circuit and the CAN interface circuit schematic diagram of multifunctional electric energy quality monitoring analyzer band of the present invention insulation blocking;

Figure 14 is the circuit connection diagram of multifunctional electric energy quality monitoring analyzer NANDFLASH memory of the present invention;

Figure 15 is a multifunctional electric energy quality monitoring analyzer Synchronous Dynamic Random Access Memory circuit connection diagram of the present invention;

Figure 16 multifunctional electric energy quality monitoring and analyzing system method to set up of the present invention flow chart;

Figure 17 multifunctional electric energy quality monitoring and analyzing system method for real-time monitoring of the present invention flow chart;

Figure 18 multifunctional electric energy quality monitoring and analyzing system failure wave-recording of the present invention flow chart.

Embodiment

Below in conjunction with accompanying drawing the present invention is described in further detail.

Accompanying drawing 1 is a general structure block diagram of the present invention.Multifunctional electric energy quality monitoring analyzer of the present invention is made up of signal acquisition module 1, signal analysis scheduler module 2 and power module 3, server 4 and global positioning system 5; Described tested three-phase alternating voltage, three-phase alternating current are input to the voltage signal input and the current signal input of signal acquisition module 1 respectively, and switching value is input to the digital signal input end of signal acquisition module 1; The input/output terminal of the parallel bus interface circuit of signal acquisition module 1 connects the input/output terminal of the parallel bus interface circuit of signal analysis scheduler module 2; Second input/output terminal of second input/output terminal of second input/output terminal of the ethernet interface circuit of the band insulation blocking of signal analysis scheduler module 2, RS232 communication interface circuit and RS485 communication interface circuit is first input/output terminal, second input/output terminal and the 3rd input/output terminal of Connection Service device 4 respectively, selection is wherein a kind of arbitrarily according to user's needs during use, and second input/output terminal of the CAN communication interface circuit of signal analysis scheduler module 2 connects the input/output terminal of global positioning system 5; First circuit output end of pressure-stabilizing of power module 3 connects the power input of signal acquisition module 1, and second circuit output end of pressure-stabilizing of power module 3 connects the power supply signal input of signal analysis scheduler module 2;

Signal transduction process:

The present invention gathers the analog signal of three-phase four-wire system electric power system or three-phase three-wire system electric power system: comprise 4 road three-phase alternating voltages and 4 road three-phase alternating currents, the related device dumb contact provides 32 way word switch amount signals; 8 road voltage/current analog signals convert 8 16 bit data to through after the signal acquisition module 1,32 way word switch amounts convert 2 16 bit data to, these 10 16 bit data pass to signal analysis scheduler module 2 by signal through signal acquisition module 1, after signal analysis scheduler module 2 is received data, these data are carried out real-time analysis, calculate parameters of electric power and power quality index, the result is exported to server or in local USB memory device, store.

Signal acquisition module 1 of the present invention includes: voltage protection circuit 1-1, voltage modulate circuit 1-2, the first analog to digital converter 1-3, current protecting circuit 1-4, current regulating circuit 1-5, the second analog to digital converter 1-6, pull-up resistor circuit 1-7, isolation protective circuit 1-8, buffer 1-9 and CPLD 1-10 as Fig. 3~shown in Figure 6;

Among Fig. 3, voltage protection circuit 1-1 is made up of piezo-resistance RVDR2, first capacitor C 10, second capacitor C 2 and the 3rd capacitor C 11; The A phase voltage+UA end connects an end, first capacitor C, 10 1 ends, an end of second capacitor C 2 and first output of voltage protection circuit of piezo-resistance RVDR2, the A phase voltage-UA end connects the other end, the other end of first capacitor C 10, an end of the 3rd capacitor C 11 and second output of voltage protection circuit of piezo-resistance RVDR2, and the other end of second capacitor C 2 is connected with the other end of the 3rd capacitor C 11 and connects tool housing; The model of piezo-resistance RVDR2 is S20K250E2;

Voltage modulate circuit 1-2 is made up of current-limiting resistance RA4, voltage transformer pt 2, transient voltage voltage stabilizing didoe D1, sample resistance RA2, operational amplifier U1, low-pass filtering resistance R 2 and the 4th capacitor C 12; First output of voltage protection circuit 1-1 connects the input of current-limiting resistance RA4, and second output of voltage protection circuit 1-1 connects the former limit pin 2 of voltage transformer pt 1; The output of current-limiting resistance RA4 connects the former limit pin 1 of voltage transformer pt 2; The secondary pin 4 of voltage transformer pt 1 connects an end, the end of sample resistance RA2 and the pin 2 of operational amplifier U1 of transient voltage voltage stabilizing didoe D1, and the other end of the secondary pin 3 connection transient voltage voltage stabilizing didoe D1 of voltage transformer pt 1 and the pin 3 of operational amplifier also connect simulation ground; The pin 6 of the other end concatenation operation amplifier U1 of sample resistance RA2 and the input of low-pass filtering resistance R 2; The pin 4 connection-15VA power supplys of operational amplifier U1, the power supply of the pin 7 connection+15VA of operational amplifier U1, the output of low-pass filtering resistance R 2 connects an end of the 4th capacitor C 12 and the output UA of voltage modulate circuit 1-2, another termination simulation ground of the 4th capacitor C 12; Described voltage transformer pt 1 model is soldier's word TVA1421, and operational amplifier U1 model is OPA211, and transient voltage voltage stabilizing didoe D1 model is 1.5KE15 (C) A;

The voltage protection circuit of three-phase voltage is identical therewith with the voltage modulate circuit in addition; The voltage modulate circuit will import ± and the alternating voltage of 500V nurses one's health ± the alternating voltage output signal of 5V, in the process of conditioning, require nonlinearity to be not more than 0.1%, phase shift is less than 5 ';

The output UA of voltage modulate circuit 1-2 connects the pin 33 of first analog to digital converter 1.3, and other three road alternating voltages are behind correspondent voltage protective circuit and voltage modulate circuit, and its output connects pin 36, pin 39 and the pin 42 of first analog to digital converter 1.3 successively; The pin 54 of first analog to digital converter 1.3, pin 56, pin 58, pin 51 connect an end of the 5th capacitor C 29, an end of the 6th capacitor C 28, an end of the 7th capacitor C 17, an end of the 8th capacitor C 18 successively, and the other end of the 5th capacitor C 29 connects the other end of the 6th capacitor C 28, the other end of the 7th capacitor C 17 and the other end and the ground connection of the 8th capacitor C 18; Pin 63 connecting pins 61 of first analog to digital converter 1.3 and pin 24 also connect+the 3.3V power supply, 62 pin of the first analog to digital converter 1-3 connect 29 pin and 20 pin and ground connection, 27 pin of the first analog to digital converter 1-3 connect an end of resistance R 9 and an end of resistance R 10, another termination power+3.3V of resistance R 9, the other end ground connection of resistance R 10,64 pin connecting pins, 1~pin 7 and the ground connection of the first analog to digital converter 1-3, pin 11 ground connection, pin 12 connecting pins 13~pin 16 and ground connection, pin 17 connects+the 3.3V power supply; The model of the described first analog to digital converter 1-3 and the second analog to digital converter 1-6 is ADS8556;

Among Fig. 4, current protecting circuit 1-4 is made up of resettable fuse FS, and the A phase current of three-phase alternating current is input to the end of resettable fuse FS from+IA end, and the other end of resettable fuse FS is as the output of current protecting circuit 1-4;

Current regulating circuit 1-5 is made up of current transformer CT1, transient voltage voltage stabilizing didoe D2, sample resistance RA5, operational amplifier U3, low-pass filtering resistance R 3 and the first electric capacity R13; The output of current protecting circuit 1-4 connects 5 pin of current transformer RA5, A phase current-IA end is connected to the pin 6 of current transformer CT1, the pin 3 of current transformer CT1 connects input, the end of transient voltage voltage stabilizing didoe D2 and the pin 2 of operational amplifier U3 of sample resistance RA5, and the other end of the pin 4 connection transient voltage voltage stabilizing didoe D3 of current transformer CT1 and the pin 3 of operational amplifier also connect simulation ground; The pin 6 of operational amplifier U3 connects the other end of sample resistance RA5 and the input of low-pass filtering resistance R 3; The pin 4 connection-15VA power supplys of operational amplifier U3, the power supply of the pin 7 connection+15VA of operational amplifier U3; The output of low-pass filtering resistance R 3 connects an end of first capacitor C 13 and the output IA of current regulating circuit 1-5; Another termination simulation ground of first capacitor C 13; Described current transformer CT1 model is soldier's word TA1016, and the model of operational amplifier U3 is OPA211, and the model of transient voltage diode D2 is 1.5KE15 (C) A;

The voltage protection circuit of three-phase current is identical therewith with the voltage modulate circuit in addition; The current regulating circuit will import ± and the alternating current of 20A converts to ± output-current rating of 20mA, makes the voltage of output ± 5V by sampling resistor;

The output IA of current regulating circuit 1-5 connects the pin 33 of the second analog to digital converter 1-6, and in like manner, other three road current signals connect pin 36, pin 39 and the pin 42 of the second analog to digital converter 1-6 respectively;

Among Fig. 5, be example, the circuit connecting relation of pull-up resistor circuit 1-7, isolation protective circuit 1-8, buffer 1-9 is described with one group of 8 way word switch amount.

Pull-up resistor circuit 1-7 is made up of first resistance R 7, second resistance R 4, the 3rd resistance R 3, the 4th resistance R the 2, the 5th resistance R 11, the 6th resistance R 10, the 7th resistance R 9, the 8th resistance R 8; Isolation protective circuit 1.8 is made up of the first insulation blocking chip U5 and the second insulation blocking chip U6; Buffer 1.9 is made up of buffer U7; 8 tunnel amounts of opening the light signal is connecting pin DSI0~DSI3 and pin DSI4~DSI7 respectively, pin DSI0 connects an end of first resistance R 7 and the pin 3 of the first insulation blocking chip U5, pin DSI1 connects an end of second resistance R 4 and the pin 4 of the first insulation blocking chip U5, pin DSI2 connects an end of the 3rd resistance R 3 and the pin 5 of the first insulation blocking chip U5, the DSI3 end connects an end of the 4th resistance R 2 and the pin 6 of the first insulation blocking chip U5, the other end of first resistance R 7 connects the other end of second resistance R 4, the other end of the 3rd resistance R 3, the other end of the 4th resistance R 2, the pin 1 of one end of first capacitor C 59 and insulation blocking chip U5 also is connected+the 5VE power supply, and the other end of first capacitor C 59 connects pin 2 and the tool housing of the first insulation blocking chip U5; The pin 11 of the first insulation blocking chip U5, pin 12, pin 13 and pin 14 are according to the pin 5, pin 4, pin 3, the pin 2 that are connected buffer U7; The pin 16 of the first insulation blocking chip U5 connects an end of second capacitor C 58 and connects+the 3.3V power supply, and the pin 15 of the first insulation blocking chip U5 connects the other end and the ground connection of second capacitor C 58; The pin 10 connection+3.3V power supplys of the first insulation blocking chip U5; Pin 9 ground connection of the first insulation blocking chip U5;

Pin DSI4 connects an end of the 5th resistance R 11 and the pin 3 of the second insulation blocking chip U6, pin DSI5 connects an end of the 6th resistance R 10 and the pin 4 of the second insulation blocking chip U6, pin DSI6 connects an end of the 7th resistance R 9 and the pin 5 of the second insulation blocking chip U6, and pin DSI7 connects an end of the 8th resistance R 8 and the pin 6 of the second insulation blocking chip U6; The other end of the other end of the other end of the other end of the 5th resistance R 11, the 6th resistance R 10, the 7th resistance R 9 and the 8th resistance R 8 is connected the pin 1 of the end of the 3rd capacitor C 65 and the second insulation blocking chip U6 and connects+the 5VE power supply; The other end of the 3rd capacitor C 65 connects the pin 2 of the second insulation blocking chip U6 and connects tool housing; The pin 16 of the second insulation blocking chip U6 connects an end of the 4th capacitor C 66 and connects+the 3.3V power supply; The pin 15 of the second insulation blocking chip U6 connects the other end and the ground connection of the 4th capacitor C 66; The pin 14 of the second insulation blocking chip U6, pin 13, pin 12 and pin 11 are connected pin 6, pin 7, pin 8 and the pin 9 of buffer U7 successively; Pin 9 ground connection of the second insulation blocking chip U6; The pin 10 of the second insulation blocking chip U6 connects+the 3.3V power supply; The pin 1 of buffer U7 connects an end of the 9th resistance R 25 and connects+the 3.3V power supply; The other end of the 9th resistance R 25 connects the pin 19 of buffer U7; The pin 20 of buffer U7 connects an end of the 5th capacitor C 62 and connects+the 3.3V power supply, and the pin 10 of buffer U7 connects the other end and the ground connection of the 5th electric capacity; The model of the first insulation blocking chip and the second insulation blocking chip is ISO7240, and the model of buffer is SN74LVTH245A;

As Fig. 6 is the circuit theory diagrams of the first analog to digital converter 1-3, the second analog to digital converter 1-6 and CPLD 1-10, dual core processor 2-1.The pin 7 of the first analog to digital converter 1-3, pin 11, pin 18, pin 19, pin 21, pin 22, pin 23 and pin 28 are connected pin 112, pin 113, pin 118, pin 117, pin 109, pin 110, pin 111 and the pin 114 of CPLD 1-10 successively; The pin 7 of the second analog to digital converter 1-6, pin 11, pin 18, pin 19, pin 21, pin 22, pin 23 and pin 28 are connected pin 123, pin 124, pin 129, pin 127, pin 120, pin 121, pin 122 and the pin 125 of CPLD 1-10 successively; Pin 11~pin 18 of buffer 1-9 connects pin 137~pin 144 of CPLD 1-10 successively,

Other 3 group of 8 way word switch amount signal is connected to pin 1~pin 8, pin 11~pin 16, pin 21~pin 24, pin 27~pin 32, the pin 37~pin 44 of CPLD 1-10 respectively;

Pin 87~pin 88 of programmable logic device (CPLD) 1-10, pin 93~pin 98, pin 101~108 pin, pin 71~pin 72, pin 73~81 pin and 84 pin~86 pin, pin 58, pin 59, pin 62, pin 63, pin 66, pin 67, pin 68, pin 69 and pin 70 are connected pin EMA_D14~EMA_D15 of dual core processor 2-1 parallel bus interface EMIFA successively, EMA_D8~EMA_D13, EMA_D0~EMA_D7, EMA_A12~EMA_A13, EMA_A3~EMA_A11, EMA_A0~EMA_A2, CS0, CS4, CS5, BA1, BA0, WE, DQM2, DQM1 and OE; The model of dual core processor is OMAPL137.

The circuit of signal analysis scheduler module 2 connects as Fig. 7~shown in Figure 15.

Fig. 7 is clock circuit 2-2, real time clock circuit 2-3 and dual core processor 2-1 circuit theory diagrams;

Clock circuit 2-2 is connected to the phase-locked loop of dual core processor 2-1 inside, and phase-locked loop carries out frequency multiplication to the clock that clock circuit 2-2 provides, for dual core processor provides clock.Among the clock circuit 2-2, the end of the first crystal oscillator Y1 connects an end of first capacitor C 14 and the pin F2 of dual core processor 2-1, the other end of the first crystal oscillator Y1 connects an end of second capacitor C 27 and is connected with the pin F1 of dual core processor 2-1, and the other end of second capacitor C 27 is connected with the pin E2 of dual core processor after connecting the other end of first capacitor C 14; Pin 1 connection of magnet ring F1 and an end of the 3rd capacitor C 39 also connect+the 1.2V power supply, the pin 3 of magnet ring F1 connects an end, an end of the 5th capacitor C 42 and the pin D1 of dual core processor 2-1 of the 4th capacitor C 40, and the other end of the 3rd capacitor C 39 connects pin 2, the other end of the 4th capacitor C 40, the other end of the 5th capacitor C 42 and pin E1 and the ground connection of dual core processor 2-1 of magnet ring F1;

Among the real time clock circuit 2-3, the pin G1 of dual core processor connects an end of the 6th capacitor C 25, an end of the 7th capacitor C 26, the end of the 8th capacitor C F1 and the negative pole of diode D3 successively, the other end of the 6th capacitor C 25 is connected with the other end of the 7th capacitor C 26 and ground connection, the other end ground connection of the 8th capacitor C F1; The positive pole of diode D3 connects an end of first resistance R 7, another termination+1.8V power supply of first resistance R 7, the end of the second crystal oscillator Y2 connects an end of end of second resistance R 8 and the 9th capacitor C 38 and is connected with the pin H1 of dual core processor 2-1, the other end of the second crystal oscillator Y2 connect second resistance R 8 the other end, the tenth capacitor C 44 an end and be connected with the pin H2 of dual core processor 2-1, the other end of the other end of the tenth capacitor C 44, the 9th capacitor C 38 connects an end of the 3rd resistance R 9, and the other end of the 3rd resistance R 9 connects the pin G2 of dual core processor 2-1;

Fig. 8 is extremely peripheral circuit 2-4 of USB controller, and this circuit comprises distributor, electromagnetic compatibility protection chip, distributor, magnet ring, electric capacity and inductance, and pin 1~pin 4 of the peripheral plug J4 of USB controller connects the input/output terminal of USB flash disk 1-4; The model of distributor is TPS2065, and the model of electromagnetic compatibility protection chip is the model NFM21PC474R1C3D of TPPD2E001, magnet ring;

Fig. 9 is the Ethernet control circuit, the ethernet interface circuit 2-6 that comprises ethernet physical layer 2-5, band insulation blocking, described ethernet physical layer circuit 2-5 is made up of ethernet physical layer chip U11, and the ethernet interface circuit 2-6 of band insulation blocking is made up of the Ethernet interface J7 and the protection chip of band insulation blocking; The pin 2 of ethernet physical layer chip U15A, pin 5, pin 6, pin 9, pin 10, pin 15, pin 16, pin 17, pin 18 connects the pin A6 of dual core processor 2-1 successively, pin C7, pin B7, pin A7, pin D7, pin A4, pin D8, pin B8, pin C8, the pin 1 of ethernet physical layer chip U11 connects an end of first resistance R 32 and the pin B6 of dual core processor, other end connection+3.3V the power supply of first resistance R 32, pin 14 ground connection of ethernet physical layer chip U11, pin 19 is connected with pin 20 and ground connection, pin 21 connects an end of second resistance R 35, pin 22 connects an end of the 3rd resistance R 34, and the other end of the other end of second resistance R 35 and the 3rd resistance R 34 is connected and connects+the 3.3V power supply; The pin 41 of ethernet physical layer chip U11 connects the end of the 4th resistance R A5, the pin 1 of the ethernet interface circuit J7 of the pin 1 of the first protection chip and band insulation blocking, the other end of the 4th resistance R A5 connects the end of the 5th resistance R A6 successively, the end of the 6th resistance R A7, the end of the 7th resistance R A8, pin 5 and the pin 2 of the ethernet interface circuit J7 of band insulation blocking, one end of first capacitor C 90, one end of second capacitor C 97 also connects+the 3.3V power supply, the pin 40 of ethernet physical layer chip U11 connects the pin 2 of the first protection chip and is with the pin 3 of the Ethernet interface chip J7 of insulation blocking, the pin 33 of ethernet physical layer chip U11 connects the other end of the 6th resistance R 47, the pin 4 of the ethernet interface circuit J7 of the pin 1 of the second protection chip and band insulation blocking, the pin 32 of ethernet physical layer chip U11 connects the pin 2 of the second protection chip and is with the pin 6 of the ethernet interface circuit J7 of insulation blocking, the other end of the other end of first capacitor C 90 and second capacitor C 97 is connected and ground connection, and the pin 9 of the ethernet interface circuit J7 of band insulation blocking is connected with pin 11 and connects+the 3.3V power supply; The pin 26 of ethernet physical layer chip and pin 27 be the pin 12 and the pin 10 of the Ethernet interface of connecting band insulation blocking successively; The model of ethernet physical layer chip is KSZ8001, and the model of the Ethernet interface chip of band insulation blocking is 13F-60AGYD2PL2NL, and the model of protection chip is TPN3021;

Figure 10 is the RS232 transmission circuit, comprises RS232 conversion buffer circuit 2-7 and RS232 communication interface circuit 2-8, and described RS232 conversion buffer circuit 2-7 is made up of level conversion isolating chip U12; The pin 11 of level conversion isolating chip U12 and pin 12 are connected pin D6 and the pin C6 of dual core processor 2-1 successively, the pin 1 of level conversion isolating chip U6 connects an end of first capacitor C 55, the pin 3 of level conversion isolating chip U12 connects the other end of first capacitor C 55, the pin 4 of level conversion isolating chip U12 connects an end of second capacitor C 60, and the pin 5 of level conversion isolating chip U12 connects the other end of second capacitor C 60; The pin 14 of level conversion isolating chip U12 and pin 13 are connected the pin RS232_1_TXD and the pin RS232_1_RXD pin of RS232 communication interface circuit successively; The pin 2 of level conversion isolating chip U12 connects an end of the 4th capacitor C 56, the pin 6 of level conversion isolating chip U12 connects an end of the 3rd capacitor C 50, the pin 15 of level conversion isolating chip U12 connects the other end, the other end of the 4th capacitor C 56 and an end and the ground connection of the 5th capacitor C 43 of the 3rd capacitor C 50, and the pin 16 of level conversion isolating chip U12 connects the other end of the 5th capacitor C 43 and connects+the 3.3V power supply;

Figure 11 is touch screen control circuit 2-11, SPI0 by dual core processor 2-1 in the present embodiment extends out a touch screen controller U13, the pin R5 of dual core processor 2-1, pin R6, pin T5, pin P6, pin N4, pin B4 connect pin 11, pin 12, pin 16, pin 14, pin 15 and the pin 13 of touch screen controller U13 successively, and pin 2~pin 5 of touch screen controller U13 connects the touch-screen input; Wherein the model of touch screen controller is TSC2046IPWR;

Figure 12 is the liquid crystal display screen circuit, comprises integrated load switch U15, the first buffer U14, the second buffer U16 and LCD screen; The pin 5 of integrated load switch U15 connects the pin L2 of dual core processor 2-1, pin 2~pin 5 of the first buffer U14, pin 19 connects the pin T11 of dual core processor 2-1 successively, pin R11, pin N8, pin P11 and pin C5, the pin 18 of the first buffer U14, pin 17, pin 16, pin 15 connects the pin LCD_DCLK of LCD screen successively, pin LCD_HSYNC, pin LCD_VSYNC, pin LCD_nENB, the pin 47 of the second buffer U16, pin 46, pin 44, pin 43, pin 41, pin 40, pin 38 pin 37, pin 36, pin 35, pin 33, pin 32, pin 30, pin 29, pin 27, pin 26 connects the pin M16 of dual core processor 2-4 successively, pin N14, pin N16, pin P14, pin P16, pin R14, pin T14, pin N12, pin T9, pin N9, pin P8, pin R8, pin T10, pin R10, pin P10, pin N10, the pin 2 of the second buffer U16, pin 3, pin 5, pin 6, pin 8, pin 9, pin 11, pin 12, pin 13, pin 14, pin 16, pin 17, pin 19, pin 20, pin 22, pin 23 connects the pin LCD_D15~LCD_D0 of LCD screen successively; The model of integrated load switch is FDC6331L, and the model of first buffer is SN74LVTH245A, and the model of second buffer is SN74LVTH16245A;

Figure 13 is a CAN transport module circuit, and the SPI1 by dual core processor 2-1 in the present embodiment extends out a CAN controller, and this CAN transport module comprises the CAN physical layer circuit 2-13 and the CAN interface circuit 2-14 of CAN controller, band insulation blocking; The pin 1 of CAN controller U18, pin 2 pin are pin 3 and the pin 4 of the CAN physical chip U17 of connecting band insulation blocking respectively, the pin 11 of CAN controller U18 connects an end of first resistance R 30, the other end of first resistance R 30 connects the negative pole of the first light-emitting diode D6, the positive pole connection+3.3V power supply of the first light-emitting diode D6; The pin 12 of CAN controller U18 connects an end of second resistance R 31, and the other end of second resistance R 31 connects the negative pole of second light-emitting diode, the positive pole connection+3.3V power supply of second light-emitting diode; The pin 8 of CAN controller connects the end of crystal oscillator Y2 and an end of first capacitor C 68, and the other end of crystal oscillator Y2 connects the pin 9 of CAN controller U18 and an end of second capacitor C 69, and the other end of first capacitor C 68 connects the other end and the ground connection of second capacitor C 69; The pin 18 of CAN controller U15, pin 17, pin 16, pin 14, pin 13 be connecting pin P4, pin P5, pin N3, pin T6, pin R4 successively, the pin 20 of CAN controller U18 connects an end of the 3rd capacitor C 70 and connects+the 3.3V power supply, and the pin 10 of CAN controller U18 connects an end and the ground connection of the 3rd capacitor C 70; 1 pin of the CAN physical layer U17 of band insulation blocking connects an end of the 4th capacitor C 71,2 pin and the ground connection of the CAN physical layer U17 of the other end connecting band insulation blocking of the 4th capacitor C 71; 8 pin of CAN physical layer U17 of band insulation blocking connect shell, and connect 3 pin of CAN joint J11 through 2,7 pin that capacitor C 72 and resistance R 28 meet CAN joint J11, and 6 pin of the CAN physical layer U17 of band insulation blocking connect 4 pin of CAN joint J11; CAN controller model is MCP2515-1/ST, and the model of the CAN physical chip of band insulation blocking is CTM1050T;

Figure 14 is the circuit connection diagram of NANDFLASH memory and dual core processor 2-1, the EMA_WAIT0 pin of dual core processor 2-1, EMA_OE pin, EMA_CS3 pin, EMA_CS2 pin, EMA_A2 pin, EMA_A1 pin, EMA_WE pin, EMA_D0 pin~EMA_D7 pin connect 6 pin, 8 pin, 9 pin, 10 pin, 16 pin, 17 pin, 18 pin, 29 pin~32 pin of NASHFLASH memory successively, 41 pin~44 pin, 12 pin and 37 pin of NASHFLASH memory connect+the 3.3V power supply, 13 pin and 36 pin ground connection;

Figure 15 is the circuit connection diagram of Synchronous Dynamic Random Access Memory 2-6 and dual core processor 2-1, the EMB_D0 pin~EMB_D15 pin of dual core processor, the EMB_WE_DQM0 pin, the EMB_WE_DQM1 pin, EMB_A0 pin~EMB_A12 pin, the EMB_B0 pin, the EMB_BA1 pin, the EMB_CLK pin, the EMB_SDCKE pin, the EMB_CS pin, the EMB_RAS pin, the EMB_PAS pin, the EMB_WE pin connects D0~D15BA0 pin of the first synchronous DRAM SDRAM successively, the DQML pin, the DQMH pin, A0 pin~A12 pin, the BA0 pin, the BA1 pin, the CLK pin, the CKE pin, the CS pin, the RAS pin, the PAS pin, the WE pin; VDDQ.1 pin~VDDQ.4 pin and the VDD.1 pin~VDD.3 pin of the first synchronous DRAM SDRAM connect+the 3.3V power supply simultaneously; VSS.1 pin~VSS.3 the pin of the first synchronous DRAM SDRAM and VSSQ.1 pin~VSSQ.4 pin is ground connection simultaneously; EMB_D16 pin~EMB_D31 the pin of dual core processor, the EMB_WE_DQM2 pin, the EMB_WE_DQM3 pin, EMB_A0 pin~EMB_A12 pin, the EMB_B0 pin, the EMB_BA1 pin, the EMB_CLK pin, the EMB_SDCKE pin, the EMB_CS pin, the EMB_RAS pin, the EMB_PAS pin, the EMB_WE pin connects D0~D15BA0 pin of the first synchronous DRAM SDRAM successively, the DQML pin, the DQMH pin, A0 pin~A12 pin, the BA0 pin, the BA1 pin, the CLK pin, the CKE pin, the CS pin, the RAS pin, the PAS pin, the WE pin; VDDQ.1 pin~VDDQ.4 pin and the VDD.1 pin~VDD.3 pin of the second synchronous DRAM SDRAM connect+the 3.3V power supply simultaneously; VSS.1 pin~VSS.3 the pin of the second synchronous DRAM SDRAM and VSSQ.1 pin~VSSQ.4 pin is ground connection simultaneously; The model of synchronous DRAM is MT48LC16M16A2P-75;

Described power module 3 comprises DC-DC switch voltage-stabilizing circuit 3-1, power transfer module 3-2 and AC-DC transformer 3-3.Described DC-DC switch voltage-stabilizing circuit 3-1 comprises 3 DC-DC voltage stabilizing chips, an output 3.3V, an output 1.8V and an output 1.2V's, select TPS54331, REG1117A-1.8 and TPS54331 respectively for use; Described power transfer module 3-2 comprises three DC-DC switch voltage-stabilizing circuits: a DC-DC power conversion chip, the 2nd DC-DC power conversion chip and the 3rd DC-DC power conversion chip, model is respectively the 4NIC-D2-S of 5V2W, the 4NIC-D2-S of 5V15W, ± 4NIC-DC5-D of 15V5W; The civil power of 220V50Hz is converted to the input of the direct current access power transfer module 3.2 of 12V.Power transfer module 3.2 with the 12V voltage transitions become two-way 5V and ± 15V, and pass to DC-DC conversion voltage stabilizing chip.DC DC conversion voltage stabilizing chip with two-way 5V and ± 15V converts to ± 15V, 5VA, 5VD, 5VE, 3.3V, 1.8V and 1.2V etc., the whole instrument power supply, wherein 5VA represents to be used for the 5V electricity to the analogue device power supply, and 5VD represents the 5V electricity to the digital device power supply of 5V, and 5VE represents the 5V to the isolating device power supply of the isolating device of digital switch quantity and communication interface.

Claims (7)

1. a multifunctional electric energy quality monitoring and analyzing system is characterized in that: comprise a plurality of multifunctional electric energy quality monitoring analyzers, global positioning system and server computer; A plurality of multifunctional electric energy quality monitoring analyzers carry out communication by Ethernet or CAN bus interface or RS232 communication interface or RS485 communication interface and global positioning system and server computer respectively;
Described multifunctional electric energy quality monitoring analyzer is made up of signal acquisition module 1, signal analysis scheduler module 2 and power module 3, server 4 and global positioning system 5; Described tested three-phase alternating voltage, three-phase alternating current are input to the voltage signal input and the current signal input of signal acquisition module 1 respectively, and switching value is input to the digital signal input end of signal acquisition module 1; The input/output terminal of the parallel bus interface circuit of signal acquisition module 1 connects the input/output terminal of the parallel bus interface circuit of signal analysis scheduler module 2; Second input/output terminal of second input/output terminal of second input/output terminal of the ethernet interface circuit of the band insulation blocking of signal analysis scheduler module 2, RS232 communication interface circuit and RS485 communication interface circuit is first input/output terminal, second input/output terminal and the 3rd input/output terminal of Connection Service device 4 respectively, and second input/output terminal of the CAN communication interface circuit of signal analysis scheduler module 2 connects the input/output terminal of global positioning system 5; First circuit output end of pressure-stabilizing of power module 3 connects the power input of signal acquisition module 1, and second circuit output end of pressure-stabilizing of power module 3 connects the power input of signal acquisition module 1 and the power supply signal input of signal analysis scheduler module 2.
2. a kind of multifunctional electric energy quality monitoring and analyzing system according to claim 1 is characterized in that: the signal acquisition module 1 of described multifunctional electric energy quality monitoring analyzer includes: voltage protection circuit 1-1, voltage modulate circuit 1-2, the first analog to digital converter 1-3, current protecting circuit 1-4, current regulating circuit 1-5, the second analog to digital converter 1-6, pull-up resistor circuit 1-7, isolation protective circuit 1-8, buffer 1-9 and CPLD 1-10; Three-phase alternating voltage connects the voltage input end of voltage protection circuit 1-1, the output of voltage protection circuit 1-1 connects the input of voltage modulate circuit 1-2, the output of voltage modulate circuit 1-2 connects the input end of analog signal of the first analog to digital converter 1-3, and the digital signal input/output terminal of the first analog to digital converter 1-3 connects the first digital signal input/output terminal of the analog to digital converter controller of CPLD 1-10; Three-phase alternating current connects the alternating current input of current protecting circuit 1-4, the output of current protecting circuit 1-4 connects the input that exchanges modulate circuit 1-5, the output of current regulating circuit 1-5 connects the input end of analog signal of the second analog to digital converter 1-6, and the digital signal input/output terminal of the second analog to digital converter 1-6 connects the second digital signal input/output terminal of the analog to digital converter controller of CPLD 1-10; The switching value signal connects the end of pull-up resistor 1-7; the other end of pull-up resistor circuit 1-7 connects the input of isolation protective circuit; the output of isolation protective circuit 1-8 connects the input of buffer, and the input/output terminal of buffer 1-9 connects the input/output terminal of the switch acquisition controller of complex programmable controller 1-10.
3. a kind of multifunctional electric energy quality monitoring and analyzing system according to claim 1 is characterized in that: the signal analysis scheduler module 2 of described multifunctional electric energy quality monitoring analyzer includes: dual core processor 2-1, clock circuit 2-2, real time clock circuit 2-3, USB memory circuit 2-4, ethernet physical layer circuit 2-5, the ethernet interface circuit 2-6 of band insulation blocking, RS232 conversion buffer circuit 2-7, RS232 communication interface circuit 2-8, RS485 conversion buffer circuit 2-9, RS485 communication interface circuit 2-10, touch-screen 2-11, liquid crystal display screen 2-12, the CAN physical layer circuit 2-13 of band insulation blocking, CAN interface circuit 2-14, NANDFLASH built-in storage 2-15, Synchronous Dynamic Random Access Memory 2-16; The input/output terminal of the parallel bus interface of described dual core processor 2-1, the input of phase-locked loop circuit, the input of real time clock circuit, the input/output terminal of USB controller, the data/address bus address bus input/output terminal of ethernet controller, the input/output terminal of the first universal asynchronous reception/dispensing device UART1 interface circuit, the input/output terminal of the second universal asynchronous reception/dispensing device UART2 interface circuit, the input of touch screen controller, the data address bus output of liquid crystal display screen controller, the input/output terminal of CAN controller, the input/output terminal of the data address bus of first memory controller A, the data address bus input/output terminal of second memory controller B connects the input/output terminal of the parallel bus interface of signal acquisition module 1, the output of clock circuit 2-2 successively, the output of real time clock circuit 2-3, the input/output terminal of USB memory circuit 2-4, the input/output terminal of the data address bus of ethernet physical layer circuit 2-5, first input/output terminal of RS232 conversion buffer circuit 2-7, first input/output terminal of RS485 conversion buffer circuit 2-9, the output of touch-screen 2-11, the data address bus input of liquid crystal display screen 2-12, first input/output terminal of the CAN physical layer circuit 2-13 of band insulation blocking, the input/output terminal of the data address bus of NANDFLASH built-in storage 2-15 and the input/output terminal of Synchronous Dynamic Random Access Memory 2-16; First input/output terminal of the ethernet interface circuit 2-6 of the input/output terminal connecting band insulation blocking of ethernet physical layer circuit 2-5; Second input/output terminal of RS232 conversion buffer circuit 2-7 connects first input/output terminal of RS232 communication interface circuit 2-8; Second input/output terminal of RS485 conversion buffer circuit 2-9 connects first input/output terminal of RS485 communication interface circuit 2-10; Second input/output terminal of the CAN physical layer circuit 2-13 of band insulation blocking connects first input/output terminal of CAN interface circuit 2-14.
4. a kind of multifunctional electric energy quality monitoring and analyzing system according to claim 2 is characterized in that: the voltage protection circuit 1-1 of described multifunctional electric energy quality monitoring analyzer is made up of piezo-resistance RVDR2, first capacitor C 10, second capacitor C 2 and the 3rd capacitor C 11; The A phase voltage+UA end connects an end, first capacitor C, 10 1 ends, an end of second capacitor C 2 and first output of voltage protection circuit of piezo-resistance RVDR2; the A phase voltage-UA end connects the other end, the other end of first capacitor C 10, an end of the 3rd capacitor C 11 and second output of voltage protection circuit of piezo-resistance RVDR2, and the other end of second capacitor C 2 is connected with the other end of the 3rd capacitor C 11 and connects tool housing.
5. a kind of multifunctional electric energy quality monitoring and analyzing system according to claim 2 is characterized in that: the voltage modulate circuit 1-2 of described multifunctional electric energy quality monitoring analyzer is made up of current-limiting resistance RA4, voltage transformer pt 2, transient voltage voltage stabilizing didoe D1, sample resistance RA2, operational amplifier U1, low-pass filtering resistance R 2 and the 4th capacitor C 12; First output of voltage protection circuit 1-1 connects the input of current-limiting resistance RA4, and second output of voltage protection circuit 1-1 connects the former limit pin 2 of voltage transformer pt 1; The output of current-limiting resistance RA4 connects the former limit pin 1 of voltage transformer pt 2; The secondary pin 4 of voltage transformer pt 1 connects an end, the end of sample resistance RA2 and the pin 2 of operational amplifier U1 of transient voltage voltage stabilizing didoe D1, and the other end of the secondary pin 3 connection transient voltage voltage stabilizing didoe D1 of voltage transformer pt 1 and the pin 3 of operational amplifier also connect simulation ground; The pin 6 of the other end concatenation operation amplifier U1 of sample resistance RA2 and the input of low-pass filtering resistance R 2; The pin 4 connection-15VA power supplys of operational amplifier U1, the power supply of the pin 7 connection+15VA of operational amplifier U1, the output of low-pass filtering resistance R 2 connects an end of the 4th capacitor C 12 and the output UA of voltage modulate circuit 1-2, another termination simulation ground of the 4th capacitor C 12.
6. a kind of multifunctional electric energy quality monitoring and analyzing system according to claim 2; it is characterized in that: the current protecting circuit 1-4 of described multifunctional electric energy quality monitoring analyzer is made up of resettable fuse FS; three-phase alternating current is input to the end of resettable fuse FS from+IA end, and the other end of resettable fuse FS is as the output of current protecting circuit 1-4.
7. a kind of multifunctional electric energy quality monitoring and analyzing system according to claim 2 is characterized in that: the current regulating circuit 1-5 of described multifunctional electric energy quality monitoring analyzer is made up of current transformer CT1, transient voltage voltage stabilizing didoe D2, sample resistance RA5, operational amplifier U3, low-pass filtering resistance R 3 and the first electric capacity R13; The output of current protecting circuit 1-4 connects 5 pin of current transformer RA5,-IA end is connected to the pin 6 of current transformer CT1, the pin 3 of current transformer CT1 connects input, the end of transient voltage voltage stabilizing didoe D2 and the pin 2 of operational amplifier U3 of sample resistance RA5, and the other end of the pin 4 connection transient voltage voltage stabilizing didoe D3 of current transformer CT1 and the pin 3 of operational amplifier also connect simulation ground; The pin 6 of operational amplifier U3 connects the other end of sample resistance RA5 and the input of low-pass filtering resistance R 3; The pin 4 connection-15VA power supplys of operational amplifier U3, the power supply of the pin 7 connection+15VA of operational amplifier U3; The output of low-pass filtering resistance R 3 connects an end of first capacitor C 13 and the output IA of current regulating circuit 1-5; Another termination simulation ground of first capacitor C 13.
CN2010101519169A 2010-04-21 2010-04-21 Electric energy quality monitoring and analyzing system CN101860076B (en)

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CN102169158A (en) * 2011-03-15 2011-08-31 深圳市双合电气股份有限公司 Steady state oscillograph for power system
CN102269801A (en) * 2010-06-07 2011-12-07 宇达电脑(上海)有限公司 Device for monitoring power supply quality of server
CN102539976A (en) * 2012-01-12 2012-07-04 宁夏回族自治区电力公司 Electric multifunctional wave recording analyzer
CN103023739A (en) * 2012-11-07 2013-04-03 国网智能电网研究院 EtherCAT communication management device for dual-core based power electronic equipment
CN104635114A (en) * 2015-03-04 2015-05-20 江苏省电力公司常州供电公司 Positioning system and method for electric energy quality disturbance source
TWI491136B (en) * 2012-06-27 2015-07-01 Ind Tech Res Inst Method and system for monitoring load of electric device
CN105044498A (en) * 2015-07-01 2015-11-11 新疆特变电工自控设备有限公司 Device for capturing transient power quality disturbance
CN105676060A (en) * 2014-11-18 2016-06-15 苏州银蕨电力科技有限公司 Smart grid sensing device
CN106054789A (en) * 2016-08-22 2016-10-26 安徽瑞宏信息科技有限公司 Building project intelligent management system
CN106300657A (en) * 2016-07-22 2017-01-04 安徽亚辉电气自动化有限公司 A kind of control system based on earthing resistance cabinet
CN107171301A (en) * 2017-06-23 2017-09-15 国网江西省电力公司电力科学研究院 A kind of distribution line switch protection fixed value adjusting computing device and method

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102269801A (en) * 2010-06-07 2011-12-07 宇达电脑(上海)有限公司 Device for monitoring power supply quality of server
CN102169158A (en) * 2011-03-15 2011-08-31 深圳市双合电气股份有限公司 Steady state oscillograph for power system
CN102169158B (en) * 2011-03-15 2012-12-26 深圳市双合电气股份有限公司 Steady state oscillograph for power system
CN102539976A (en) * 2012-01-12 2012-07-04 宁夏回族自治区电力公司 Electric multifunctional wave recording analyzer
CN102539976B (en) * 2012-01-12 2016-01-06 宁夏回族自治区电力公司 Electric multifunctional analysis instrument
TWI491136B (en) * 2012-06-27 2015-07-01 Ind Tech Res Inst Method and system for monitoring load of electric device
CN103023739A (en) * 2012-11-07 2013-04-03 国网智能电网研究院 EtherCAT communication management device for dual-core based power electronic equipment
CN103023739B (en) * 2012-11-07 2015-05-13 国网智能电网研究院 EtherCAT communication management device for dual-core based power electronic equipment
CN105676060A (en) * 2014-11-18 2016-06-15 苏州银蕨电力科技有限公司 Smart grid sensing device
CN104635114B (en) * 2015-03-04 2017-11-21 江苏省电力公司常州供电公司 A kind of power quality disturbance alignment system and localization method
CN104635114A (en) * 2015-03-04 2015-05-20 江苏省电力公司常州供电公司 Positioning system and method for electric energy quality disturbance source
CN105044498A (en) * 2015-07-01 2015-11-11 新疆特变电工自控设备有限公司 Device for capturing transient power quality disturbance
CN105044498B (en) * 2015-07-01 2018-04-24 新疆特变电工自控设备有限公司 A kind of catching device of transient power quality disturbance
CN106300657A (en) * 2016-07-22 2017-01-04 安徽亚辉电气自动化有限公司 A kind of control system based on earthing resistance cabinet
CN106054789A (en) * 2016-08-22 2016-10-26 安徽瑞宏信息科技有限公司 Building project intelligent management system
CN107171301A (en) * 2017-06-23 2017-09-15 国网江西省电力公司电力科学研究院 A kind of distribution line switch protection fixed value adjusting computing device and method
CN107171301B (en) * 2017-06-23 2019-03-01 国网江西省电力公司电力科学研究院 A kind of distribution line switch protection fixed value adjusting computing device and method

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