CN101859595B - Latch device and latch method thereof - Google Patents
Latch device and latch method thereof Download PDFInfo
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Abstract
The invention relates to a latch device and a latch method thereof. The latch device comprises a rectifying element, a capacitor, a first latch circuit, a filter circuit, an invalidation circuit and a second latch circuit, wherein, the rectifying element is connected with power wiring; the capacitor is connected with the forward side of the rectifying element; the first latch circuit operates under the capacitor voltage and latches input data according to a first latch signal; the filter circuit outputs a third latch signal and drives a second latch signal which is more delayed than the first latch signal to generate a third latch signal through a low-pass filter; the invalidation circuit invalidates the second latch signal by means of detecting reduced power supply voltage of power wiring; and the second latch circuit operates under the capacitor voltage and latches the output data of the first latch circuit according to the third latch signal.
Description
Technical field
The present invention relates to a kind of under the situation of supply voltage generation drastic change the latch means and the latch method of latch data.
Background technology
Under the situation of power-supply wiring because of the influence that receives outside load (for example the switching of the sudden change of electrical Interference, load, other circuit etc.), the situation of rapid change takes place in the supply voltage by this power-supply wiring power supply sometimes.The supply voltage of this drastic change might drop to below the minimum rated current potential of the resetting voltage, earthing potential and even the circuit that in circuit, reset.Its result usually can destroy the significant data (for example register value etc.) of system.
In order to prevent that the data on the required IC of integrated circuit (below be called " IC ") work are destroyed, and usually are provided with the stand-by circuit to the drastic change of supply voltage.Through stand-by circuit is set, restore data automatically just.For example, use back-up source to use battery, use the comparer and the back-up source of the decline that detects supply voltage to use capacitor as solving countermeasure in the chip as outside chip, solving countermeasure.
In addition,, the storage data of the 1st latch cicuit are kept in the 2nd latch cicuit, just can prevent that the data on the IC are destroyed (for example, with reference to patent documentation 1) through transmission circuit through when the supply of cutting off the electricity supply.
Patent documentation 1: TOHKEMY 2008-78754 communique
But, in above-mentioned prior art, under the moment of the data latching in the IC situation consistent,, also can not correctly carry out latching of data even stand-by circuit is arranged with the moment of the drastic change of supply voltage.Therefore, latch result can be unstable.
Summary of the invention
Therefore, the objective of the invention is to,, also can make stable latch means of latch result and latch method even provide a kind of latch and supply voltage that rapid change takes place simultaneously.
To achieve these goals, the latch means that the present invention is correlated with comprises:
The rectifier cell that is connected with power-supply wiring;
The capacitor that is connected with the forward side of said rectifier cell;
First latch cicuit, its capacitor electrode at said capacitor are depressed work and are latched the input data according to first latch signal;
Export the filtering circuit of the 3rd latch signal, it makes second latch signal that postpones than said first latch signal produce the 3rd latch signal through low-pass filter;
The ineffective treatment circuit, the decline of its supply voltage through detecting said power-supply wiring makes said second latch signal invalid; And
Second latch cicuit, it depresses work at said capacitor electrode, and latchs the output data of said first latch cicuit according to said the 3rd latch signal.
In addition, to achieve these goals, the latch method that the present invention is correlated with comprises:
First step latchs the input data through first latch signal is input to first latch cicuit, and wherein, this first latch cicuit is depressed work at capacitor electrode, and this capacitor is connected to the forward side of the rectifier cell that is connected with power-supply wiring;
Second step makes second latch signal that postpones than said first latch signal produce the 3rd latch signal through low-pass filter;
Third step, the decline of the supply voltage through detecting said power-supply wiring makes said second latch signal invalid; And
The 4th step makes said the 3rd latch signal be input to the output data that second latch cicuit of depressing work at said capacitor electrode latchs said first latch cicuit.
The invention effect
According to the present invention,, also can prevent the unsettled situation of latch result even the drastic change that latchs with supply voltage takes place simultaneously.
Description of drawings
Fig. 1 is the structural drawing of power supply voltage variation countermeasure circuit 100 of the embodiment of the latch means of being correlated with as the present invention.
Fig. 2 is the sequential chart about DIN, WR1, WR2, DOUT.
Fig. 3 is the concrete example of filtering circuit F1.
Fig. 4 is the structural drawing that can be predisposed to 1 or 0 data holding register.
Fig. 5 is embodiments of the invention.
Fig. 6 is the sequential chart of the latch method in the common state of expression power supply voltage variation countermeasure circuit 100.
Fig. 7 is sequential chart expression power supply voltage variation countermeasure circuit 100, the latch method when the drastic change of the rising edge generation supply voltage of latch signal WR1.
Fig. 8 be expression power supply voltage variation countermeasure circuit 100, during rising edge from the rising edge of latch signal WR1 to latch signal WR2 the sequential chart of latch method during the drastic change of generation supply voltage.
Fig. 9 be expression power supply voltage variation countermeasure circuit 100, during rising edge from the rising edge of latch signal WR2 to latch signal WR1 the sequential chart of latch method during the drastic change of generation supply voltage.
Figure 10 be expression power supply voltage variation countermeasure circuit 100, when the drastic change of the rising edge generation supply voltage of latch signal WR2, the sequential chart of the latch method of supply voltage when descending earlier constantly than the rising of latch signal WR2.
Figure 11 be expression power supply voltage variation countermeasure circuit 100, when the drastic change of the rising edge generation supply voltage of latch signal WR2 the sequential chart of the latch method of supply voltage in than the constantly late decline of the rising of latch signal WR2.
Figure 12 is the power backup circuit of the transistor QD with Fig. 1 when replacing with N channel-style transistor.
Figure 13 is the power backup circuit of the transistor QD with Fig. 1 when replacing with diode.
Figure 14 is the power backup circuit of the resistance R 1 with Fig. 1 when replacing with P channel-style transistor.
Figure 15 is the power backup circuit of the resistance R 1 with Fig. 1 when replacing with N channel-style transistor.
Symbol description among the figure:
QD, Q1～Q6 transistor
The D1 latch cicuit
The C1 capacitor
R1, R2 resistive element
N1 AND circuit
The F1 filtering circuit
I1, I2 negater circuit
Embodiment
Below, the structure and the function thereof of power supply voltage variation countermeasure circuit of the embodiment of the latch means of being correlated with as the present invention is described.Power supply voltage variation countermeasure circuit is the circuit of the data that are used for keeping in circuit in the protection of the drastic change of supply voltage, is formed on the IC chip.Even if the drastic change of generation supply voltage (for example in latching constantly; The change time: a few μ second～tens μ second, falling quantity of voltages: below the resetting voltage of circuit or below the ground voltage), power supply voltage variation countermeasure circuit also can be protected the data that in circuit, keep.
Fig. 1 is the structural drawing of power supply voltage variation countermeasure circuit 100 of the embodiment of the latch means of being correlated with as the present invention.Power supply voltage variation countermeasure circuit 100 comprises as main structure: transistor QD, capacitor C1, latch cicuit D1, filtering circuit F1, AND circuit N1 and latch cicuit D2.In addition, power supply voltage variation countermeasure circuit 100 also comprises resistive element R1.
The circuit that is made up of Q1, C1, R1 produces to the whole back-up source voltage VDD2 of power supply voltage variation countermeasure circuit.D1 and D2 are respectively the 1st latch cicuit and the 2nd latch cicuit.WR1 is the 1st latch signal to latch cicuit D1, and WR2 is the 2nd latch signal to latch cicuit D2.DIN is the input data, and DOUT is an output data.N1 is the AND circuit that detects the decline of supply voltage VDD.F1 removes the drastic change of noise and supply voltage of latch signal WR2E to the low-pass filter of the influence of latch cicuit D2.
Each structure of power supply voltage variation countermeasure circuit 100 is described in further detail.
Transistor QD is the rectifier cell that is connected with the power-supply wiring that is used to provide supply voltage VDD.Transistor QD shown in Figure 1 is a P channel-style transistor.As concrete example, P passage MOSFET can give an example.The grid of transistor QD is connected with supply voltage VDD with drain electrode, and the source electrode of transistor QD is connected to capacitor C1.The transistor QD that so is arranged between power-supply wiring and the capacitor works as the rectifier cell that with the direction from supply voltage VDD side direction capacitor C1 side is forward.Supply voltage VDD than the high situation of the condenser voltage VDD2 (that is, back-up source voltage VDD2) of capacitor C1 under, owing to the electric current forward flow makes capacitor C1 be recharged.On the contrary, under the supply voltage VDD situation lower than condenser voltage VDD2, transistor QD cuts off electric current flowing from the direction of capacitor C1 side direction supply voltage VDD side.In other words, transistor QD provides voltage to capacitor C1 usually, under the situation that supply voltage descends, capacitor C1 is separated from the decline of supply voltage.
Have again, both can be shown in figure 12, transistor QD shown in Figure 1 is replaced with N channel-style transistor, also can be shown in figure 13, replace with diode.According to this connection of diagram, any element all can play a role as rectifier cell.
Capacitor C1 is the chip inner capacitor that is connected with the forward side of transistor QD, as the power supply use of power supply voltage variation countermeasure circuit 100.The capacity of capacitor C1 can be tens pF.
Latch cicuit D1 keeps the input data DIN from digital units according to the latch signal WR1 in cycle.Latch cicuit D2 keeps from the output data D1OUT of latch cicuit D1 output according to the latch signal WRE2 that produces based on latch signal WR2, and the phase place of this latch signal WR2 is postponed with respect to latch signal WR1.Latch signal WR1, WR2 are the pulse signals with recurrent pulse.And, exported as the output valve DOUT of power supply voltage variation countermeasure circuit 100 from the output data D2OUT of latch cicuit D2 output.
Fig. 2 is the sequential chart of relevant DIN, WR1, WR2, DOUT.Latch signal WR2 has phase delay Td with respect to latch signal WR1.
In Fig. 1, AND circuit N1 works as the testing circuit of the decline that detects supply voltage VDD, and also invalid idle circuit works as making latch signal WR2 simultaneously.AND circuit N1 makes latch signal WR2 invalid during the decline that detects supply voltage VDD.That is, AND circuit N1 makes latch signal WR2 invalid during below the supply voltage VDD setting.From the level signal WR2D of AND circuit N1 output, latch signal WR2 invalid during regardless of the input of latch signal WR2, all be fixed to the L level.AND circuit N1 is in (under the situation that latch signal WR2 is not disabled) under the situation of the decline that does not detect supply voltage VDD, and directly output latch signal WR2 (being that level signal WR2D equals latch signal WR2) of ground remains unchanged.
Filtering circuit F1 is through handling the latch signal WR2E (the 3rd latch signal) that output is produced to the latch signal WR2 through AND circuit N1 with low-pass filter.For the drastic change of evading noise and supply voltage VDD to the influence of latch signal WR2 and use this low-pass filter.
Fig. 3 is the concrete example of filtering circuit F1.Filtering circuit F1 comprises: as the CR wave filter of low-pass filter (circuit that is made up of resistive element R2 and chip inner capacitor C2), make the reverse negater circuit I1 of the output of CR wave filter and make the reverse negater circuit I2 of output of negater circuit I1.The output of filtering circuit F1 output negater circuit I2 is as latch signal WR2E.
In Fig. 1, resistive element R1 is the arresting element of operable time that is used to determine carry out according to the supply voltage of capacitor C1 because of the decline of supply voltage VDD the power supply voltage variation countermeasure circuit 100 of work.Be connected to the resistive element R1 of the forward side of transistor QD, C1 is connected in parallel with capacitor.The electric charge of capacitor C1 is through resistive element R1 discharge.In resistance value through increasing resistive element R1 and the capacity of capacitor C1 at least any one, just can prolong the operable time of power supply voltage variation countermeasure circuit 100.For example,, the power of the common supply voltage VDD of hope keeps as far as possible for a long time under the data conditions after descending, can be according to the time that keeps data, and the resistance value of decision resistive element R1 and the capacity of capacitor C1.For example, can regard the decline of the supply voltage during a few microsecond to tens microseconds as drastic change, the power that common supply voltage is regarded in the decline of the supply voltage that the hundreds of microsecond is above as the decline that causes that descends gets final product.
Have again, both can be shown in figure 14, resistive element R1 shown in Figure 1 is replaced with P channel-style transistor, also can be shown in figure 15, replace with N channel-style transistor.Through illustrated this connection, any element all utilizes the diode between source electrode-drain electrode to work as arresting element.In addition, use transistor, can reduce layout area as the situation of arresting element and the contrast of resistive element.
Fig. 6 is the sequential chart of the latch method under the common state of expression power supply voltage variation countermeasure circuit 100.Under common duty (being supply voltage VDD normal condition), back-up source voltage VDD2 equals from supply voltage VDD, to deduct the voltage after the loss part that is caused by Q1.The latch signal WR1 of latch cicuit D1 receiving cycle exports to latch cicuit D2 to output data D1OUT.Latch cicuit D2 receives the latch signal WR2E based on the cycle of latch signal WR2, latching constantly of latch signal WR2E, exports latched data D1OUT as output data D2OUT (DOUT).Under common duty owing to do not detect the decline of supply voltage VDD, so AND circuit N1 still output latch signal WR2 as output data WR2D.In addition, the pulse width of latch signal WR2E is because through filtering circuit F1, so longer than the pulse width of latch signal WR1.
Under the situation of the drastic change that produces supply voltage, supply voltage VDD is benchmark with the earthing potential, usually drops to 0V or resetting voltage.In the case, transistor QD ends, and back-up source VDD2 separates with supply voltage VDD.Its result, the electric charge of capacitor C1 can not leak to supply voltage VDD side.The capacitor C1 that separates with supply voltage VDD is as the power work of power supply voltage variation countermeasure circuit 100.
The state of the moment of the generation of the drastic change of supply voltage for latch signal can be divided into 4 types.
(1) side by side produces the drastic change (with reference to Fig. 7) of supply voltage VDD with the rising edge of the latch signal WR1 of latch cicuit D1
(2) after the rising of the latch signal WR1 of latch cicuit D1 till the rising of the latch signal WR2 of latch cicuit D2 during, produce the drastic change (with reference to Fig. 8) of supply voltage VDD
(3) side by side produce the drastic change (with reference to Figure 10,11) of supply voltage VDD with the rising edge of the latch signal WR2 of latch cicuit D2
(4) after the rising of the latch signal WR2 of latch cicuit D2 till the rising of the latch signal WR1 of latch cicuit D1 during, produce the drastic change (with reference to Fig. 9) of supply voltage VDD
Below, explain (1)～work of power supply voltage variation countermeasure circuit 100 when (4) each moment, supply voltage VDD change took place.
(1) under the situation (situation of Fig. 7), the data of latch cicuit D1 are not sure of because of input data DIN changes simultaneously.Therefore, can not guarantee the data of latch cicuit D1.But in the case, the latch signal WR2 (WR2E) of latch cicuit D2 is owing to invalid by AND circuit N1, so can not produce later at the drastic change of supply voltage VDD again.Therefore, the stable data of drastic change before the moment that keep supply voltage VDD in latch cicuit D2.
(2) under the situation (situation of Fig. 8), because the latch signal WR2 (WRE2) of latch cicuit D2 is invalid by AND circuit N1, so just can not produce again later at the drastic change of supply voltage VDD.Therefore, in latch cicuit D2, stablize maintenance by the latch signal WRE2 latched data that last time received.
(3) under the situation (Figure 10,11 situation), the data of latch cicuit D1 are in normally.
Shown in figure 10, if because of the delay in the chip, supply voltage VDD descended earlier before the rising constantly of latch signal WR2, then utilized AND circuit N1 to make latch signal WR2 invalid.Can not produce latch signal WR2E thus.Therefore, in latch cicuit D2, stablize maintenance by the latch signal WRE2 latched data that last time received.
On the other hand, shown in figure 11, if being later than the rising of latch signal WR2, supply voltage VDD descends constantly, then till the decline that detects supply voltage VDD, AND circuit N1 directly makes latch signal WR2 pass through.Filtering circuit F1 suppresses or the short pulse below removal hundreds of nanosecond usually.
Therefore, the pulse width of the latch signal WR2 through AND circuit N1 is not if the length that can be removed by filtering circuit F1 then produces latch signal WR2E.Thus, in latch cicuit D2, stably keep by the latch signal WRE2 latched data that last time receives.On the other hand, if the pulse width of the latch signal WR2 through AND circuit N1 is the length that can not be removed by filtering circuit F1, then this latch signal WR2 is counted as useful signal, is received by latch cicuit D2 as latch signal WR2E.Its result, the output data D1OUT that exports from latch cicuit D1 is transferred to latch cicuit D2.That is, latch cicuit D2 at the edge of the latch signal WR2E that is counted as effective signal, can stablize and latch output data D1OUT.Owing to do not receive the influence of the drastic change of supply voltage VDD, in latch cicuit D2, transmit normal data (being output data D1OUT).
Have again, can for example can be decided by the pulse width of the latch signal WR2 of filtering circuit F1 removal through the constant of adjusting CR circuit shown in Figure 3.
(4) under the situation (situation of Fig. 9), latch cicuit D2 has obtained normal data.And latch cicuit D2 before supply voltage VDD returns to normal value, can not receive latch signal once more.Therefore, in latch cicuit D2, stably keep by the latch signal WRE2 institute latched data that last time receives.
Behind the drastic change that supply voltage VDD takes place, supply voltage VDD rises to conventional value at leisure.During the last look that can not prepare to import data DIN, output data DOUT exports from power supply voltage variation countermeasure circuit 100 with extremely short delay.The data of output are the data that keep during the drastic change of supply voltage VDD during this period, are the data before the drastic change of supply voltage VDD takes place.
Have again; At the drastic change that is not supply voltage VDD; Under the situation of (for example the power-off of primary power etc.), power supply voltage variation countermeasure circuit 100 is at the constantly initial retaining data during of stopping power supply from supply voltage VDD but original supply voltage VDD stops power supply.But, because the electric charge of capacitor C1 is through resistive element R1 discharge, so the data that finally kept by power supply voltage variation countermeasure road 100 will disappear.So, through the structure that can be discharged by arresting elements such as resistive element R1 is set, after the stopping power supply of original supply voltage once more during energized, the end value (i.e. output by mistake) before the power supply that can prevent to export this supply voltage stops.
Therefore; According to above-mentioned explanation; Even data latching is constantly under (latch signal is for rising constantly) situation consistent with the moment of supply voltage drastic change; Because the phase place of latch signal that is input to the 2nd latch cicuit is than the latch signal delay that is input to the 1st latch cicuit, so the disappearance of the data that can avoid in latch cicuit, keeping.
That is, when latching of latch cicuit D1 constantly the drastic change of supply voltage takes place,,, do not change so keep the data in the latch cicuit D2 owing to do not produce the latch signal of latch cicuit D2.
In addition, when latching of latch cicuit D2 constantly the drastic change of supply voltage took place, if with respect to the latch signal of latch cicuit D2, the pulse width of this latch signal was short, then by the whole filterings of filtering circuit.If the pulse width of this latch signal is long, then owing to not eliminated and kept, so the normal data of latch cicuit D1 are transferred to latch cicuit D2 according to the latch signal through filtering circuit by filtering circuit.
Have again, can must be also longer than the maximal value that is assumed to be the time that supply voltage changes sharp with the delay width setup between 2 latch signals.
But, set the initial value of the register in latch cicuit D1, the D2 through adjusting the size of the chip section of reverser back-to-back.Constitute 2 a plurality of transistorized grid width of reverser and the ratio of grid length are not balances between these a plurality of transistors back-to-back through making; And they are set at imbalance, the initial value of the register in the time of making the power connection of IC thus must be decided to be setting (1 or 0).
Fig. 4 is the structural drawing of chip section of the register of latch cicuit.As follows, can preset the initial value of each register.Transistor Q1, Q2, Q3, Q4 form 2 reversers back-to-back that are used for the positive feedback of data maintenance.Usually, in order to form the structure of balance, equally design the size of Q1 and Q3 and the size of Q2 and Q4.Under the situation of this balanced structure, the A, the value that B is ordered of the input and output value of reverser get initial value at random back-to-back as 2.
On the other hand, in the present invention, the grid size of transistor Q1, Q2, Q3, Q4 is set to imbalance between each transistor.For example, hope the initial value of lead-out terminal QO is predisposed to 1 time marquis, can the initial value of lead-out terminal QO be predisposed to 1 through any method in 4 establishing methods as follows.
[establishing method 1]
Set the grid width of transistor Q4 and the ratio of grid length greater than the grid width of Q2 and the ratio of grid length, set the size of transistor Q1 and Q3 equal.Just can make transistor Q4 be easy to conducting thus.
[establishing method 2]
Set the grid width of transistor Q3 and the ratio of grid length less than the grid width of Q1 and the ratio of grid length, set the size of transistor Q2 and Q4 equal.Just can make transistor Q1 be easy to conducting thus.
[establishing method 3]
Set the grid width of transistor Q4 and the ratio of grid length greater than the grid width of Q2 and the ratio of grid length, set the grid width of transistor Q3 and the ratio of grid length less than the grid width of Q1 and the ratio of grid length.Just can make transistor Q1 and Q4 be easy to conducting thus.
Through these any establishing methods, the balance of the size of breaking crystal pipe is tending towards than the lower direction of B point the A point.And, through the action of positive feedback, because the value that will put B is converged in 0, the value that will put A is converged in 1, so can the initial value of lead-out terminal QO be predisposed to 1.Likewise consider, opposite through the magnitude relationship that makes the ratio shown in the above-mentioned establishing method, just can the initial value of lead-out terminal QO be predisposed to 0.
Embodiment
Fig. 5 is a concrete example of having used chip of the present invention.The AD transducer (ADC) of low speed sampling produces the data DIN to power supply voltage variation countermeasure circuit periodically by the digital control unit control as the Digital Logic device.Latch signal WR1 and WR2 are produced by the Digital Logic device of following sequential.Under the situation of ADC by the rate output data DIN of a sampling/ms,, then need 1ms in order to make end value revert to output DOUT if there is not power supply voltage variation countermeasure circuit.But, just can make end value revert to output DOUT with tens μ s according to the present invention.
Hereinbefore, though specified the preferred embodiment of the invention, the invention is not restricted to the embodiments described, do not depart from the scope of the present invention and in the above embodiments, can append various distortion and replacement.
For example, can mutual alternative Fig. 1, each component parts in 12～15.
Claims (12)
1. latch means comprises:
The rectifier cell that is connected with power-supply wiring;
The capacitor that is connected with the forward side of said rectifier cell;
First latch cicuit, its capacitor electrode at said capacitor are depressed work and are latched the input data according to first latch signal;
Export the filtering circuit of the 3rd latch signal, it makes second latch signal that postpones than said first latch signal produce the 3rd latch signal through low-pass filter;
The AND circuit, the decline of its supply voltage through detecting said power-supply wiring makes said second latch signal invalid; And
Second latch cicuit, it depresses work at said capacitor electrode, and latchs the output data of said first latch cicuit according to said the 3rd latch signal.
2. latch means according to claim 1 is characterized in that,
Said filtering circuit comprises: as the CR wave filter of said low-pass filter, make the first reverse negater circuit of output of CR wave filter, and the second reverse negater circuit of output that makes first negater circuit,
This latch means is exported said the 3rd latch signal according to the output of said second negater circuit.
3. latch means according to claim 1 and 2 is characterized in that,
In the forward side of said rectifier cell, possesses the arresting element of the charge discharge that makes said capacitor.
4. latch means according to claim 3 is characterized in that,
Said arresting element and said capacitor are connected in parallel.
5. latch means according to claim 4 is characterized in that,
Said arresting element is a resistive element.
6. latch means according to claim 4 is characterized in that,
Said arresting element is N channel transistor or P channel transistor.
7. latch means according to claim 1 and 2 is characterized in that,
When said supply voltage is higher than said condenser voltage, make just always said capacitor being charged of the said rectifier cell of current direction, when said supply voltage forced down than said capacitor electrode, blocking flow to the electric current of said rectifier cell.
8. latch means according to claim 7 is characterized in that,
Said rectifier cell is N channel transistor or P channel transistor.
9. latch means according to claim 7 is characterized in that,
Said rectifier cell is a diode.
10. latch means according to claim 1 and 2 is characterized in that,
Said first latch cicuit and said second latch cicuit comprise the back-to-back reverser that is made up of a plurality of transistors;
Set said a plurality of transistorized grid size lopsidedly.
11. latch means according to claim 1 and 2 is characterized in that,
The latch signal output circuit that also comprises said first latch signal of output and said second latch signal.
12. a latch method comprises:
First step latchs the input data through first latch signal is input to first latch cicuit, and wherein, this first latch cicuit is depressed work at capacitor electrode, and this capacitor is connected to the forward side of the rectifier cell that is connected with power-supply wiring;
Second step makes second latch signal that postpones than said first latch signal produce the 3rd latch signal through low-pass filter;
Third step, the decline of the supply voltage through detecting said power-supply wiring makes said second latch signal invalid; And
The 4th step makes said the 3rd latch signal be input to the output data that second latch cicuit of depressing work at said capacitor electrode latchs said first latch cicuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101333843A CN101859595B (en) | 2009-04-07 | 2009-04-07 | Latch device and latch method thereof |
| JP2009119835A JP5262981B2 (en) | 2009-04-07 | 2009-05-18 | Latch device and latch method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101333843A CN101859595B (en) | 2009-04-07 | 2009-04-07 | Latch device and latch method thereof |
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| CN101859595A CN101859595A (en) | 2010-10-13 |
| CN101859595B true CN101859595B (en) | 2012-04-04 |
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| CN2009101333843A Expired - Fee Related CN101859595B (en) | 2009-04-07 | 2009-04-07 | Latch device and latch method thereof |
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|---|---|---|---|---|
| CN1360396A (en) * | 2000-12-21 | 2002-07-24 | 日本电气株式会社 | Clock and data restoring circuit and its clock control method |
| CN1816967A (en) * | 2003-09-19 | 2006-08-09 | 印芬龙科技股份有限公司 | Master latch circuit with signal level displacement for a dynamic flip-flop |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0350935U (en) * | 1989-09-22 | 1991-05-17 | ||
| JPH066185A (en) * | 1992-06-16 | 1994-01-14 | Ricoh Co Ltd | Circuit for not propagating meta-stable state |
| JP3429937B2 (en) * | 1996-01-12 | 2003-07-28 | 三菱電機株式会社 | Semiconductor device |
| JP3896957B2 (en) * | 2002-11-28 | 2007-03-22 | 株式会社デンソー | Level shift circuit |
| JP4656040B2 (en) * | 2006-10-19 | 2011-03-23 | 株式会社デンソー | Electronic circuit |
-
2009
- 2009-04-07 CN CN2009101333843A patent/CN101859595B/en not_active Expired - Fee Related
- 2009-05-18 JP JP2009119835A patent/JP5262981B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1360396A (en) * | 2000-12-21 | 2002-07-24 | 日本电气株式会社 | Clock and data restoring circuit and its clock control method |
| CN1816967A (en) * | 2003-09-19 | 2006-08-09 | 印芬龙科技股份有限公司 | Master latch circuit with signal level displacement for a dynamic flip-flop |
Also Published As
| Publication number | Publication date |
|---|---|
| JP5262981B2 (en) | 2013-08-14 |
| CN101859595A (en) | 2010-10-13 |
| JP2010246074A (en) | 2010-10-28 |
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