JP4656040B2 - Electronic circuit - Google Patents

Description

  The present invention relates to an electronic circuit including a control circuit that operates in synchronization with a clock signal.

In electronic circuits, as a measure to protect data or prevent malfunctions in the event of a momentary power interruption, a capacitor with a relatively large capacity is prepared, and the voltage accumulated by the charge accumulated in the capacitor is reduced. It is common practice to pass the period when the power supply is cut off by delaying the drop. However, when a large-capacitance capacitor is used, there is a problem that the element size is large and an arrangement space is required and the cost is increased.
Further, in Patent Document 1, in order to prevent destruction of data stored in the EEPROM, when a drop in the power supply voltage is detected, a chip select signal output from the CPU to the EEPROM is blocked to access the EEPROM. Disallowed technology is disclosed.
JP-A-8-249244

However, the technique disclosed in Patent Document 1 can be applied only to data protection of a nonvolatile memory accessed from a CPU, such as an EEPROM, and controls a sequencer composed of the CPU itself and hardware logic. In order to prevent malfunction of the circuit, a large-capacity capacitor is still necessary.
The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic circuit capable of preventing malfunction of a control circuit when a power supply interruption occurs without using a large-capacitance capacitor. It is in.

  According to the electronic circuit of the first aspect, the power supply for operation of the control circuit is supplied from the capacitor charged from the main power supply via the diode. The main power is supplied to the clock signal output circuit and the clock signal output circuit is operated by shifting the level of the clock signal by the clock level shift circuit. Then, when the voltage drop detection circuit detects that the main power supply voltage has fallen below the detection threshold set to be lower than the operation power supply voltage, the clock supply stop circuit stops the supply of the clock signal to the control circuit. That is, when the main power supply voltage is temporarily lowered, the logic operation based on the clock signal is stopped, and the power consumption by the control circuit becomes small. Therefore, it is possible to back up the operating power supply during the period when the main power supply voltage is lowered, even with a relatively small capacitor.

According to the electronic circuit of the second aspect, since the clock level shift circuit and the clock supply stop circuit are integrally formed, the functions of both can be integrated to reduce the size of the entire circuit.
According to another aspect of the electronic circuit of the present invention, the reset circuit outputs a reset signal to the control circuit when detecting that the power supply voltage for operation of the control circuit is lower than the reset threshold set below the detection threshold. To do. Therefore, if the main power supply voltage is lowered for a relatively long period of time, the charging charge of the capacitor is consumed, the power supply voltage for operation of the control circuit is lowered, and the internal state of the control circuit cannot be guaranteed. The control circuit can be reset.

  According to the electronic circuit of claim 4, when there is a peripheral circuit that inputs / outputs a signal to / from the control circuit when the main power is supplied, the signal level shift circuit transmits the signal transferred between the two. Since the level is shifted, signal input / output can be performed without any problem.

  According to the electronic circuit of the fifth aspect, the signal level shift circuit fixes the signal level output to the control circuit side regardless of the corresponding input signal level when the voltage drop detection circuit detects the voltage drop. The signal level output to the peripheral circuit side is fixed according to the corresponding input signal level. Therefore, the input / output signal level during the period when the main power supply voltage is lowered and the operation of the control circuit is stopped can be appropriately fixed by the signal level shift circuit.

  According to the electronic circuit of claim 6, when the control circuit is a CPU, the operation power supplied by the capacitor is also supplied to the memory circuit that is directly accessed by the CPU, so that even when the memory circuit is volatile, The stored contents can be backed up.

  According to the electronic circuit of the seventh aspect, the control circuit is configured to perform control related to the vehicle. That is, an electronic circuit mounted on a vehicle must operate in a very noisy environment, and the voltage of the battery often fluctuates due to the noise. Therefore, the present invention is extremely effective when applied to a control circuit mounted on a vehicle.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing a configuration of a control system centering on a sequencer. The power supply VDD is directly supplied to the clock generation circuit (clock signal output circuit) 1, level shift circuits 2 and 3, logic circuit (peripheral circuit) 4, and low voltage detection circuit (voltage drop detection circuit) 5. The power supply VDD is connected to the ground via a series circuit of a diode 6 and a capacitor 7. The cathode side of the diode 6 is a sequencer (control circuit) 8 and level shift circuits 2 and 3 as a supply terminal for the power supply VDDH. It is connected to the.

  The sequencer 8 is configured by hardware logic, and the clock signal CLK generated by the clock generation circuit 1 is supplied via the level shift circuit 2. The sequencer 8 operates in clock synchronization and outputs a control signal corresponding to a predetermined control sequence. The logic circuit 4 is an object to be controlled by the sequencer 8, and signals and the like input / output between them are transferred to each other via the bidirectional level shift circuit 3.

  The low voltage detection circuit 5 includes a band gap regulator (BGR) 9, a series circuit of resistance elements 10 and 11, and a comparator 12, and detects a voltage drop of the power supply VDD. That is, the common connection point of the series circuit is connected to the (+) terminal of the comparator 12, and the output terminal of the BGR 9 is connected to the (-) terminal. Then, the comparator 12 changes the output signal level from high to low when the voltage of the power supply VDD falls below the threshold value VPOR1 and the divided potential falls below the reference voltage Vref generated by the BGR9.

That is, the threshold voltage VPOR1 is expressed as follows when the resistance values of the resistance elements 10 and 11 are R3 and R4.
VPOR1 = Vref × (R3 + R4) / R4
The output signal of the comparator 12 is given to the level shift circuits 2 and 3 as an enable signal EN (high active). When the enable signal EN becomes low level, the output of the clock signal CLK to the sequencer 8, the sequencer 8 and the logic Input / output of signals to / from the circuit 4 is stopped.

  The reset circuit 13 is configured by connecting a series circuit of a resistance element 14 and an N-channel MOSFET 15 and a series circuit of a P-channel MOSFET 16 and a resistance element 17 in parallel between a power supply VDDH and the ground. The gates of the FETs 15 and 16 are commonly connected to the drain of the FET 15, and the source of the FET 16 is connected to the reset terminal (high active) of the sequencer 8 via the NOT gate 18.

Therefore, if the voltage of the power supply VDDH is equal to or higher than VPOR2 = 2V, which is the sum of the threshold voltages Vtn and Vtp of the two FETs 15 and 16, the FETs 15 and 16 are both ON, and the input terminal of the NOT gate 18 A high level (= VDDH) is given. When the voltage of the power supply VDDH becomes less than 2V, both the FETs 15 and 16 are turned OFF, the input terminal (reset signal RESB) of the NOT gate 18 is set to the low level, and the sequencer 8 is reset.
Here, for example, assuming that VDD = 5.0V,
VDDH = 4.3V, VPOR1 = 4.0V, VPOR2 = 2.0V
Is set to the level.

  FIG. 2 shows an internal configuration of the clock level shift circuit (clock supply stop circuit) 2. The level shift circuit 2 includes NOT gates 19 to 21 and a NAND gate 22. The input side which is the high potential (VDD) side is configured by connecting NOT gates 19 and 20 in series, and a power supply VDD is supplied to them. The output side which is the low potential side is configured by connecting a NAND gate 22 and a NOT gate 21 in series, and a power supply VDDH is supplied to them. The output terminal of the NOT gate 20 is connected to one input terminal of the NAND gate 22, and the enable signal EN is given to the other input terminal of the NAND gate 22 from the low voltage detection circuit 5.

  That is, if the enable signal EN is high, when a high-level signal on the high potential side is input to the input terminal of the NOT gate 19, a high-level signal on the low potential side is output from the output terminal of the NOT gate 21. When the enable signal EN becomes low level, the output terminal of the NOT gate 21 maintains low level regardless of the signal level on the high potential side.

FIG. 3 shows the internal configuration of the bidirectional signal level shift circuit 3. The signal level shift circuit 3 converts a signal level input / output between the sequencer 8 and the logic circuit 4. That is, the level shift from the low potential side to the high potential side is performed in the high potential conversion unit 3H in the direction of the sequencer 8 → logic circuit 4, and in the low potential conversion unit 3L in the direction of the sequencer 8 ← logic circuit 4. A level shift from the high potential side to the low potential side is performed.
Therefore, the low potential conversion unit 3L is configured by the NOT gates 23 to 25 and the NAND gate 26 with the same connection as the level shift circuit 2. On the other hand, in the high potential conversion unit 3H, the low potential input side is configured by connecting NOT gates 27 and 28 in series, and the high potential output side is configured by four FETs 29 to 32 and NOT gates 33 and 34.

  That is, a series circuit of a P-channel MOSFET 29 and an N-channel MOSFET 30 and a series circuit of a P-channel MOSFET 31 and an N-channel MOSFET 32 are connected in parallel between the power supply VDD and the ground. It is connected to the input terminal of the NOT gate 33. The gate of the FET 31 is connected to the drain of the FET 29, the gate of the FET 30 is connected to the output terminal of the NOT gate 28, and the gate of the FET 32 is connected to the output terminal of the NOT gate 27. The NOT gates 33 and 34 are connected in series, and a power supply VDD is supplied to them.

When the input signal of the high potential converter 3H becomes high level (VDDH), the FETs 30 and 31 are turned on, the FETs 32 and 29 are turned off, and the output terminal of the NOT gate 34 becomes high level (VDD). When the input signal of the high potential converter 3H is at low level, the ON / OFF relationship of the FETs 29 to 32 is reversed, and the output terminal of the NOT gate 34 is at low level.
In FIG. 3, only one high potential conversion unit 3H and one low potential conversion unit 3L are shown for the sake of illustration, but in actuality, mutual input / output is performed between the sequencer 8 and the logic circuit 4. One or more of them are arranged according to the number of signals.

  Next, the operation of this embodiment will be described with reference to FIG. FIG. 4 is a timing chart showing the waveform change of each part when the voltage of the power supply VDD decreases. As shown in FIG. 4A, when the voltage of the main power supply VDD is normal (period A), both the enable signal EN and the reset signal RESB are at a high level (see (c) and (b)). A clock signal CLK is supplied to the sequencer 8 (see (e)), and signal input / output between the sequencer 8 and the logic circuit 4 is also performed.

From this state, when the voltage of the main power supply VDD decreases for some reason and falls below the level of the threshold VPOR1, the low voltage detection circuit 5 changes the enable signal EN to the low level (period B). Then, the supply of the clock signal CLK is stopped by the level shift circuit 2 (the output level is fixed to low). Signal input / output between the sequencer 8 and the logic circuit 4 is also stopped by the signal level shift circuit 3. At this time, on the low potential conversion unit 3L side, the output level of the NOT gate 24 becomes indefinite, but the output level for the sequencer 8 is fixed to low.
At this time, the power supply VDDH held by the capacitor 7 is supplied to the sequencer 8, and the power consumption of the sequencer 8 is greatly reduced by stopping the supply of the clock signal CLK. Accordingly, the level of the power supply VDDH becomes lower than that of the main power supply VDD, and the internal state of the sequencer 8 is maintained.

  When the level of the main power supply VDD returns to the normal state once from the ground GND and the supply of the clock signal CLK is resumed, the sequencer 8 continues the control from the held internal state (period C). Further, when the level of the main power supply VDD decreases again, the supply of the clock signal CLK is similarly stopped (period D). When the period continues for a longer period, the charge of the capacitor 7 is gradually consumed, and the level of the power supply VDDH gradually decreases. When the level of the power supply VDDH falls below VPOR2, the reset circuit 13 sets the reset signal RESB to a low level (period E). In this case, since the internal state of the sequencer 8 is not guaranteed, the sequencer 8 is reset.

  Note that the time until the level of the power supply VDDH reaches the threshold value VPOR2 is determined by the capacitance of the capacitor 7 and the power consumption of the reset circuit 13. After that, when the level of the main power supply VDD returns to the normal state, the reset of the sequencer 8 is released and the supply of the clock signal CLK is resumed, so that the sequencer 8 executes the control sequence from the reset state (period F ).

  As described above, according to the present embodiment, the power supply for operating the sequencer 8 is supplied from the main power supply VDD via the diode 6 and the capacitor 7 is charged, and the clock generation circuit 1 is supplied with the main power supply VDD. The level shift circuit 2 shifts the level of the clock signal and outputs it to the sequencer 8. When the low voltage detection circuit 5 detects that the main power supply voltage has dropped below the detection threshold VPOR1, the level shift circuit 2 stops supplying the clock signal to the sequencer 8. Therefore, it is possible to back up the operating power supply during the period when the main power supply voltage is lowered, even if the capacitor 7 has a relatively small capacity.

  Here, when the power source is backed up only by the charge of the capacitor as in the prior art, the capacitance of the capacitor needs to be on the order of μF. Such a large-capacity capacitor cannot be formed as an element on a semiconductor substrate, and a discrete element must be externally attached to the IC. On the other hand, according to the configuration of the present embodiment, the capacitor 7 can be backed up even if the capacitance is on the order of several tens of pF. Therefore, the capacitor 7 is also formed on the semiconductor substrate and is integrally configured as an IC. Can do.

The reset circuit 13 outputs a reset signal to the sequencer 8 when detecting that the operation power supply voltage of the sequencer 8 is lower than the reset threshold value VPOR2 set to be less than the detection threshold value VPOR1. The sequencer 8 can be reset when the internal state cannot be guaranteed.
Since the level shift circuit 3 shifts the level of the signal transferred between the sequencer 8 and the logic circuit 4, it is possible to input / output signals between the two without any problem. Further, when the low voltage detection circuit 5 detects a voltage drop, the level shift circuit 3 fixes the signal level output to the sequencer 8 side regardless of the corresponding input signal level and outputs it to the logic circuit 4 side. The signal level is fixed according to the corresponding input signal level. Therefore, the level shift circuit 3 can appropriately fix the input / output signal state during the period when the main power supply voltage is lowered and the operation of the sequencer 8 is stopped.

(Second embodiment)
FIG. 5 shows a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. The control system of the second embodiment is a case where a CPU (control circuit) 41 is used in place of the sequencer 8 and is applied to a microcomputer mainly composed of the CPU 41. The clock signal CLK output from the level shift circuit 2 is applied to the clock input terminal of the CPU 41, and the reset signal RSTB output from the reset circuit 13 is applied to the reset terminal of the CPU 41.

  Further, a ROM (memory circuit) 42 storing a control program and a RAM (memory circuit) 43 used as a work area are connected to the CPU 41 via an address bus and a data bus. Similar to the CPU 41, the power supply VDDH is supplied. An I / O unit (peripheral circuit) 44 is arranged in place of the logic circuit 4 of the first embodiment, and the A / D converter (ADC) 45 is connected to the level shift circuit 3 according to the input / output configuration with the CPU 41. It is connected to the CPU 41 through a signal level shift circuit 46 configured similarly. A power supply VDD is supplied to the A / D converter (peripheral circuit) 45.

  The control system is configured as an ECU (Electronic Control Unit) for vehicle control, for example. That is, the CPU 41 controls a control target (such as an engine or a motor) via the I / O unit 44 according to a control command or the like given from the outside, for example, another ECU via a communication circuit (not shown) The data read from the / D converter 45 is transmitted to the outside.

  According to the second embodiment configured as described above, when the control circuit is the CPU 41, the operation power supplied from the capacitor 7 is also supplied to the ROM 42 and the RAM 43 that are directly accessed by the CPU 41. Can also be backed up. The vehicle control ECU operates in an environment in which the battery power supply VDD is easily affected by noise and the possibility of instantaneous interruption is relatively high. Therefore, the present invention can be applied effectively.

(Third embodiment)
FIG. 6 shows a third embodiment of the present invention and is a view corresponding to FIG. In the third embodiment, a diode-connected N-channel MOSFET 47 is used instead of the diode 6. That is, the drain of the FET 47 is connected to the power supply VDD side, and the source is connected to the capacitor 7 side. The gate of the FET 47 is connected to its own drain, and the back gate is connected to the ground.
According to the third embodiment configured as described above, the same effects as in the first and second embodiments can be obtained.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
The peripheral circuit in the second embodiment may be a communication circuit or the like. Further, when a gate array or a DMA controller is connected to the CPU 41, these may also be handled as a control circuit, and the power supply for operation may be supplied from the capacitor 7 in the same manner as the CPU 41 to stop the clock supply.
In addition, when there are a plurality of control circuits as described above, a plurality of capacitors may be provided in order to appropriately back up the operation power supply.

1 is a block diagram showing a configuration of a control system centering on a sequencer according to a first embodiment of the present invention. The figure which shows the internal configuration of the clock level shift circuit Diagram showing the internal configuration of the signal level shift circuit Timing chart of circuit operation according to voltage change of power supply VDD FIG. 1 equivalent view showing a second embodiment of the present invention. FIG. 1 is a partial equivalent diagram of FIG. 1 showing a third embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is a clock generation circuit (clock signal output circuit), 2 is a clock level shift circuit (clock supply stop circuit), 3 is a signal level shift circuit, 4 is a logic circuit (peripheral circuit), and 5 is a low voltage detection circuit. (Voltage drop detection circuit), 6 is a diode, 7 is a capacitor, 8 is a sequencer (control circuit), 13 is a reset circuit, 41 is a CPU (control circuit), 42 is a ROM (memory circuit), 43 is a RAM (memory circuit) , 44 is an I / O unit (peripheral circuit), 45 is an A / D converter (peripheral circuit), 46 is a signal level shift circuit, and 47 is an N-channel MOSFET (diode).

Claims (7)

In an electronic circuit configured with a control circuit that operates in synchronization with a clock signal,
A capacitor that is charged by being connected to a main power source via a diode, and whose charging voltage is supplied as an operation power source of the control circuit;
A clock signal output circuit which operates by being supplied with the main power;
A clock level shift circuit for shifting the level of the clock signal supplied from the clock signal output circuit to the control circuit;
A voltage drop detection circuit for detecting that the main power supply voltage has fallen below a detection threshold set to be lower than the operation power supply voltage;
An electronic circuit comprising: a clock supply stop circuit that stops supply of a clock signal to the control circuit when the voltage drop detection circuit detects a voltage drop.   2. The electronic circuit according to claim 1, wherein the clock level shift circuit and the clock supply stop circuit are integrated.   3. A reset circuit that outputs a reset signal to the control circuit when detecting that the operating power supply voltage has dropped below a reset threshold set below the detection threshold. Electronic circuit.   4. A signal level shift circuit that shifts a level of a signal transferred between the control circuit and a peripheral circuit that operates by being supplied with the main power supply. Electronic circuit.   When the voltage drop detection circuit detects a voltage drop, the signal level shift circuit fixes the signal level output to the control circuit side regardless of the corresponding input signal level and outputs it to the peripheral circuit side. 5. The electronic circuit according to claim 4, wherein the signal level is fixed in accordance with a corresponding input signal level.   6. The electronic circuit according to claim 1, wherein when the control circuit is a CPU, the power supply for operation is also supplied to a memory circuit that is directly accessed by the CPU.   The electronic circuit according to claim 1, wherein the electronic circuit is mounted on a vehicle, and the control circuit is configured to perform control related to the vehicle.

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