CN101853824A

CN101853824A - Array substrate and manufacturing method thereof

Info

Publication number: CN101853824A
Application number: CN200910134072A
Authority: CN
Inventors: 叶财记; 谢欣媛; 黄婷熏; 彭文辉
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2009-03-31
Filing date: 2009-03-31
Publication date: 2010-10-06

Abstract

The invention discloses an array substrate and a manufacturing method thereof. The array substrate comprises a substrate, a first circuit, a second circuit, a patterned protective layer and a conductive layer, wherein the first circuit is arranged on the substrate; the second circuit is arranged on the substrate in parallel with the first circuit; the patterned protective layer is arranged on the substrate, covers the first and second circuits and has an opening partially exposing the first circuit; and the conductive layer is arranged in the opening, is in contact with the first circuit, is extended in a direction vertical to the second circuit and covers the second circuit. The array substrate and the manufacturing method thereof have the advantages of avoiding conductive particles penetrating adjacent wires to cause short circuit, and simultaneously increasing offset in a pressing process.

Description

Array base palte and manufacture method thereof

Technical field

The present invention is about a kind of array base palte and manufacture method thereof, particularly relevant for a kind of array base palte that increases the chip pressing area.

Background technology

At present, it has been normality as man-machine communication interface that mobile phone and general electronic products are carried TFT-LCD, and demand also changes more amusements and animation Presentation Function into from the ground literal Presentation Function in past, so the requirement of resolution is also just more and more higher.Pursuing under resolution and the cost consideration, areolar (fine pitch) chip (IC) is also just increasingly important, and for the chip at small size holds more function, (chip on glass, COG) required precision of processing procedure is more and more higher to glass flip chip.The tradition board can't satisfy the demands gradually, sees also Fig. 1, and Fig. 1 on array base palte 10, is typically provided with many circuits 11, and on each circuit 11 pad 12 is set for the schematic diagram of existing array base palte 10.Continuation is referring to Fig. 2 A and Fig. 2 B, and Fig. 2 A is the pad 12 and IC piece 13 contrapositions schematic diagram just often among Fig. 1, and Fig. 2 B be the schematic diagram of the pad 12 among Fig. 1 when being offset with 13 contrapositions of IC piece.When contraposition was offset, IC piece 13 was pressed onto adjacent lines, because circuit 11 top layers matcoveredn only, IC piece 13 might be pressed and be worn protective layer and cause line short.Simultaneously, pad 12 areas are less, may cause pressing area deficiency because of the skew in the COG processing procedure, thereby cause display abnormality because of impedance is excessive.In addition, if because of considering that being offset the length that increases IC piece 13 guarantees that the pressing area satisfies process requirement, then makes the width of IC reduce.

Summary of the invention

At above-mentioned technical problem, the present invention covers contiguous cabling by pad is extended to, and effective pressing area is strengthened.

Array base palte provided by the invention comprises substrate, first circuit, second circuit, patterning protective layer and conductive layer.First circuit is arranged on the substrate.Second circuit is arranged on the substrate in the mode parallel with first circuit.The patterning protective layer is arranged on the substrate and covers first circuit and second circuit, and have opening expose the part this first circuit.Conductive layer is arranged in the opening and contacts with first circuit, and this conductive layer extends on the direction vertical with second circuit and covers this second circuit.

According to array base palte of the present invention, conductive layer is made by tin indium oxide.The patterning protective layer comprises the ground floor and the second layer, and this ground floor has the P-SiNx component, and this second layer has the Ge-SiNx component.

According to array base palte of the present invention, has spacer region between first circuit and second circuit.Further, conductive layer is crossed over first circuit, spacer region and second circuit.

The present invention also provides a kind of manufacture method of array base palte, comprises following steps.Substrate is provided.Form first circuit parallel to each other and second circuit on this substrate.Form the patterning protective layer on this substrate and cover this first circuit and this second circuit, wherein this patterning protective layer has opening and exposes this first circuit of part.Form patterned conductive layer in this opening, wherein this conductive layer extends on the direction vertical with this second circuit and covers this second circuit.

According to manufacture method of the present invention, in the step that forms patterned conductive layer, the coverage rate of this conductive layer is crossed over this first circuit and this second circuit.

By the present invention, make pressure programming wider range, the problem of tolerable board precision deficiency more makes IC programmable littler.

Description of drawings

Fig. 1 is the schematic diagram of existing array base palte;

Fig. 2 A is pad and the IC piece contraposition schematic diagram just often among Fig. 1;

Schematic diagram when Fig. 2 B is pad among Fig. 1 and IC piece contraposition skew;

Fig. 3 is the schematic diagram of the array base palte of one embodiment of the invention;

Fig. 4 is the schematic diagram in the A-A cross section among Fig. 3;

Schematic diagram when Fig. 5 is the pad of array base palte of one embodiment of the invention and the contraposition of IC piece;

Fig. 6 is the schematic diagram in the B-B cross section among Fig. 5.

Embodiment

For making purpose of the present invention, structure, feature and function thereof there are further understanding, cooperate embodiment to be described in detail as follows now.

See also Fig. 3 and Fig. 4, Fig. 3 is the schematic diagram of the array base palte 30 of one embodiment of the invention, and Fig. 4 is the schematic diagram in the A-A cross section among Fig. 3.Array base palte 30 comprises substrate 39, first circuit 31, second circuit 32, patterning protective layer 33 and conductive layer 34.First circuit 31 is arranged on the substrate 39.Second circuit 32 is arranged on the substrate 39 in the mode parallel with first circuit 31.Patterning protective layer 33 is arranged on the substrate 39 and covers first circuit 31 and second circuit 32, and have at least one opening 333 expose the part this first circuit 31.Conductive layer 34 is arranged in the opening 333 and with first circuit 31 and contact, the extension and cover this second circuit 32 on the direction vertical with second circuit 32 of this conductive layer 34.Specifically, has spacer region between first circuit 31 and second circuit 32.Further, conductive layer 34 is crossed over first circuit 31, spacer region and second circuit 32.

In one embodiment, conductive layer 34 is made by tin indium oxide (ITO).Patterning protective layer 33 can comprise the ground floor 331 and the second layer 332, and this ground floor 331 has the P-SiNx component, and this second layer 332 has the Ge-SiNx component.

The present invention also provides a kind of manufacture method of array base palte 30, comprises following steps.Substrate 39 is provided.Form first circuit 31 parallel to each other and second circuit 32 on this substrate 39.Form patterning protective layer 33 on this substrate 39 and cover this first circuit 31 and this second circuit 32, wherein this patterning protective layer 33 has opening 333 and exposes this first circuit 31 of part.Form patterned conductive layer 34 in this opening 333, wherein this conductive layer 34 extends on the direction vertical with this second circuit 32 and covers this second circuit 32.

In the step that forms patterned conductive layer 34, the coverage rate of this conductive layer 34 is crossed over this first circuit 31 and this second circuit 32.

For further specifying beneficial effect of the present invention, see also Fig. 5 and Fig. 6, Fig. 5 is the pad 34 of array base palte 50 of one embodiment of the invention schematic diagram during with IC piece (bump) 60 contrapositions, Fig. 6 is the schematic diagram in the B-B cross section among Fig. 5.Array base palte 50 is similar to above-mentioned array base palte 30, does not repeat them here.IC piece 60 even there is certain deviation amount (Shift) in the processing procedure, still can obtain maximum pressing area by pad 34 pressings of conducting particles 61 with array base palte 50.

By the present invention, conductive layer covers adjacent traces, can avoid the conducting particles pressure to wear adjacent traces and cause short circuit; Simultaneously, it is big that the COG processing procedure can be offset quantitative change, and production stability is improved.

The present invention is described by above-mentioned related embodiment, yet the foregoing description is only for implementing example of the present invention.Must be pointed out that the embodiment that has disclosed does not limit the scope of the invention.On the contrary, change of being done and retouching without departing from the spirit and scope of the present invention all belongs to scope of patent protection of the present invention.

Claims

1. array base palte is characterized in that comprising:

Substrate;

First circuit is arranged on this substrate;

Second circuit is arranged on this substrate in the mode parallel with this first circuit;

The patterning protective layer is arranged on this substrate and covers this first circuit and this second circuit, and has opening and expose this first circuit of part;

Conductive layer is arranged in this opening and contacts with this first circuit, and this conductive layer extends on the direction vertical with this second circuit and covers this second circuit.

2. array base palte as claimed in claim 1 is characterized in that: this conductive layer is made by tin indium oxide.

3. array base palte as claimed in claim 1 is characterized in that: this patterning protective layer comprises the ground floor and the second layer, and this ground floor has the P-SiNx component, and this second layer has the Ge-SiNx component.

4. array base palte as claimed in claim 1 is characterized in that: have spacer region between this first circuit and this second circuit.

5. array base palte as claimed in claim 4 is characterized in that: this conductive layer is crossed over this first circuit, this spacer region and this second circuit.

6. the manufacture method of an array base palte is characterized in that comprising:

Substrate is provided;

Form first circuit parallel to each other and second circuit on this substrate;

Form the patterning protective layer on this substrate and cover this first circuit and this second circuit, wherein this patterning protective layer has opening and exposes this first circuit of part;

Form patterned conductive layer in this opening, wherein this conductive layer extends on the direction vertical with this second circuit and covers this second circuit.

7. manufacture method as claimed in claim 6 is characterized in that: in the step that forms patterned conductive layer, the coverage rate of this conductive layer is crossed over this first circuit and this second circuit.