CN101847995A - High-precision digital-to-analog converter and method for improving resistor matching precision thereof - Google Patents
High-precision digital-to-analog converter and method for improving resistor matching precision thereof Download PDFInfo
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- CN101847995A CN101847995A CN 201010151530 CN201010151530A CN101847995A CN 101847995 A CN101847995 A CN 101847995A CN 201010151530 CN201010151530 CN 201010151530 CN 201010151530 A CN201010151530 A CN 201010151530A CN 101847995 A CN101847995 A CN 101847995A
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Abstract
The invention discloses a high-precision digital-to-analog converter and a method for improving resistor matching precision. The converter comprises a decoder, an R-2R resistor network and a (m, n)-bit binary data input end, wherein the output end of the decoder is connected with a common resistor R network, the output end of the common resistor R network is connected with a comparator, and the output end of the R-2R resistor network is connected with the other input end of the comparator. In the method for improving resistor matching precision, all basic resistor units R in the common resistor R network and the R-2R resistor network are arranged around a certain centroid in up-down and left-wight symmetry to form a symmetrical resistor matrix. The invention effectively improves the precision of a low-level resistor, thereby improving the conversion precision of the digital-to-analog converter, reducing the chip area, and having the advantage of high ratio of performance to price. The high-precision digital-to-analog converter and the method for improving resistor matching precision thereof, which are provided by the invention, are applied to 30MHz radio frequency transmitters.
Description
Technical field
The present invention relates to a kind of electronic device and a kind of method that improves this electronic device precision, the method for particularly a kind of high-precision digital-to-analog converter and raising resistor matching precision thereof.
Background technology
Tradition R-2R ladder is a structure very commonly used in the digital analog converter, introduces the operation principle of R-2R ladder network digital analog converter below.R-2R ladder network with reference to shown in Figure 1 has:
In Fig. 1 R-2R resistor ladder
R4’＝2R
R4＝2R//2R＝R
R3’＝R+R4＝2R
R3＝2R//R3’＝R
The rest may be inferred, to all i, and Ri '=2R, so obtain following current relationship:
I1＝Vref/2R
I2＝Vref/4R
I3＝Vref/8R
I4＝Vref/16R
Like this, the R-2R ladder promptly can be used for obtaining the binary weighting electric current, and simultaneously only with the resistance value R of a single size, 2R can connect with two resistance R and obtain, and the R-2R method has provided less size and accuracy preferably like this.
Fig. 2 is the 4 bit digital analogue converters of realizing with the R-2R ladder network, and the circuit based on this R-2R has,
Ir＝Vref/(2R)
With
In the digital analog converter of realizing with the R-2R electric resistance array, the precision of R-2R resistance has determined the resolution of digital analog converter.Yet, R-2R resistance is because the relation of position distribution, cause the R-2R resistance can be not identical, layout R-2R resistance how, be the key of finishing the R-2R digital analog converter, traditional digital analog converter cost performance is all very low, or conversion accuracy height but chip area causes cost very high greatly, reduce chip area but cause conversion accuracy low, can't on conversion accuracy and chip area, obtain a good balance point all the time.
Summary of the invention
In order to solve above-mentioned technical problem, the purpose of this invention is to provide a kind of conversion accuracy height and the little high-precision digital-to-analog converter of chip area.
Another object of the present invention provides a kind of method that can improve the little raising resistor matching precision of digital analog converter conversion accuracy and area occupied.
The technical solution adopted for the present invention to solve the technical problems is:
High-precision digital-to-analog converter, comprise decoder, R-2R resistor network and (m, n) bit binary data input, described high m bit binary data input is connected with the input of decoder, described low n bit binary data input is connected with the input of R-2R resistor network, the output of described decoder is connected with conventional, electric-resistance R network, the output of described conventional, electric-resistance R network is connected with comparator, and the output of described R-2R resistor network is connected with another input of comparator.
Further, the figure place of described (m, n) binary number is 10.
Further, described m is 5, and n is 5.
Further, described decoder is the 5-31 decoder.
Further, described comparator comprises an operational amplifier, and the in-phase input end of described operational amplifier connects the mean value of reference voltage, and the out-phase input of described operational amplifier is connected with the output of operational amplifier by a resistance R _ f.
A kind of method that improves resistor matching precision, the layout of all basic resistance unit R is the center with a certain barycenter in described conventional, electric-resistance R network and the R-2R resistor network, symmetry and left-right symmetric form symmetrical resistor matrix up and down.
Further, described radix position resistance and even bit resistance be evenly distributed on described resistor matrix barycenter up and down and about.
Further, the line between each resistance on the described resistor matrix is that metal layer conductive line connects.
Further, equivalent resistance R is also arranged in unnecessary room on the described resistor matrix.
Further, described resistor matrix is the matrix of 6 row, 8 row.
The invention has the beneficial effects as follows: the present invention adopts (m, n) position R-2R digital analog converter, wherein low n position binary digit weighted code is the R-2R resistor network, high m position binary digit weighted code is the segmented model of R resistor network, effectively improved the precision of low level resistance, and then the conversion accuracy of raising digital analog converter, reduce chip area, have the high advantage of cost performance.
Another beneficial effect of the present invention is: the present invention adopts the common centroid symmetrical structure to come layout R-2R structure, effectively improves R-2R architecture digital analog converter resistor matching precision, realizes high-precision R-2R digital analog converter with less area and power consumption.
The present invention has finished 30MHz radio frequency sending set DAC with less area and power consumption, than saving very big power consumption and area with current mode DAC.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples.
Fig. 1 is traditional R-2R circuit theory diagrams;
Fig. 2 is the digital to analog converter circuit theory diagrams;
Fig. 3 is a circuit block diagram of the present invention;
Fig. 4 is circuit theory diagrams of the present invention;
Fig. 5 is a resistor matrix layout of the present invention.
Embodiment
With reference to Fig. 3, high-precision digital-to-analog converter, comprise decoder 1, R-2R resistor network 3 and (m, n) bit binary data input, described high m bit binary data input is connected with the input of decoder 1, described low n bit binary data input is connected with the input of R-2R resistor network 3, the output of described decoder 1 is connected with conventional, electric-resistance R network 2, the output of described conventional, electric-resistance R network 2 is connected with comparator 4, and the output of described R-2R resistor network 3 is connected with another input of comparator 4.
With further reference to Fig. 4, the figure place of described (m, n) binary number is 10.
Further, described m is 5, and n is 5.
Further, described decoder 1 is the 5-31 decoder.
Further, described comparator 4 comprises an operational amplifier, and the in-phase input end of described operational amplifier connects the mean value of reference voltage, and the out-phase input of described operational amplifier is connected with the output of operational amplifier by a resistance R _ f.
A kind of method that improves resistor matching precision, the layout of all basic resistance unit R is the center with a certain barycenter in described conventional, electric-resistance R network 2 and the R-2R resistor network 3, symmetry and left-right symmetric form symmetrical resistor matrix up and down.
Further, described radix position resistance and even bit resistance be evenly distributed on described resistor matrix barycenter up and down and about.
Further, the line between each resistance on the described resistor matrix is that metal layer conductive line connects.
Further, equivalent resistance R is also arranged in unnecessary room on the described resistor matrix.
Further, described resistor matrix is the matrix of 6 row, 8 row.
Fig. 3 is 10 R-2R digital analog converter structures, and the location layout of resistance is the key that realizes the high-precision digital-to-analog transducer, b0, b1 among Fig. 3 ..., b9 is the input data, wherein b0 is a low data, b9 is a high position data..D1 is to the data that obtain after d31 is high 5 bit data (b5 is to b9) decoding, sw0, sw1 ..., sw35 is the two-phase switch, when the data bit of control switch was 1, switch met Vref+, when the data bit of control switch was 0, switch met Vref-.
R1=R2=...=R31=R1 '=R2 '=R3 '=R4 '=R5 '=RA=RB=RC=RD=RE=RF=R, Rf is the feedback resistance of concatenation operation amplifier, and the positive input terminal of operational amplifier connects common-mode voltage Vcm=((Vref-)+(Vref+))/2.
With reference to the common centroid topology layout of the present invention of Fig. 5 form:
R1 ', R2 ' ..., R5 ' and RA, RB ..., RF layout such as form 1, connect binary decoder resistance R 1, R2 ..., R31 is symmetrical centre with the common centroid with vertical direction in the horizontal direction, the distribution of resistance of even number and odd mark is on the both sides of public barycenter, Rdummy is a unnecessary room, can put the resistance with the R equivalence.All smaller with the error of each resistance of vertical direction so in the horizontal direction, eliminated the influence of change in location to resistance value..Simultaneously, forbid line between each resistance of cloth on the resistance.Use this layout method, can reach the requirement of 10 bit digital analog converters.
More than be that preferable enforcement of the present invention is specified, but the invention is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of spirit of the present invention, modification that these are equal to or replacement all are included in the application's claim institute restricted portion.
Claims (10)
1. high-precision digital-to-analog converter, it is characterized in that: comprise decoder (1), R-2R resistor network (3) and (m, n) bit binary data input, described high m bit binary data input is connected with the input of decoder (1), described low n bit binary data input is connected with the input of R-2R resistor network (3), the output of described decoder (1) is connected with conventional, electric-resistance R network (2), the output of described conventional, electric-resistance R network (2) is connected with comparator (4), and the output of described R-2R resistor network (3) is connected with another input of comparator (4).
2. high-precision digital-to-analog converter according to claim 1 is characterized in that: the figure place of described (m, n) binary number is 10.
3. high-precision digital-to-analog converter according to claim 2 is characterized in that: described m is 5, and n is 5.
4. high-precision digital-to-analog converter according to claim 3 is characterized in that: described decoder (1) is the 5-31 decoder.
5. high-precision digital-to-analog converter according to claim 4, it is characterized in that: described comparator (4) comprises an operational amplifier, the in-phase input end of described operational amplifier connects the mean value of reference voltage, and the out-phase input of described operational amplifier is connected with the output of operational amplifier by a resistance R _ f.
6. according to each a kind of method that improves resistor matching precision of claim 1 to 5, it is characterized in that: the layout of all basic resistance unit R is the center with a certain barycenter in described conventional, electric-resistance R network (2) and the R-2R resistor network (3), symmetry and left-right symmetric form symmetrical resistor matrix up and down.
7. a kind of method that improves resistor matching precision according to claim 6 is characterized in that: described radix position resistance and even bit resistance be evenly distributed on described resistor matrix barycenter up and down and about.
8. according to claim 6 or 7 described a kind of methods that improve resistor matching precision, it is characterized in that: the line between each resistance on the described resistor matrix is that metal layer conductive line connects.
9. according to claim 6 or 7 described a kind of methods that improve resistor matching precision, it is characterized in that: equivalent resistance R is also arranged in unnecessary room on the described resistor matrix.
10. according to claim 6 or 7 described a kind of methods that improve resistor matching precision, it is characterized in that: described resistor matrix is the matrix of 6 row, 8 row.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114050829A (en) * | 2021-10-08 | 2022-02-15 | 吉林大学 | Precision programmable digital-to-analog converter based on FPGA and method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1341293A (en) * | 1999-12-21 | 2002-03-20 | 松下电器产业株式会社 | High-precision D-A converter circuit |
| CN101656540A (en) * | 2008-08-18 | 2010-02-24 | 旺宏电子股份有限公司 | Digital to analog converter and method thereof |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1341293A (en) * | 1999-12-21 | 2002-03-20 | 松下电器产业株式会社 | High-precision D-A converter circuit |
| CN101656540A (en) * | 2008-08-18 | 2010-02-24 | 旺宏电子股份有限公司 | Digital to analog converter and method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114050829A (en) * | 2021-10-08 | 2022-02-15 | 吉林大学 | Precision programmable digital-to-analog converter based on FPGA and method thereof |
| CN114050829B (en) * | 2021-10-08 | 2024-04-19 | 吉林大学 | FPGA-based digital-analog converter with programmable precision and method thereof |
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Application publication date: 20100929 |