CN101847655A - Trench grate capable of improving trench grate MOS device performance and manufacture method thereof - Google Patents
Trench grate capable of improving trench grate MOS device performance and manufacture method thereof Download PDFInfo
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- CN101847655A CN101847655A CN201010153744A CN201010153744A CN101847655A CN 101847655 A CN101847655 A CN 101847655A CN 201010153744 A CN201010153744 A CN 201010153744A CN 201010153744 A CN201010153744 A CN 201010153744A CN 101847655 A CN101847655 A CN 101847655A
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Abstract
The invention provides a trench grate capable of improving trench grate MOS device performance and manufacture method thereof. In the prior art, the bottom end part of a grate dielectric layer is only silicon oxide, thereby grate drain capacitance is too large and in the manufacture process, over etching tends to appear, damage a silicon substrate and influence the performance of the device. The trench grate capable of improving the trench grate MOS device performance comprises the grate dielectric layer and a polycrystal grate layer, which are superposed in a grate groove. The grate dielectric layer is provided with a side wall part and a bottom end part, which are respectively arranged at the side wall and the bottom end of the grate groove. The side wall part is the silicon oxide. The bottom end part comprises a first silicon oxide layer, a chemical mechanical polishing stop layer and a second silicon oxide layer, which are superposed in turn. When the chemical mechanical polishing process of the silicon oxide proceeds, the trench grate manufacture method stops on the chemical mechanical polishing stop layer. The invention can prevent the over etching from damaging the silicon substrate and the performance of the device and can reduce the grate drain capacitance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of trench gate and manufacture method thereof that improves trench grate MOS device performance.
Background technology
In power MOS (Metal Oxide Semiconductor) device, traditional surperficial grid structure exists the big and high problem of power consumption of on state resistance, can't well satisfy the demand of power device, so trench grate MOS device just arises at the historic moment, it uses grooving technology and medium fill process to make trench gate, can access lower on state resistance, so trench grate MOS device has obtained widespread usage in low pressure range.
Referring to Fig. 1, it is the composition structural representation of the trench gate of trench grate MOS device in the prior art, as shown in the figure, trench gate of the prior art is produced in the silicon substrate 1, it comprises gate dielectric layer 2 and the polycrystalline grid layer 3 that is layered in the gate trench, this gate dielectric layer 2 has the sidewall sections 20 and the bottom part 22 of gate trench sidewalls of laying respectively at and bottom, and this side wall portion 20 and bottom part 22 are silica.The technology of making trench gate in the prior art may further comprise the steps: (1), a silicon substrate is provided; (2), on silicon substrate, carry out etching technics and form gate trench; (3), by chemical vapor deposition method for example high density plasma CVD (HDP CVD) technology in groove, fill silica; (4), carry out chemico-mechanical polishing (CMP) technology and remove the outer silica of gate trench; (4), carry out wet-etching technology and form gate dielectric layer; (5), carry out chemical vapor deposition method deposit spathic silicon on gate dielectric layer; (6), carry out CMP (Chemical Mechanical Polishing) process and remove the outer polysilicon of gate trench.
During the CMP technology of above-mentioned prior art trench gate manufacture craft in carrying out step (4) because the selection of silica and silicon is smaller, be difficult to grab accurately polishing end point (endpoint), be prone to the polishing phenomenon and damaged silicon substrate, thereby influence subsequent technique and reduce device performance (for example electric leakage increase and reliability reduction etc.); The bottom part of gate dielectric layer is a silica in addition, for reducing the gate leakage capacitance (Cgd) of trench grate MOS device, need to do the silica of bottom part thick as much as possible, but thicken silicon oxide thickness on-state is increased than resistance and channel resistance, so reduce gate leakage capacitance and be subjected to certain limitation by thickening silicon oxide thickness.
Therefore, how to provide a kind of trench gate that improves trench grate MOS device performance and manufacture method thereof avoiding the polishing damage silicon substrate, and effectively reduce gate leakage capacitance, become the technical problem that industry needs to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide a kind of trench gate and manufacture method thereof that improves trench grate MOS device performance, can avoid the polishing damage silicon substrate and reduce device performance by described trench gate and manufacture method thereof, and can reduce the gate leakage capacitance of trench grate MOS device.
The object of the present invention is achieved like this: a kind of trench gate that improves trench grate MOS device performance, comprise the gate dielectric layer and the polycrystalline grid layer that are layered in the gate trench, this gate dielectric layer has the sidewall sections and the bottom part of gate trench sidewalls of laying respectively at and bottom, this sidewall sections is a silica, and this bottom part comprises first silicon oxide layer, chemico-mechanical polishing stop layer and second silicon oxide layer that stacks gradually.
In the trench gate of above-mentioned improved trench grate MOS device performance, this chemico-mechanical polishing stop layer is silicon nitride or silicon oxynitride.
In the trench gate of above-mentioned improved trench grate MOS device performance, the thickness range of this first silicon oxide layer, chemico-mechanical polishing stop layer and second silicon oxide layer is respectively 100～200 dusts, 200～1000 dusts and 500～3000 dusts.
The present invention also provides a kind of trench gate manufacture method of above-mentioned improved trench grate MOS device performance, may further comprise the steps: a, provide a silicon substrate; B, on silicon substrate, carry out etching technics and form gate trench; C, carry out chemical vapor deposition method and deposit first silicon oxide layer and chemico-mechanical polishing stop layer; D, carry out chemical vapor deposition method deposition media silicon oxide layer; E, carry out CMP (Chemical Mechanical Polishing) process and remove the outer media silicon oxide layer of gate trench; F, carry out wet-etching technology and remove the outer chemico-mechanical polishing stop layer of gate trench; G, carry out wet-etching technology and remove media silicon oxide layer side wall in the gate trench; H, carry out wet-etching technology and remove chemico-mechanical polishing stop layer side wall in the gate trench; I, carry out wet-etching technology and remove the silica do not covered by the chemico-mechanical polishing stop layer; J, carry out chemical vapor deposition method and deposit second silicon oxide layer and polysilicon layer; K, carry out CMP (Chemical Mechanical Polishing) process and remove the outer polysilicon layer of gate trench.
In the trench gate manufacture method of above-mentioned improved trench grate MOS device performance, in step f and step h, the etching liquid of described wet etching is a phosphoric acid.
In the trench gate manufacture method of above-mentioned improved trench grate MOS device performance, in step g and step I, the etching liquid of described wet etching is a dilute hydrofluoric acid.
In the trench gate manufacture method of above-mentioned improved trench grate MOS device performance, in steps d, by high density plasma CVD process deposits media silicon oxide layer.
With the bottom part of gate dielectric layer in the prior art only be silica, thereby cause gate leakage capacitance excessive and be prone to over etching damage silicon substrate and influence device performance and compare, the bottom part that improves the trench gate of trench grate MOS device performance of the present invention comprises first silicon oxide layer that stacks gradually, the chemico-mechanical polishing stop layer and second silicon oxide layer, thereby convenient trench gate of the present invention CMP technology during fabrication stops on the chemico-mechanical polishing stop layer, avoided the performance of over etching damage silicon substrate and device, first silicon oxide layer that stacks gradually in addition, the chemico-mechanical polishing stop layer and second silicon oxide layer can effectively reduce gate leakage capacitance.
Description of drawings
Trench gate and the manufacture method thereof that improves trench grate MOS device performance of the present invention provided by following embodiment and accompanying drawing.
Fig. 1 is the composition structural representation of the trench gate of trench grate MOS device in the prior art;
Fig. 2 is the composition structural representation that improves the trench gate of trench grate MOS device performance of the present invention;
Fig. 3 is the flow chart that improves the trench gate manufacture method of trench grate MOS device performance of the present invention;
Fig. 4 to Figure 12 finishes among Fig. 3 the composition structural representation of trench grate MOS device behind the step S31 to S39.
Embodiment
Below will be described in further detail trench gate and the manufacture method thereof that improves trench grate MOS device performance of the present invention.
Referring to Fig. 2, it is the composition structural representation that improves the trench gate of trench grate MOS device performance of the present invention, as shown in the figure, the trench gate that improves trench grate MOS device performance of the present invention is produced in the silicon substrate 1, it comprises gate dielectric layer 2 ' and the polycrystalline grid layer 3 that is layered in the gate trench, described gate dielectric layer has the sidewall sections 20 and the bottom part 22 ' of gate trench sidewalls of laying respectively at and bottom, and described sidewall sections 20 is a silica.Described bottom part 22 ' comprises first silicon oxide layer 220 ', chemico-mechanical polishing stop layer 222 ' and second silicon oxide layer 224 ' that stacks gradually.Described chemico-mechanical polishing stop layer 222 ' is silicon nitride or silicon oxynitride.The thickness range of described first silicon oxide layer 220 ', chemico-mechanical polishing stop layer 222 ' and second silicon oxide layer 224 ' is respectively 100～200 dusts, 200～1000 dusts and 500～3000 dusts.
In the present embodiment, described chemico-mechanical polishing stop layer 222 ' is a silicon nitride, and the thickness of described first silicon oxide layer 220 ', chemico-mechanical polishing stop layer 222 ' and second silicon oxide layer 224 ' is respectively 200 dusts, 1000 dusts and 1000 dusts.
Referring to Fig. 3, it has shown the flow chart that improves the trench gate manufacture method of trench grate MOS device performance of the present invention, and the trench gate manufacture method that improves trench grate MOS device performance of the present invention is at first carried out step S30, and a silicon substrate is provided.
Then continue step S31, carry out etching technics and form gate trench on silicon substrate, described etching technics is a dry etch process, and etching gas can be carbon tetrafluoride (CF
4) and oxygen (O
2) mist.
Referring to Fig. 4, it has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S31, and as shown in the figure, gate trench 10 is formed on the silicon substrate 1.
Then continue step S32, carry out chemical vapor deposition method and deposit first silicon oxide layer and chemico-mechanical polishing stop layer, the described first silicon oxide layer thickness range is 100～200 dusts; The chemico-mechanical polishing stop layer is silicon nitride or silicon oxynitride, and its thickness range is 200～1000 dusts.In the present embodiment, form first silicon oxide layer by thermal oxidation technology, its thickness is 200 dusts; The chemico-mechanical polishing stop layer is a silicon nitride, and its thickness is 1000 dusts, forms by low-pressure chemical vapor deposition process (LPCVD) deposition.
Referring to Fig. 5, in conjunction with referring to Fig. 4, Fig. 5 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S32, as shown in the figure, first silicon oxide layer 40 and chemico-mechanical polishing stop layer 42 are deposited on successively and comprise on the silicon substrate 1 inside and outside the groove 10, and first silicon oxide layer 40 and chemico-mechanical polishing stop layer 42 corresponding gate trenchs 10 all have corresponding side wall.
Then continue step S33, carry out chemical vapor deposition method deposition media silicon oxide layer.In the present embodiment, by high density plasma CVD technology (HDP CVD) deposition media silicon oxide layer.
Referring to Fig. 6, in conjunction with referring to Fig. 4 and Fig. 5, Fig. 6 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S33, as shown in the figure, media silicon oxide layer 44 covers on the chemico-mechanical polishing stop layer 42, and its corresponding gate trench 10 has corresponding side wall.
Then continue step S34, carry out CMP (Chemical Mechanical Polishing) process and remove the outer media silicon oxide layer of gate trench.
Referring to Fig. 7, in conjunction with referring to Fig. 4 to Fig. 6, Fig. 7 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S34, and as shown in the figure, media silicon oxide layer 44 covers gate trench 10 outer parts and all is removed.
Then continue step S35, carry out wet-etching technology and remove the outer chemico-mechanical polishing stop layer of gate trench, the etching liquid of described wet etching is a phosphoric acid.
Referring to Fig. 8, in conjunction with referring to Fig. 4 to Fig. 7, Fig. 8 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S35, and as shown in the figure, gate trench 10 outer chemico-mechanical polishing stop layers 42 all are removed.
Then continue step S36, carry out wet-etching technology and remove the interior media monox lateral wall of gate trench, the etching liquid of described wet etching is a dilute hydrofluoric acid.
Referring to Fig. 9, in conjunction with referring to Fig. 4 to Fig. 8, Fig. 9 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S36, and as shown in the figure, media silicon oxide layer 44 only keeps at the bottom section of gate trench 10, and other zones all are removed.
Then continue step S37, carry out the chemico-mechanical polishing stop layer side wall that wet-etching technology is removed gate trench, the etching liquid of described wet etching is a phosphoric acid.
Referring to Figure 10, in conjunction with referring to Fig. 2, Fig. 4 to Fig. 9, Figure 10 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S37, as shown in the figure, chemico-mechanical polishing stop layer 42 only keeps and forms the included chemico-mechanical polishing stop layer 222 ' of bottom part 22 ' at the bottom section of gate trench 10.
Then continue step S38, carry out wet-etching technology and remove the silica that is not covered by the chemico-mechanical polishing stop layer, the etching liquid of described wet etching is a dilute hydrofluoric acid.
Referring to Figure 11, in conjunction with referring to Fig. 2, Fig. 4 to Figure 10, Figure 11 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S38, as shown in the figure, bottom part 22 ' included first silicon oxide layer 220 ' and the chemico-mechanical polishing stop layer 222 ' is formed on gate trench 10 bottoms.
Then continue step S39, carry out chemical vapor deposition method and deposit second silicon oxide layer and polysilicon layer.
Referring to Figure 12, in conjunction with referring to Fig. 2, Fig. 4 to Figure 11, Figure 12 has shown the composition structural representation that can improve trench grate MOS device behind the completing steps S39, as shown in the figure, bottom part 22 ' included first silicon oxide layer 220 ', chemico-mechanical polishing stop layer 222 ' and second silicon oxide layer 224 ' is formed on gate trench 10 bottoms.
Then continue step S40, carry out CMP (Chemical Mechanical Polishing) process and remove the outer polysilicon layer of gate trench.The composition structure that can improve trench grate MOS device behind the completing steps S40 as shown in Figure 2.
In sum, the trench gate that improves trench grate MOS device performance of the present invention comprises gate dielectric layer and the polycrystalline grid layer that is layered in the gate trench, described gate dielectric layer has the sidewall sections and the bottom part of gate trench sidewalls of laying respectively at and bottom, described sidewall sections is a silica, described bottom part comprises first silicon oxide layer that stacks gradually, the chemico-mechanical polishing stop layer and second silicon oxide layer, trench gate of the present invention CMP technology during fabrication stops on the chemico-mechanical polishing stop layer, avoid the performance of over etching damage silicon substrate and device, can effectively reduce gate leakage capacitance in addition.
Claims (7)
1. trench gate that can improve trench grate MOS device performance, comprise the gate dielectric layer and the polycrystalline grid layer that are layered in the gate trench, this gate dielectric layer has the sidewall sections and the bottom part of gate trench sidewalls of laying respectively at and bottom, this sidewall sections is a silica, it is characterized in that this bottom part comprises first silicon oxide layer, chemico-mechanical polishing stop layer and second silicon oxide layer that stacks gradually.
2. the trench gate that improves trench grate MOS device performance as claimed in claim 1 is characterized in that, this chemico-mechanical polishing stop layer is silicon nitride or silicon oxynitride.
3. the trench gate that improves trench grate MOS device performance as claimed in claim 1 or 2, it is characterized in that the thickness range of this first silicon oxide layer, chemico-mechanical polishing stop layer and second silicon oxide layer is respectively 100～200 dusts, 200～1000 dusts and 500～3000 dusts.
4. described manufacture method that improves the trench gate of trench grate MOS device performance of claim 1 may further comprise the steps: a, provide a silicon substrate; B, on silicon substrate, carry out etching technics and form gate trench; It is characterized in that this method is further comprising the steps of: c, carry out chemical vapor deposition method and deposit first silicon oxide layer and chemico-mechanical polishing stop layer; D, carry out chemical vapor deposition method deposition media silicon oxide layer; E, carry out CMP (Chemical Mechanical Polishing) process and remove the outer media silicon oxide layer of gate trench; F, carry out wet-etching technology and remove the outer chemico-mechanical polishing stop layer of gate trench; G, carry out wet-etching technology and remove media silicon oxide layer side wall in the gate trench; H, carry out wet-etching technology and remove chemico-mechanical polishing stop layer side wall in the gate trench; I, carry out wet-etching technology and remove the silica do not covered by the chemico-mechanical polishing stop layer; J, carry out chemical vapor deposition method and deposit second silicon oxide layer and polysilicon layer; K, carry out CMP (Chemical Mechanical Polishing) process and remove the outer polysilicon layer of gate trench.
5. the trench gate manufacture method that improves trench grate MOS device performance as claimed in claim 1 is characterized in that, in step f and step h, the etching liquid of described wet etching is a phosphoric acid.
6. the trench gate manufacture method that improves trench grate MOS device performance as claimed in claim 1 is characterized in that, in step g and step I, the etching liquid of described wet etching is a dilute hydrofluoric acid.
7. the trench gate manufacture method that improves trench grate MOS device performance as claimed in claim 1 is characterized in that, in steps d, by high density plasma CVD process deposits media silicon oxide layer.
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| CN201010153744.9A CN101847655B (en) | 2010-04-22 | 2010-04-22 | Trench grate capable of improving trench grate MOS device performance and manufacture method thereof |
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| CN201010153744.9A CN101847655B (en) | 2010-04-22 | 2010-04-22 | Trench grate capable of improving trench grate MOS device performance and manufacture method thereof |
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| CN101847655B CN101847655B (en) | 2014-10-22 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377903A (en) * | 2012-04-28 | 2013-10-30 | 上海华虹Nec电子有限公司 | Method for forming grate trench of deep trench type super junction with trench grates |
| CN104124149B (en) * | 2013-04-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| WO2019184957A1 (en) * | 2018-03-27 | 2019-10-03 | 无锡华润上华科技有限公司 | Trenched split-gate device and method for manufacturing same |
| CN112207877A (en) * | 2020-09-07 | 2021-01-12 | 中国工程物理研究院激光聚变研究中心 | Method for generating spiral groove on surface of asphalt polishing disc in annular polishing |
| CN113035956A (en) * | 2021-02-26 | 2021-06-25 | 中之半导体科技(东莞)有限公司 | Field effect transistor with sunken groove |
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| CN1591798A (en) * | 2003-07-10 | 2005-03-09 | 国际整流器公司 | Process for forming thick oxides on si or sic for semiconductor devices |
| US20060126398A1 (en) * | 2002-06-21 | 2006-06-15 | Micron Technologies, Inc. | NROM memory cell, memory array, related devices and methods |
| US20060205222A1 (en) * | 2002-12-14 | 2006-09-14 | In T Zandt Michael A A | Manufacture of trench-gate semiconductor devices |
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2010
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060126398A1 (en) * | 2002-06-21 | 2006-06-15 | Micron Technologies, Inc. | NROM memory cell, memory array, related devices and methods |
| US20060205222A1 (en) * | 2002-12-14 | 2006-09-14 | In T Zandt Michael A A | Manufacture of trench-gate semiconductor devices |
| CN1591798A (en) * | 2003-07-10 | 2005-03-09 | 国际整流器公司 | Process for forming thick oxides on si or sic for semiconductor devices |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103377903A (en) * | 2012-04-28 | 2013-10-30 | 上海华虹Nec电子有限公司 | Method for forming grate trench of deep trench type super junction with trench grates |
| CN103377903B (en) * | 2012-04-28 | 2016-02-10 | 上海华虹宏力半导体制造有限公司 | The formation method of the gate groove of the deep slot type super junction containing trench gate |
| CN104124149B (en) * | 2013-04-28 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| WO2019184957A1 (en) * | 2018-03-27 | 2019-10-03 | 无锡华润上华科技有限公司 | Trenched split-gate device and method for manufacturing same |
| CN112207877A (en) * | 2020-09-07 | 2021-01-12 | 中国工程物理研究院激光聚变研究中心 | Method for generating spiral groove on surface of asphalt polishing disc in annular polishing |
| CN112207877B (en) * | 2020-09-07 | 2022-04-26 | 中国工程物理研究院激光聚变研究中心 | Method for generating spiral groove on surface of asphalt polishing disc in annular polishing |
| CN113035956A (en) * | 2021-02-26 | 2021-06-25 | 中之半导体科技(东莞)有限公司 | Field effect transistor with sunken groove |
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| CN101847655B (en) | 2014-10-22 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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