CN101847608A - Array substrate and manufacturing method - Google Patents
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- CN101847608A CN101847608A CN200910080891A CN200910080891A CN101847608A CN 101847608 A CN101847608 A CN 101847608A CN 200910080891 A CN200910080891 A CN 200910080891A CN 200910080891 A CN200910080891 A CN 200910080891A CN 101847608 A CN101847608 A CN 101847608A
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Abstract
The invention relates to an array substrate and a manufacturing method. The method for manufacturing the array substrate comprises a first-time masking process, a second-time masking process and a third-time masking process, wherein in the first-time masking process, a first metal layer containing a grid line and a gate electrode is formed on a glass substrate; in the second-time masking process, a first insulating layer is formed, a silicon island, tangent plane patterns for forming rupture surfaces and a second metal layer containing a data line, a source electrode and a drain electrode are formed on the first insulating layer sequentially, and the tangent plane patterns and the data line are arranged at set intervals and are parallel to one another; and in the third-time masking process, a second insulating layer is formed, a pixel electrode electrically connected with the drain electrode of the second metal layer is formed by a stripping process, and the edge of the pixel electrode is positioned on the tangent plane patterns. The array substrate overcomes the defect that ruptured parts of a pixel electrode layer cannot be formed effectively when the pixel electrode layer is deposited in the prior art, ensures the normal operation of the stripping process in the third-time masking process, and improves the process quality.
Description
Technical field
The invention belongs to the liquid crystal indicator field, particularly utilize the array base palte and the manufacture method of 3 mask process.
Background technology
Liquid crystal indicator (Liquid Crystal Display abbreviates LCD as) is a kind of main panel display apparatus (Flat Panel Display abbreviates FPD as).According to the direction of an electric field that drives liquid crystal, liquid crystal indicator is divided into vertical electric field type liquid crystal display device and horizontal electric field type LCD device.Horizontal electric field type LCD device is divided into further: boundary electric field switches (Fringe Field Switching is designated hereinafter simply as FFS) type liquid crystal indicator, and copline is switched (In-Plane Switching abbreviates IPS as) type liquid crystal indicator.
Fig. 1 is the schematic diagram of the process mask process first time in the existing manufacturing method of array base plate.Fig. 2 is the schematic diagram of the process mask process second time in the existing manufacturing method of array base plate.Fig. 3 a is through the schematic diagram of mask process for the third time in the existing manufacturing method of array base plate.Fig. 3 b is the α zone schematic cross-section of deposition second insulating barrier in the mask process for the third time of existing manufacturing method of array base plate.Fig. 3 c is the α zone schematic cross-section after developing in the mask process for the third time of existing manufacturing method of array base plate.Fig. 3 d is the α zone schematic cross-section that carries out in the mask process for the third time of existing manufacturing method of array base plate after the etching.Fig. 3 e is the α zone schematic cross-section that carries out in the mask process for the third time of existing manufacturing method of array base plate after the ashing.Fig. 3 f is the α zone schematic cross-section of pixel deposition electrode layer in the mask process for the third time of existing manufacturing method of array base plate.Shown in Fig. 1～Fig. 3 f, in the process of existing manufacturing array substrate, in order to reduce investment and to improve output, the method by the array base palte of 3 mask process manufacturing liquid crystal indicators has appearred, be specially:
Mask process deposits and the first metal layer for the first time, forms grid line 1 and common wire 2 with a dull mask plate (full tone mask);
Mask process deposits first insulating barrier, semiconductor layer and second metal level successively for the second time, forms silicon island 4, thin film transistor channel, data wire 5, source electrode 51 and drain electrode 52 with two mask plates (dual tone mask) of transferring;
Mask process deposits second insulating barrier 6 for the third time, forms via hole with two mask plates of transferring, and residual photoresist 8 is carried out ashing, and the pixel deposition electrode layer, forms pixel electrode after peeling off (lift off) residual photoresist.
But in mask process for the third time, form after the via hole, when carrying out ashing, the photoresist of via area, second insulating barrier and first insulating barrier can be removed simultaneously, thereby form an inclined-plane that gradient is little.Therefore after the pixel deposition electrode layer, pixel electrode layer does not have the part of fracture, has caused can't removing photoresist and be positioned at this pixel electrode above photoresist in stripping technology, has promptly caused normally carrying out stripping technology.
Summary of the invention
The purpose of this invention is to provide a kind of array base palte and manufacture method, to overcome the defective that occurs because of the part that can not effectively form the pixel electrode fault rupture in the prior art.
For achieving the above object, the invention provides a kind of manufacture method of array base palte, comprising: mask process for the first time forms the first metal layer that includes grid line and gate electrode on glass substrate; Mask process for the second time, on the described glass substrate of the process described first time of mask process, be formed for covering first insulating barrier of described the first metal layer and described substrate, and second metal level that on described first insulating barrier, forms the silicon island successively, is used to form the tangent plane pattern of the plane of disruption and includes data wire, source electrode and drain electrode, described tangent plane pattern and described data wire are separated with setpoint distance, and parallel with described data wire; And mask process for the third time, on the described glass substrate of the process described second time of mask process, be formed for covering second insulating barrier of whole described glass substrate, and form the pixel electrode that is electrically connected with the drain electrode of described second metal level by stripping technology, the edge of described pixel electrode is positioned at above the described tangent plane pattern.
Wherein, described tangent plane pattern also is separated with setpoint distance with described grid line, and parallel with described grid line, and is positioned at the top of described tangent plane pattern with the edge of the contiguous pixel electrode of described grid line.
Wherein, described first time, mask process was specially: form the first metal layer that includes common wire, grid line and gate electrode on glass substrate, described tangent plane pattern also is separated with setpoint distance with described common wire, and parallel, and be positioned at the top of described tangent plane pattern with the edge of the contiguous pixel electrode of described common wire with described common wire.
Wherein, when forming described second metal level, adopt with the described second metal level identical materials and form described tangent plane pattern simultaneously.
For achieving the above object, the present invention also provides a kind of array base palte, comprising: gate electrode and the grid line that is electrically connected with described gate electrode are positioned on the glass substrate; First insulating barrier is positioned at described grid electricity and above the described grid line; The silicon island is positioned at described gate electrode top; Source electrode and drain electrode are positioned at above the described silicon island, are provided with thin film transistor channel between described source electrode and the described drain electrode, and described source electrode is electrically connected with data wire; The tangent plane pattern that is used to form the plane of disruption is parallel with described data wire or described grid line; Second insulating barrier covers whole described glass substrate; Pixel electrode is electrically connected with drain electrode by the via hole of offering on described second insulating barrier.
Wherein, when described tangent plane pattern was parallel with described data wire, the edge of the described pixel electrode of contiguous described data wire was positioned at described tangent plane pattern top.
Wherein, when described tangent plane pattern was parallel with described grid line, the edge of the described pixel electrode of contiguous described grid line was positioned at described tangent plane pattern top.
Wherein, the material of described tangent plane pattern is identical with the material of described data wire.
For achieving the above object, the present invention also provides a kind of array base palte, comprising: grid line and common wire are positioned on the glass substrate; First insulating barrier is positioned at described grid line and above the described common wire; The silicon island is positioned at described grid line top; Source electrode and drain electrode be positioned at described silicon island above, be provided with thin film transistor channel between described source electrode and the described drain electrode, described source electrode is electrically connected with data wire, and is provided with the tangent plane pattern that is used to form the plane of disruption between described data wire and pixel electrode area; Second insulating barrier covers whole described glass substrate, and described second insulating barrier corresponding with described drain electrode is provided with via hole; Pixel electrode is positioned at above described second insulating barrier, is electrically connected with described drain electrode by the via hole corresponding with described drain electrode.
Wherein, between described grid line and described pixel electrode area, also be provided with the tangent plane pattern that is used to form the plane of disruption.
Wherein, described tangent plane pattern is made of black matrix material and metal material, and described black matrix material is positioned at above the described metal material.
The present invention is by forming the mode of tangent plane pattern between pixel electrode area and data wire in the mask process in the second time, data wire side at this tangent plane pattern in mask process for the third time forms the plane of disruption, thereby can be in the part that forms fracture in the masking process for the third time during the pixel deposition electrode layer effectively, can not form the defective of the part of pixel electrode fault rupture when having overcome pixel deposition electrode layer in the prior art effectively, guarantee normally carrying out of in mask process for the third time stripping technology, improved processing quality.In addition, also can prevent light leakage phenomena between pixel electrode area and the data wire at the tangent plane pattern between pixel electrode area and the data wire.
Below by drawings and Examples, technical scheme of the present invention is described in further detail.
Description of drawings
Fig. 1 is the schematic diagram of the process mask process first time in the existing manufacturing method of array base plate;
Fig. 2 is the schematic diagram of the process mask process second time in the existing manufacturing method of array base plate;
Fig. 3 a is through the schematic diagram of mask process for the third time in the existing manufacturing method of array base plate;
Fig. 3 b is the α zone schematic cross-section of deposition second insulating barrier in the mask process for the third time of existing manufacturing method of array base plate;
Fig. 3 c is the α zone schematic cross-section after developing in the mask process for the third time of existing manufacturing method of array base plate;
Fig. 3 d is the α zone schematic cross-section that carries out in the mask process for the third time of existing manufacturing method of array base plate after the etching;
Fig. 3 e is the α zone schematic cross-section that carries out in the mask process for the third time of existing manufacturing method of array base plate after the ashing;
Fig. 3 f is the α zone schematic cross-section of pixel deposition electrode layer in the mask process for the third time of existing manufacturing method of array base plate;
Fig. 4 is the flow chart of first embodiment of manufacturing method of array base plate of the present invention;
Fig. 5 is the flow chart of second embodiment of manufacturing method of array base plate of the present invention;
Fig. 6 is the schematic diagram of the process mask process first time among second embodiment of manufacturing method of array base plate of the present invention;
Fig. 7 is the schematic diagram of the process mask process second time among second embodiment of manufacturing method of array base plate of the present invention;
Fig. 8 a among second embodiment of manufacturing method of array base plate of the present invention through the schematic diagram of mask process for the third time;
Fig. 8 b is the β zone schematic cross-section of deposition second insulating barrier in the mask process for the third time of second embodiment of manufacturing method of array base plate of the present invention;
β zone schematic cross-section after developing in the mask process for the third time of Fig. 8 c for second embodiment of manufacturing method of array base plate of the present invention;
Carry out the β zone schematic cross-section after the etching in the mask process for the third time of Fig. 8 d for second embodiment of manufacturing method of array base plate of the present invention;
Carry out the β zone schematic cross-section after the ashing in the mask process for the third time of Fig. 8 e for second embodiment of manufacturing method of array base plate of the present invention;
Fig. 8 f is the β zone schematic cross-section of pixel deposition electrode layer in the mask process for the third time of second embodiment of manufacturing method of array base plate of the present invention;
Carry out the β zone schematic cross-section behind the stripping technology in the mask process for the third time of Fig. 8 g for second embodiment of manufacturing method of array base plate of the present invention;
Fig. 9 a is the floor map of first embodiment of array base palte of the present invention;
Fig. 9 b is the A-A` schematic cross-section of Fig. 9 a;
Figure 10 a is the floor map of second embodiment of array base palte of the present invention;
Figure 10 b is the B-B` schematic cross-section of Figure 10 a;
Figure 10 c is the C-C` schematic cross-section of Figure 10 a.
Description of reference numerals
The 1-grid line; The 2-common wire; 3-first insulating barrier;
The 4-silicon island; The 5-data wire; 51-source electrode;
The 52-drain electrode; 6-second insulating barrier; The 7-pixel electrode;
The 8-photoresist; 9-tangent plane pattern.
Embodiment
First embodiment of manufacturing method of array base plate of the present invention
Fig. 4 is the flow chart of first embodiment of manufacturing method of array base plate of the present invention.As shown in Figure 4, the manufacturing method of array base plate of present embodiment comprises:
Step 101 forms the first metal layer that includes grid line and gate electrode on glass substrate.
Step 102, on the process described glass substrate of step 101, be formed for covering first insulating barrier of described the first metal layer and described substrate, and second metal level that on described first insulating barrier, forms the silicon island successively, is used to form the tangent plane pattern of the plane of disruption and includes data wire, source electrode and drain electrode, described tangent plane pattern and described data wire are separated with setpoint distance, and parallel with described data wire.
Step 103, on the process described glass substrate of step 102, be formed for covering second insulating barrier of whole described glass substrate, and form the pixel electrode that is electrically connected with the drain electrode of described second metal level by stripping technology, the edge of described pixel electrode is positioned at above the described tangent plane pattern.
In the present embodiment, the corresponding mask process for the first time of step 101, the corresponding mask process for the second time of step 102, step 103 correspondence is mask process for the third time.
Present embodiment is by forming the mode of tangent plane pattern between pixel electrode area and data wire in the mask process in the second time, data wire side at this tangent plane pattern in mask process for the third time forms the plane of disruption, thereby can be in the part that forms fracture in the masking process for the third time during the pixel deposition electrode layer effectively, can not form the defective of the part of pixel electrode fault rupture when having overcome pixel deposition electrode layer in the prior art effectively, guarantee normally carrying out of in mask process for the third time stripping technology, improved processing quality.In addition, also can prevent light leakage phenomena between pixel electrode area and the data wire at the tangent plane pattern between pixel electrode area and the data wire.
Further, in the present embodiment, carry out the second time during mask process, between described grid line and described pixel electrode area, also be formed for forming the tangent plane pattern of the plane of disruption, and described tangent plane pattern and described grid line are separated with setpoint distance, and parallel, and be positioned at the top of described tangent plane pattern with the edge of the contiguous pixel electrode of described grid line with described grid line.At this moment, in follow-up mask process for the third time,, thereby can more effectively guarantee normally carrying out of stripping technology by being positioned at the pixel electrode area plane of disruption all around at the grid line side formation plane of disruption of this tangent plane pattern.
Further, in the present embodiment, described first time, mask process was specially: form the first metal layer that includes common wire, grid line and gate electrode on glass substrate, described tangent plane pattern also is separated with setpoint distance with described common wire, and parallel, and be positioned at the top of described tangent plane pattern with the edge of the contiguous pixel electrode of described common wire with described common wire.At this moment, in follow-up mask process for the third time,, thereby can more effectively guarantee normally carrying out of stripping technology by being positioned at the pixel electrode area plane of disruption all around at the common wire side formation plane of disruption of this tangent plane pattern.
Further, in the present embodiment, carry out the second time during mask process, form a tangent plane pattern that is made of black matrix material and metal material, described black matrix material is positioned at above the described metal material.At this moment, can prevent that the tangent plane pattern is reflective and the various defectives that cause.
Further, in the present embodiment, when forming described second metal level, adopt with the described second metal level identical materials and form described tangent plane pattern simultaneously.
Second embodiment of manufacturing method of array base plate of the present invention
Fig. 5 is the flow chart of second embodiment of manufacturing method of array base plate of the present invention.Fig. 6 is the schematic diagram of the process mask process first time among second embodiment of manufacturing method of array base plate of the present invention.Fig. 7 is the schematic diagram of the process mask process second time among second embodiment of manufacturing method of array base plate of the present invention.Fig. 8 a among second embodiment of manufacturing method of array base plate of the present invention through the schematic diagram of mask process for the third time.Fig. 8 b is the β zone schematic cross-section of deposition second insulating barrier in the mask process for the third time of second embodiment of manufacturing method of array base plate of the present invention.β zone schematic cross-section after developing in the mask process for the third time of Fig. 8 c for second embodiment of manufacturing method of array base plate of the present invention.Carry out the β zone schematic cross-section after the etching in the mask process for the third time of Fig. 8 d for second embodiment of manufacturing method of array base plate of the present invention.Carry out the β zone schematic cross-section after the ashing in the mask process for the third time of Fig. 8 e for second embodiment of manufacturing method of array base plate of the present invention.Fig. 8 f is the β zone schematic cross-section of pixel deposition electrode layer in the mask process for the third time of second embodiment of manufacturing method of array base plate of the present invention.Carry out the β zone schematic cross-section behind the stripping technology in the mask process for the third time of Fig. 8 g for second embodiment of manufacturing method of array base plate of the present invention.Shown in Fig. 5～Fig. 8 g, the manufacturing method of array base plate of present embodiment comprises:
Step 201 deposits the first metal layer on glass substrate, and coating photoresist 8.Adopt a dull mask plate that photoresist 8 is exposed and develop, to keep the photoresist 8 on grid region and the common wire zone.The first metal layer that is not covered by photoresist 8 is carried out etching, form grid line 1 and common wire 2.
Step 202 is depositing first insulating barrier, semiconductor layer, heavy doping n+ type semiconductor layer and second metal level successively through on the glass substrate of step 201.Adopt two an accent that photoresist 8 is exposed and develops, only in data wire 5, source electrode 51, drain electrode 52, silicon island be used to form and keep photoresist 8 above the tangent plane pattern of the plane of disruption, and the photoresist 8 in the thin-film transistor channel region territory between source electrode 51 and drain electrode 52 is thinner than other regional photoresists 8.Second metal level and the semiconductor layer that is not covered by photoresist 8 carried out etching, form data wire 5, source electrode 51, drain electrode 52, silicon island and tangent plane pattern 9.The tangent plane pattern 9 and the pixel region that wherein form between described pixel region and data wire 5 are overlapped, the tangent plane pattern 9 and the pixel region that form between described pixel region and front end grid line are overlapped, and the tangent plane pattern 9 and the pixel region that form between described pixel region and local terminal grid line are overlapped.Then photoresist 8 is carried out ashing, further to remove the photoresist 8 that is positioned at the thin-film transistor channel region territory, and second metal level in thin-film transistor channel region territory carried out complete etching, the semiconductor layer in thin-film transistor channel region territory is carried out partially-etched, to form thin film transistor channel.
In the present embodiment, the corresponding mask process for the first time of step 201, the corresponding mask process for the second time of step 202, step 203 correspondence is mask process for the third time.
Present embodiment is by forming the tangent plane pattern in the second time in the mask process between pixel electrode area and data wire, and between pixel electrode area and grid line, form the mode of tangent plane pattern, data wire side and grid line side at this tangent plane pattern in mask process for the third time form the plane of disruption, thereby can be in the part that forms fracture in the masking process for the third time during the pixel deposition electrode layer effectively, can not form the defective of the part of pixel electrode fault rupture when having overcome pixel deposition electrode layer in the prior art effectively, guarantee normally carrying out of in mask process for the third time stripping technology, improved processing quality.In addition, also can prevent light leakage phenomena between pixel electrode area and the data wire at the tangent plane pattern between pixel electrode area and the data wire.
Further, in the present embodiment, carry out the second time during mask process, deposit after second metal level, continue the black matrix layer of deposition.Can form the tangent plane pattern that is made of black matrix material and metal material like this, described black matrix material is positioned at above the described metal material.At this moment, can prevent that the tangent plane pattern is reflective and the various defectives that cause.
Further, in the present embodiment, when forming described second metal level, adopt with the described second metal level identical materials and form described tangent plane pattern simultaneously.
Further, in the present embodiment, in mask process for the third time, described second insulating barrier that is not covered by described photoresist is carried out etching be specially: described second insulating barrier that is not covered by described photoresist is carried out wet etching, can improve etched speed like this.
First embodiment of array base palte of the present invention
Fig. 9 a is the floor map of first embodiment of array base palte of the present invention.Fig. 9 b is the A-A` schematic cross-section of Fig. 9 a.Shown in Fig. 9 a and Fig. 9 b, the array base palte of present embodiment comprises:
Gate electrode and the grid line that is electrically connected with described gate electrode are positioned on the glass substrate;
First insulating barrier 3 is positioned at described grid electricity and above the described grid line;
Source electrode and drain electrode are positioned at above the described silicon island, are provided with thin film transistor channel between described source electrode and the described drain electrode, and described source electrode is electrically connected with data wire 5;
The tangent plane pattern that is used to form the plane of disruption is parallel with described data wire 5;
Second insulating barrier 6 covers whole described glass substrate;
Present embodiment is by forming the mode of tangent plane pattern between pixel electrode area and data wire, can in follow-up technology, the data wire side at this tangent plane pattern form the plane of disruption, thereby the part that can be in follow-up technology forms fracture during the pixel deposition electrode layer effectively, can not form the defective of the part of pixel electrode fault rupture when having overcome pixel deposition electrode layer in the prior art effectively, guarantee normally carrying out of stripping technology, improved processing quality.In addition, also can prevent light leakage phenomena between pixel electrode area and the data wire at the tangent plane pattern between pixel electrode area and the data wire.
Further, in the present embodiment, can also only the tangent plane pattern be set in the zone of contiguous grid line.Since its can the technical solution problem principle identical with the above embodiments, so here repeat no more.At this moment, the edge that is close to the described pixel electrode of described grid line is positioned at described tangent plane pattern top.
Further, in the present embodiment, between described grid line and described pixel electrode area, also be provided with the tangent plane pattern that is used to form the plane of disruption.At this moment, can form the plane of disruption, thereby can more effectively guarantee normally carrying out of stripping technology by being positioned at the pixel electrode area plane of disruption all around in the grid line side of this tangent plane pattern.
Further, in the present embodiment, when described tangent plane pattern was parallel with described data wire, the edge of the described pixel electrode of contiguous described data wire was positioned at described tangent plane pattern top.
Further, in the present embodiment, described tangent plane pattern is made of black matrix material and metal material, and described black matrix material is positioned at above the described metal material.At this moment, can prevent that the tangent plane pattern is reflective and the various defectives that cause.
Further, in the present embodiment, the material of described tangent plane pattern is identical with the material of described data wire.
Second embodiment of array base palte of the present invention
Figure 10 a is the floor map of second embodiment of array base palte of the present invention.Figure 10 b is the B-B` schematic cross-section of Figure 10 a.Figure 10 c is the C-C` schematic cross-section of Figure 10 a.Shown in Figure 10 a～Figure 10 c, the array base palte of present embodiment comprises:
Gate electrode and the grid line that is electrically connected with described gate electrode are positioned on the glass substrate;
First insulating barrier 3 is positioned at described grid electricity and above the described grid line;
Source electrode and drain electrode are positioned at above the described silicon island, are provided with thin film transistor channel between described source electrode and the described drain electrode, and described source electrode is electrically connected with data wire 5;
The tangent plane pattern that is used to form the plane of disruption is parallel with described data wire 5 or described grid line;
Second insulating barrier 6 covers whole described glass substrate;
Present embodiment is by in the mode that forms the tangent plane pattern between pixel electrode area and the data wire and between pixel electrode area and grid line, can in follow-up technology, data wire side and the grid line side at this tangent plane pattern form the plane of disruption, thereby the part that can be in follow-up technology forms fracture during the pixel deposition electrode layer effectively, can not form the defective of the part of pixel electrode fault rupture when having overcome pixel deposition electrode layer in the prior art effectively, guarantee normally carrying out of stripping technology, improved processing quality.In addition, also can prevent light leakage phenomena between pixel electrode area and the data wire at the tangent plane pattern between pixel electrode area and the data wire.
Further, in the present embodiment, the edge of the described pixel electrode of contiguous described data wire is positioned at described tangent plane pattern top, and the edge of the described pixel electrode of contiguous described grid line is positioned at described tangent plane pattern top.
Further, in the present embodiment, the material of described tangent plane pattern is identical with the material of described data wire.
Further, in the present embodiment, described tangent plane pattern is made of black matrix material and metal material, and described black matrix material is positioned at above the described metal material.At this moment, can prevent that the tangent plane pattern is reflective and the various defectives that cause.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. the manufacture method of an array base palte is characterized in that, comprising:
Mask process forms the first metal layer that includes grid line and gate electrode on glass substrate for the first time;
Mask process for the second time, on the described glass substrate of the process described first time of mask process, be formed for covering first insulating barrier of described the first metal layer and described substrate, and second metal level that on described first insulating barrier, forms the silicon island successively, is used to form the tangent plane pattern of the plane of disruption and includes data wire, source electrode and drain electrode, described tangent plane pattern and described data wire are separated with setpoint distance, and parallel with described data wire; And
Mask process for the third time, on the described glass substrate of the process described second time of mask process, be formed for covering second insulating barrier of whole described glass substrate, and form the pixel electrode that is electrically connected with the drain electrode of described second metal level by stripping technology, the edge of described pixel electrode is positioned at above the described tangent plane pattern.
2. the manufacture method of array base palte according to claim 1, it is characterized in that, described tangent plane pattern also is separated with setpoint distance with described grid line, and parallel with described grid line, and is positioned at the top of described tangent plane pattern with the edge of the contiguous pixel electrode of described grid line.
3. the manufacture method of array base palte according to claim 1, it is characterized in that, described first time, mask process was specially: form the first metal layer that includes common wire, grid line and gate electrode on glass substrate, described tangent plane pattern also is separated with setpoint distance with described common wire, and parallel, and be positioned at the top of described tangent plane pattern with the edge of the contiguous pixel electrode of described common wire with described common wire.
4. according to the manufacture method of the arbitrary described array base palte of claim 1～3, it is characterized in that, when forming described second metal level, adopt with the described second metal level identical materials and form described tangent plane pattern simultaneously.
5. an array base palte is characterized in that, comprising:
Gate electrode and the grid line that is electrically connected with described gate electrode are positioned on the glass substrate;
First insulating barrier is positioned at described grid electricity and above the described grid line;
The silicon island is positioned at described gate electrode top;
Source electrode and drain electrode are positioned at above the described silicon island, are provided with thin film transistor channel between described source electrode and the described drain electrode, and described source electrode is electrically connected with data wire;
The tangent plane pattern that is used to form the plane of disruption is parallel with described data wire or described grid line;
Second insulating barrier covers whole described glass substrate;
Pixel electrode is electrically connected with drain electrode by the via hole of offering on described second insulating barrier.
6. array base palte according to claim 5 is characterized in that, when described tangent plane pattern was parallel with described data wire, the edge of the described pixel electrode of contiguous described data wire was positioned at described tangent plane pattern top.
7. array base palte according to claim 5 is characterized in that, when described tangent plane pattern was parallel with described grid line, the edge of the described pixel electrode of contiguous described grid line was positioned at described tangent plane pattern top.
8. according to the arbitrary described array base palte of claim 5～7, it is characterized in that the material of described tangent plane pattern is identical with the material of described data wire.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015067069A1 (en) * | 2013-11-05 | 2015-05-14 | 京东方科技集团股份有限公司 | Array substrate manufacturing method and through-hole manufacturing method |
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| CN1612344A (en) * | 2003-10-23 | 2005-05-04 | Lg.菲利浦Lcd株式会社 | Thin film transistor substrate for display device and fabricating method thereof |
| CN1707343A (en) * | 2004-06-05 | 2005-12-14 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1612344A (en) * | 2003-10-23 | 2005-05-04 | Lg.菲利浦Lcd株式会社 | Thin film transistor substrate for display device and fabricating method thereof |
| CN1707343A (en) * | 2004-06-05 | 2005-12-14 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015067069A1 (en) * | 2013-11-05 | 2015-05-14 | 京东方科技集团股份有限公司 | Array substrate manufacturing method and through-hole manufacturing method |
| US9379146B2 (en) | 2013-11-05 | 2016-06-28 | Boe Technology Group Co., Ltd. | Method for manufacturing array substrate and method for forming through hole |
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