CN101841509B - Method for estimating and compensating sampling clock offset and receiving device - Google Patents
Method for estimating and compensating sampling clock offset and receiving device Download PDFInfo
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Abstract
The invention relates to the field of communication, in particular to a method for estimating and compensating a sampling clock offset and a receiving device. In the invention, a sampling clock offset is estimated and comprehended by two steps. In the first step, the sampling clock offset is sampled according to two synchronous symbols in a time slot and compensated in the next time slot according to an estimating result; and in the second step, the sampling clock offset of every two adjacent data symbols in the time slot is finely estimated by utilizing the continuous pilot frequency symmetry of the data symbols and the sampling clock offset of the currently received data symbols is compensated according to a current estimating result after the sampling clock offset of every two adjacent data symbols is estimated every time. By the invention, the adjusting speed is greatly improved, and the system can rapidly enter a stable state.
Description
Technical field
The present invention relates to the communications field, particularly the sampling clock offset compensation technique in the communications field.
Background technology
At China Mobile multimedia broadcasting (China Mobile Multimedia Broadcasting, be called for short " CMMB ") in system, analog to digital converter (Analog Digital Converter is called for short " ADC ") sampling clock precision has very large impact to systematic function.When sampling clock offset is very little, within 5ppm, performance institute is influenced less, but existing terminal is faced with the pressure of production cost, and high-precision crystal oscillator cost is corresponding higher, for the crystal oscillator of low precision, is often difficult to meet the required precision of 5ppm.
At present, for the crystal oscillator of low precision, be mainly by the estimation to sampling clock offset and compensation, to meet system requirements.Specifically, as shown in Figure 1, physical layer signal is 1 frame in every 1 second to CMMB system frame structure, is divided into 40 time slots.The length of each time slot is 25ms, comprises a beacon and 53 OFDM symbols.Wherein beacon comprises transmitter mark and 2 identical synchronizing symbols, as shown in Figure 2.According to the feature of ofdm signal, utilize 2 identical synchronizing symbols, estimate sampling clock offset at frequency domain.The sampling clock cycle of supposing transmitting terminal is T
t, the receiving terminal sampling clock cycle is T
r, T under normal circumstances
t≠ T
r.Definition normalization clock cycle deviation is δ
t=(T
r-T
t)/T
r.δ
tthe scope that can follow the tracks of is at-100ppm-100ppm.According to the symmetry of synchronizing symbol subcarrier in frequency domain, can carry out the estimation of sampling clock offset, specifically realize by following steps:
1. calculate 2 conjugation products on the corresponding subcarrier of adjacent synchronizing symbol by following formula:
Wherein, the sequence number that k is pilot sub-carrier, 2 of front and back synchronizing symbol phase place on subcarrier k has increased
when the value of k during corresponding to the pilot sub-carrier of positive frequency part (k=1 ..., 768),
when the value of k during corresponding to the pilot sub-carrier of negative frequency part (k=1280 ..., 2047),
δ
ffor residual frequency offset will.Z
2, kthe data subcarrier of second synchronizing symbol, z
1, kit is the data subcarrier on previous synchronizing symbol.This formula supposes that these 2 synchronizing symbols experience identical channel, H
2, ksecond channel estimation in frequency domain value on synchronizing signal subcarrier k.
2. estimate sample offset
When the value of k during corresponding to the pilot sub-carrier of negative frequency part (k=1280 ..., 2047), above-mentioned formula (1) can do as down conversion:
According to formula (1) and (2), can obtain:
δ
t＝(angle(x
2，k)-angle(x
2，2048-k))/(2×k×2×π)，k＝1，...，768 (3)
Angle (.) is wherein the function that calculates angle.
3. calculate clock skew
Because the calculation operations amount of formula (4) is very large, therefore can simplify as follows:
Can obtain the value of approaching of sampling clock offset
Due to each subcarrier sequence number k difference, need to be multiplied by again a correction factor, for synchronizing symbol, known according to emulation, syndrome is 8/3 proper.
Above-mentioned to utilize synchronizing symbol to estimate sampling clock offset value be the method for relatively commonly using, and each time slot estimates deviant according to method above, and for the rectification building-out of next time slot data, specific implementation flow chart is illustrated in fig. 3 shown below.First the IQ data that ADC gathers pass through compensating module, for initial synchronisation, and δ
tbe set to 0, if the data of treated several time slots, that δ
tcumulative for several time slots estimate above numerical value.Complete after clock skew compensation, through down-sampling, 2 synchronizing symbols are sent into data Buffer (internal memory), sampling clock offset estimation module reads this 2 synchronizing symbols, and the sampling clock offset that carries out this is estimated, the deviant estimating can not directly be given NCO (being equivalent to accumulator), must complete filtering, δ through PI filter
tafter PI filter, make amplitude of variation fluctuation less, send into after NCO, for the partial compensation for the time of next time slot.The deviant that each Farrow filter uses is all the value that a upper time slot time offset estimation value obtains after level and smooth, and the IQ data after down-sampling just can be carried out demodulation like this, obtains the bit stream needing.
But the present inventor's discovery because each time slot only has 2 synchronizing symbols, can only estimate one group of deviant so in 25ms, the adjustment cycle of system is 25ms like this, in the more stable system of crystal oscillator, adjusts and is fine like this.But in existing terminal system, the Crystal (crystal) that often samples is as clock, and this crystal oscillator is in the large environment of variations in temperature, and clock changes greatly, and each time slot adjustment once cannot meet the performance requirement of system.Special when mobile TV is just started working, mobile phone temp meeting acute variation, need to accelerate regulating the speed of sampling clock this time, needs to adjust the requirement that repeatedly could meet system in each time slot.In addition, in the time there is larger sampling clock deviation in system, adopt in this way cannot be very fast synchronous, need sampling clock deviation to be compensated to the scope that system allows for a long time, even in some very large skew, cannot be synchronous, systematic function severe exacerbation.
Summary of the invention
The object of the present invention is to provide a kind of sampling clock offset to estimate and method and the receiving system of compensation, greatly improve regulating the speed of clock skew, saving system enters the time of stable state, has ensured the robustness of system.
For solving the problems of the technologies described above, embodiments of the present invention provide a kind of sampling clock offset to estimate and the method for compensation, comprise following steps:
A. receiving terminal carries out the rough estimate of sampling clock offset to the received signal, and according to the result of rough estimate, the signal receiving in next time slot is carried out the compensation of sampling clock offset; Wherein, the rough estimate of sampling clock offset is counted: the estimation of the sampling clock offset carrying out according to 2 synchronizing symbols in time slot;
B. receiving terminal carries out the thin estimation of sampling clock offset to the signal receiving in next time slot, wherein, carefully being estimated as of sampling clock offset: utilize the symmetry of data symbol continuous pilot, the estimation of the sampling clock offset that every 2 adjacent data symbols are carried out; Receiving terminal going out after sampling clock offset according to 2 adjacent data sign estimation, carries out the compensation of sampling clock offset according to this estimated result to the current data symbol receiving at every turn.
Embodiments of the present invention also provide a kind of receiving system, comprise:
Rough estimate module, for carrying out to the received signal the rough estimate of sampling clock offset, the rough estimate of sampling clock offset is counted: the estimation of the sampling clock offset carrying out according to 2 synchronizing symbols in time slot;
Compensating module, carries out the compensation of sampling clock offset for the signal next time slot being received according to the result of rough estimate;
Thin estimation module, carry out the thin estimation of sampling clock offset for the signal that next time slot is received, wherein, being carefully estimated as of sampling clock offset: utilize the symmetry of data symbol continuous pilot, the estimation of the sampling clock offset that every 2 adjacent data symbols are carried out;
Compensating module also for each going out after sampling clock offset according to 2 adjacent data sign estimation, according to this estimated result, the current data symbol receiving is carried out to the compensation of sampling clock offset.
Compared with prior art, the main distinction and effect thereof are embodiment of the present invention:
The estimation of sampling clock offset and compensation are divided into 2 steps, in the first step, carry out the estimation of sampling clock offset according to 2 synchronizing symbols in time slot, and compensate in next time slot according to estimated result, in second step, utilize the symmetry of data symbol continuous pilot, every adjacent 2 data symbols in time slot are carried out to the thin estimation of sampling clock offset, each going out after sampling clock offset according to 2 adjacent data sign estimation, according to this estimated result, the current data symbol receiving is carried out to the compensation of sampling clock offset.Due in the first step according to synchronizing symbol, find fast the deviation of sampling clock, make within the sampling clock deviation of whole system can narrow down to 10ppm fast, in 1 time slot, to make system reach the scope that can normally work.In second step, utilize the symmetry of data symbol continuous pilot, every 2 adjacent data symbols are just carried out the estimation of a sampling clock offset and carry out partial compensation for the time.In a time slot, include 53 data symbols, therefore in a time slot, just can carry out the estimation of 52 sampling clock offsets, greatly improved and regulated the speed, make system can enter very soon stable state.In addition, special in the special circumstances that occur clock shakiness, existing technology there will be from synchronous regime and becomes desynchronizing state, have a strong impact on the performance of system, and the present invention is in certain clock fluctuation range, be all to ensure that system works is in stable state, system is not easy to occur step-out phenomenon, has ensured the robustness of system works.And it is convenient to realize, the crystal oscillator of low precision can meet the demands, and has effectively saved production cost.
Further, carrying out the time slot of rough estimate, is first time slot in frame structure.Owing to conventionally just the sampling clock deviation of whole system can be adjusted to the scope of normal work in 1 time slot, therefore from the 2nd time slot, can carry out the thin estimation of sampling clock offset, make system can reach stable state in 2 time slots.Thereby the system of greatly having saved enters the time of stable state, make system enter stable state by 20 original time slots and be reduced into 2 time slots and can enter stable state.
Further, to according to 2 adjacent sampling clock offsets that data sign estimation goes out, also need to be multiplied by a correction factor.Sampling clock offset after calibrated, as the estimated result of this sampling clock offset, can further ensure the accuracy of partial compensation for the time.
Further, the current data symbol receiving is carried out in the compensation of sampling clock offset, the sampling clock offset that this estimation need to be obtained, carry out the filtering of PI filter, after completing the filtering of PI filter, add up with the sampling clock offset of last time compensation, the sampling clock offset that the sampling clock offset obtaining after cumulative need compensate as this.By using PI filter to carry out smoothing processing, the big ups and downs of the timing offset value that before and after can avoiding, 2 times are estimated, thus make systematicness more stable.
Brief description of the drawings
Fig. 1 is according to CMMB system frame structure schematic diagram of the prior art;
Fig. 2 is according to beacon infrastructure schematic diagram of the prior art;
Fig. 3 is the schematic diagram with compensation method according to sampling clock offset estimation of the prior art;
Fig. 4 estimates and the method flow diagram compensating according to the sampling clock offset of first embodiment of the invention;
Fig. 5 estimates and the method schematic diagram compensating according to the sampling clock offset of first embodiment of the invention;
Fig. 6 is according to the circuit diagram of Farrow Filter in first embodiment of the invention;
Fig. 7 is according to the circuit diagram of PI filter in first embodiment of the invention.
Embodiment
In the following description, in order to make reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs and the many variations based on following execution mode and amendment, also can realize the each claim of the application technical scheme required for protection.
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to a kind of sampling clock offset and estimates and the method compensating.Present embodiment is applied in China Mobile multimedia broadcasting (CMMB) system, in the present embodiment, the reception of signal is divided into 2 stages: acquisition phase and tracking phase.When system is started working, i.e. acquisition phase, according to 2 synchronizing symbols, estimate sampling clock offset, this is rough estimate, from second time slot, the clock skew estimating according to the last time carries out migration to the current signal of receiving, system enters tracking phase.Like this in the time of the 2nd time slot, the residual bias of just only have-10ppm-10ppm.At tracking phase, can strengthen and adjust frequency, according to the symmetry of data symbol continuous pilot in CMMB system, adopt similar method to estimate residual frequency departure, each data symbol is estimated once, carry out smoothly through PI filter, giving NCO and Farrow Filter is that next data symbol compensates.Thereby make entering after tracking phase, in 1 time slot, just can enter convergence state.
As shown in Figure 4, in step 410, receiving terminal carries out the rough estimate of sampling clock offset to idiographic flow to the signal of first time slot receiving, and carries out sampling clock offset estimation according to 2 synchronizing symbols in first time slot.The specific implementation of carrying out sampling clock offset estimation according to 2 synchronizing symbols in time slot is same as the prior art, does not repeat them here.
Then,, in step 420, receiving terminal, according to the rough estimate result of the sampling clock offset in step 410, to next time slot, carries out the compensation of sampling clock offset to the signal receiving in second time slot.This step is same as the prior art, does not repeat them here.
Then,, in step 430, receiving terminal, from second time slot, carries out the thin estimation of sampling clock offset to the signal receiving in time slot.Wherein, being carefully estimated as of sampling clock offset: utilize the symmetry of data symbol continuous pilot, the estimation of the sampling clock offset that every 2 adjacent data symbols are carried out.And receiving terminal going out after sampling clock offset according to 2 adjacent data sign estimation, carries out the compensation of sampling clock offset according to this estimated result to the current data symbol receiving at every turn.
Specifically, as shown in Figure 5, in the time of acquisition phase (in step 410), receiving terminal system is received IQ data, in system, adopts 2 times of over-samplings, this time, δ
t=0, be equivalent to Farrow Filter and do not compensate, through down-sampling, estimate clock skew δ according to 2 synchronizing symbols
t, obtain initial sampling clock offset estimated value.In the time of tracking phase, initial sampling clock offset estimated value δ
tgive PI filter, adjust the parameter of PI filter, make δ
tdirectly give NCO.Simultaneously, the data of second time slot start to compensate by Farrow Filter, sampling clock offset within only remain ± 10ppm of these data like this, utilize the symmetry of data symbol continuous pilot, every 2 adjacent data symbols are carried out to sampling clock offset estimation, in receiving next symbol, by the sampling clock offset δ going out by 2 data sign estimation receiving recently
tpass through successively PI filter, NCO and Farrow Filter, the data symbol that the next one is received carries out partial compensation for the time (being step 430).
To how to carry out sampling clock offset according to 2 adjacent data symbols estimate to be specifically described below.
First, calculate the conjugation product on 2 adjacent data symbol continuous pilot subcarriers by following formula:
Wherein, the sequence number that k is pilot sub-carrier, when the value of k during corresponding to the pilot sub-carrier of positive frequency part (k=1,23 ..., 1538),
when the value of k during corresponding to the pilot sub-carrier of negative frequency part (k=2558 ..., 4095),
δ
ffor residual frequency offset will, δ
tfor the sampling clock offset of last time estimation; z
n, kthe continuous pilot subcarrier of the rear data symbol in adjacent 2 data symbols, z
n-1, kbe the continuous pilot subcarrier of the previous data symbol in adjacent 2 data symbols, * represents conjugation, and adjacent 2 data symbols stand identical channel, H
n, kit is the channel estimation value on the continuous pilot subcarrier k of the rear data symbol in adjacent 2 data symbols.
Then, difference set of computations C
pphase place
with set C
nphase place
wherein, angle (.) is the function that calculates phase place, C
pfor the set of the k corresponding to positive frequency part pilot sub-carrier, C
nfor the set of the k corresponding to negative frequency part pilot sub-carrier, that is to say C
p=k|k=1,23 ..., 1538}, C
n=k|k=2558 ..., 4095}.
Then, value of approaching of calculating sampling clock skew
In the present embodiment, receiving terminal will calculate
as the estimated result of this sampling clock offset.It should be noted that, the above-mentioned thin estimation that utilizes the sampling clock offset that adjacent 2 data symbols carry out, similar with the existing sampling clock offset estimation that utilizes 2 synchronizing symbols to carry out, but in actual applications, also can realize by other means the thin estimation of sampling clock offset.
Obtaining after the estimated result of this sampling clock offset, mode and the prior art of the current data symbol receiving being carried out to partial compensation for the time according to this estimated result are identical, the sampling clock offset obtaining by this estimation, carry out the filtering of PI filter, after completing the filtering of PI filter, add up with the sampling clock offset of last time compensation, the sampling clock offset that the sampling clock offset obtaining after cumulative need compensate as this.
The compensation of the sampling clock offset to data symbol realizes by Farrow Filter (filter).It will be understood by those skilled in the art that Farrow Filter carrys out work according to filter output clock phase μ and shift command, formed by 5 grades of shift registers, 5 multipliers, 2 adders.Scope-0.5≤μ≤0.5 of clock phase μ.Concrete circuit diagram as shown in Figure 6.Control variables shift order has three states (value of shift order is decided by μ):
1. in the time of shift order=2, from input data sequence, read in two numbers, complete twice shifting function.Utilize 2 new datas and 3 legacy datas, and new μ value, complete calculating, a value of many inputs, normally exports a value;
2. in the time of shift order=1, from input data sequence, read in a number, complete a shifting function.Utilize 1 new data and 4 legacy datas, and new μ value, completing calculating, this is normal condition, inputs a value, exports a value;
3. in the time of shift order=0, need to from input data sequence, not read in number, only utilize 5 legacy datas in register, and new μ value, complete calculating, do not input, export a value more.
NCO is an accumulator, and expression is: NCO (n)=NCO (n-1)+ε.Be combined with FarrowFilter, concrete steps are as follows:
1. each ε that increases, i.e. NCO (n)=NCO (n-1)+ε, ε is the output valve of PI filter, the initial value of accumulator is 0, i.e. NCO (0)=0;
2. the value of adjusting NCO (n), rule is as follows:
If NCO (n) > 0.5, NCO (n)=NCO (n)-1, shift order=2;
If NCO (n) <-0.5, NCO (n)=NCO (n)+1, shift order=0;
If-0.5≤NCO (n)≤0.5, shift order=1;
3. last output clock phase value is to Farrow Filter, μ=NCO (n).
The transfer function of PI filter is,
realize this function with circuit, as shown in Figure 7.Specific works principle is: design a counter, can select different parameter K
p, K
i, to regulate the speed of adjustment, wherein z
-1represent delay time register.In general, K
p, K
ilarger, adjust sooner, but unsmooth, have fluctuation, in system realizes, often select the value of a compromise.By using PI filter to carry out smoothing processing, the big ups and downs of the timing offset value that before and after can avoiding, 2 times are estimated, thus make systematicness more stable.Simulation result shows, after 10-20 time is adjusted, can converge to stationary value, just can reach stable state entering after a time slot of tracking like this.
Be not difficult to find, a kind of solution of 2 step formulas is proposed in the present embodiment: 1. acquisition phase, according to synchronizing symbol, find fast the deviation of sampling clock, within making can the narrow down to fast ± 10ppm of sampling clock deviation of whole system, in 1 time slot, make system reach the scope that can normally work; 2. tracking phase, the sample offset that the data of second time slot estimate according to first time slot compensates by Farrow Filter, so only remaining offset, continuous pilot by data symbol is estimated, partially thin estimated value can obtain sampling time, undertaken smoothly by PI filter, can after 20 estimated value compensation, system reach stable state, because each time slot has 53 data symbols, can estimate 52 time, be partially worth, make system reach stable state 2 time slot the insides like this.Thereby the system of greatly having saved enters the time of stable state, make system enter stable state by 20 original time slots and be reduced into 2 time slots and can enter stable state.In addition, special in the special circumstances that occur clock shakiness, existing technology there will be from synchronous regime and becomes desynchronizing state, have a strong impact on the performance of system, and the present invention is in certain clock fluctuation range, be all to ensure that system works is in stable state, system is not easy to occur step-out phenomenon, all the time make system in stable state, ensured the robustness of system works.
It is worth mentioning that, entering after tracking phase, also 2 synchronizing symbols can be used, estimate one group and be partially worth when residual, that is to say, each time slot can estimate 53 groups and partially be worth when residual.
Second embodiment of the invention relates to a kind of sampling clock offset and estimates and the method compensating.The second execution mode improves on the basis of the first execution mode, and main improvements are: when carry out sampling clock offset estimation according to 2 adjacent data symbols, in the first embodiment, directly by the value of approaching of the sampling clock offset of calculating
as the estimated result of this sampling clock offset.And in the present embodiment, will
be multiplied by again a correction factor, then by after calibrated
as the estimated result δ of this sampling clock offset
t.
Due to the k difference of each subcarrier, therefore to the value of approaching
be multiplied by again a correction factor, can further ensure the accuracy of partial compensation for the time.
Each method execution mode of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the memory of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).Equally, memory can be for example programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), read-only memory (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.
Third embodiment of the invention relates to a kind of receiving system.This receiving system comprises:
Rough estimate module, for carrying out to the received signal the rough estimate of sampling clock offset, the rough estimate of sampling clock offset is counted: the estimation of the sampling clock offset carrying out according to 2 synchronizing symbols in time slot.
Compensating module, carries out the compensation of sampling clock offset for the signal next time slot being received according to the result of rough estimate.
Thin estimation module, carry out the thin estimation of sampling clock offset for the signal that next time slot is received, wherein, being carefully estimated as of sampling clock offset: utilize the symmetry of data symbol continuous pilot, the estimation of the sampling clock offset that every 2 adjacent data symbols are carried out.
Compensating module also for each going out after sampling clock offset according to 2 adjacent data sign estimation, according to this estimated result, the current data symbol receiving is carried out to the compensation of sampling clock offset.
Wherein, thin estimation module comprises following submodule:
Conjugation product calculating sub module, for calculate the conjugation product on the continuous pilot subcarrier of adjacent 2 data symbols by following formula:
Wherein, the sequence number that k is pilot sub-carrier, when the value of k during corresponding to the pilot sub-carrier of positive frequency part (k=1,23 ... .1538),
when the value of k during corresponding to the pilot sub-carrier of negative frequency part (k=2558 ..., 4095),
δ
ffor residual frequency offset will, δ
tfor the sampling clock offset of last time estimation; z
n, kthe continuous pilot subcarrier of the rear data symbol in adjacent 2 data symbols, z
n-1, kthe continuous pilot subcarrier of the previous data symbol in adjacent 2 data symbols,
*represent conjugation, adjacent 2 data symbols stand identical channel, H
n, kit is the channel estimation value on the continuous pilot subcarrier k of the rear data symbol in adjacent 2 data symbols.
Phase calculation submodule, for by following formula set of computations C
pphase place
with set C
nphase place
The value of approaching calculating sub module, for passing through following formula, the value of approaching of calculating sampling clock skew
Estimated result obtains submodule, for what the value of approaching calculating sub module was calculated
as the estimated result of this sampling clock offset.
Compensating module comprises following submodule:
PI filter, carries out filtering output for the sampling clock offset that this estimation is obtained.
Accumulator, for adding up the sampling clock offset of PI filter output and the sampling clock offset of last compensation.
Migration submodule, the sampling clock offset that need compensate as this for the sampling clock offset obtaining after cumulative carries out partial compensation for the time.
It is the signal in China Mobile multimedia broadcasting system that receiving system in present embodiment receives, and the time slot that carries out rough estimate by rough estimate module is first time slot in frame structure.
Be not difficult to find, the first execution mode is the method execution mode corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the first execution mode.The correlation technique details of mentioning in the first execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first execution mode.
Four embodiment of the invention relates to a kind of receiving system.The 4th execution mode improves on the basis of the 3rd execution mode, and main improvements are: carefully estimate that mould also comprises syndrome module, for what the value of approaching calculating sub module was calculated
be multiplied by a correction factor.Estimated result obtains submodule by after calibrated
as the estimated result of this sampling clock offset.
Be not difficult to find, the second execution mode is the method execution mode corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the second execution mode.The correlation technique details of mentioning in the second execution mode is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the second execution mode.
It should be noted that, each unit of mentioning in the each equipment execution mode of the present invention is all logical block, physically, a logical block can be a physical location, also can be a part for a physical location, can also realize with the combination of multiple physical locations, the physics realization mode of these logical blocks itself is not most important, and the combination of the function that these logical blocks realize is the key that just solves technical problem proposed by the invention.In addition, for outstanding innovation part of the present invention, the above-mentioned each equipment execution mode of the present invention is not introduced the unit not too close with solving technical problem relation proposed by the invention, and this does not show that the said equipment execution mode does not exist other unit.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and described, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (12)
1. sampling clock offset is estimated and a method for compensation, it is characterized in that, comprises following steps:
A. receiving terminal carries out the rough estimate of sampling clock offset to the received signal, and according to the result of described rough estimate, the signal receiving in next time slot is carried out the compensation of sampling clock offset; Wherein, the rough estimate of described sampling clock offset is counted: the estimation of the sampling clock offset carrying out according to 2 synchronizing symbols in time slot;
B. receiving terminal carries out the thin estimation of sampling clock offset to the signal receiving in described next time slot, wherein, carefully being estimated as of described sampling clock offset: utilize the symmetry of data symbol continuous pilot, the estimation of the sampling clock offset that every 2 adjacent data symbols are carried out; Described receiving terminal going out after sampling clock offset according to 2 adjacent data sign estimation, carries out the compensation of sampling clock offset according to this estimated result to the current data symbol receiving at every turn.
2. sampling clock offset according to claim 1 is estimated and the method for compensation, it is characterized in that, the estimation of the described sampling clock offset that adjacent 2 data symbols are carried out, comprises following sub-step:
Conjugation product by the continuous pilot subcarrier of described adjacent 2 data symbols of following formula calculating:
Wherein, the sequence number that k is pilot sub-carrier, when the value of k is during corresponding to the pilot sub-carrier of positive frequency part,
when the value of k is during corresponding to the pilot sub-carrier of negative frequency part,
δ
ffor residual frequency offset will, δ
tfor the sampling clock offset of last time estimation; z
n, kthe continuous pilot subcarrier of the rear data symbol in described adjacent 2 data symbols, z
n-1, kbe the continuous pilot subcarrier of the previous data symbol in described adjacent 2 data symbols, * represents conjugation, and described adjacent 2 data symbols stand identical channel, H
n, kit is the channel estimation value on the continuous pilot subcarrier k of the rear data symbol in described adjacent 2 data symbols;
By following formula set of computations C
pphase place
with set C
nphase place
wherein, angle (.) is the function that calculates phase place, C
pfor the set of the k corresponding to positive frequency part pilot sub-carrier, C
nfor the set of the k corresponding to negative frequency part pilot sub-carrier, X
n, kbe described conjugation product;
By the value of approaching of following formula calculating sampling clock skew
By what calculate
as the estimated result of this sampling clock offset.
3. sampling clock offset according to claim 2 is estimated and the method for compensation, it is characterized in that, by described in calculating
before estimated result as this sampling clock offset, also comprise following steps:
Described in inciting somebody to action
be multiplied by a correction factor;
The estimated result of described this sampling clock offset is after calibrated
4. sampling clock offset according to claim 1 is estimated and the method for compensation, it is characterized in that, describedly according to this estimated result, the current data symbol receiving is carried out, in the compensation of sampling clock offset, comprising following sub-step:
The sampling clock offset that this estimation is obtained, carries out the filtering of PI filter, adds up with the sampling clock offset of last time compensation after completing the filtering of PI filter, and the sampling clock offset that the sampling clock offset obtaining after cumulative need compensate as this.
5. estimate and the method for compensation according to the sampling clock offset described in any one in claim 1 to 4, it is characterized in that, the time slot that carries out described rough estimate is first time slot in frame structure.
6. estimate and the method for compensation according to sampling clock offset described in any one in claim 1 to 4, it is characterized in that, described in the signal that receives be the signal in China Mobile multimedia broadcasting system.
7. a receiving system, is characterized in that, comprises:
Rough estimate module, for carrying out to the received signal the rough estimate of sampling clock offset, the rough estimate of described sampling clock offset is counted: the estimation of the sampling clock offset carrying out according to 2 synchronizing symbols in time slot;
Compensating module, carries out the compensation of sampling clock offset for the signal next time slot being received according to the result of described rough estimate;
Thin estimation module, carry out the thin estimation of sampling clock offset for the signal that described next time slot is received, wherein, being carefully estimated as of described sampling clock offset: utilize the symmetry of data symbol continuous pilot, the estimation of the sampling clock offset that every 2 adjacent data symbols are carried out;
Described compensating module also for each going out after sampling clock offset according to 2 adjacent data sign estimation, according to this estimated result, the current data symbol receiving is carried out to the compensation of sampling clock offset.
8. receiving system according to claim 7, is characterized in that, described thin estimation module comprises following submodule:
Conjugation product calculating sub module, the conjugation product on the continuous pilot subcarrier by described adjacent 2 data symbols of following formula calculating:
Wherein, the sequence number that k is pilot sub-carrier, when the value of k is during corresponding to the pilot sub-carrier of positive frequency part,
when the value of k is during corresponding to the pilot sub-carrier of negative frequency part,
δ
ffor residual frequency offset will, δ
tfor the sampling clock offset of last time estimation; z
n, kthe continuous pilot subcarrier of the rear data symbol in described adjacent 2 data symbols, z
n-1, kbe the continuous pilot subcarrier of the previous data symbol in described adjacent 2 data symbols, * represents conjugation, and described adjacent 2 data symbols stand identical channel, H
n, kit is the channel estimation value on the continuous pilot subcarrier k of the rear data symbol in described adjacent 2 data symbols;
Phase calculation submodule, for by following formula set of computations C
pphase place
with set C
nphase place
The value of approaching calculating sub module, for by the value of approaching of following formula calculating sampling clock skew
Estimated result obtains submodule, for what the described value of approaching calculating sub module was calculated
as the estimated result of this sampling clock offset.
9. receiving system according to claim 8, is characterized in that, described thin estimation module also comprises syndrome module, for what the described value of approaching calculating sub module was calculated
be multiplied by a correction factor;
Described estimated result obtains submodule by after calibrated
as the estimated result of described this sampling clock offset.
10. receiving system according to claim 7, is characterized in that, described compensating module comprises following submodule:
PI filter, carries out filtering output for the sampling clock offset that this estimation is obtained;
Accumulator, for adding up the sampling clock offset of described PI filter output and the sampling clock offset of last compensation;
Migration submodule, the sampling clock offset that need compensate as this for the sampling clock offset obtaining after cumulative carries out partial compensation for the time.
11. according to the receiving system described in any one in claim 7 to 9, it is characterized in that, the time slot that carries out described rough estimate is first time slot in frame structure.
12. according to the receiving system described in any one in claim 7 to 9, it is characterized in that, described in the signal that receives be the signal in China Mobile multimedia broadcasting system.
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| CN102790740B (en) * | 2011-05-19 | 2015-04-01 | 上海中兴软件有限责任公司 | Method and device for acquiring signal power of physical uplink control channel |
| CN102185822B (en) * | 2011-05-31 | 2013-07-17 | 电子科技大学 | OFDM/OQAM (Orthogonal Frequency Division Multiplexing/Offset Quadrature Amplitude Modulation) system and time frequency synchronization method thereof |
| CN102332975A (en) * | 2011-06-03 | 2012-01-25 | 北京星网锐捷网络技术有限公司 | Method and device for self-adaptively sampling interface |
| CN102932903B (en) * | 2011-08-08 | 2015-05-20 | 京信通信系统（中国）有限公司 | Uplink synchronization control method and device, and base station |
| CN102955869B (en) * | 2011-08-30 | 2015-04-08 | 国际商业机器公司 | Method and device for evaluating clock skew |
| CN103428151B (en) * | 2012-05-23 | 2017-11-10 | 中兴通讯股份有限公司 | Go the method and device of cyclic prefix |
| CN104467939B (en) * | 2014-12-25 | 2018-02-09 | 中科创达软件股份有限公司 | A kind of method and device for optimizing multiple antennas and receiving |
| CN105490981B (en) * | 2015-12-30 | 2018-11-06 | 合肥东芯通信股份有限公司 | The device and method of adaptive equalization SCO in a kind of LTE system |
| CN108964819B (en) * | 2017-05-19 | 2019-11-26 | 华为技术有限公司 | A kind of clock adjustment, clock jitter calculation method, equipment and system |
| CN110099023B (en) * | 2019-05-17 | 2021-07-27 | 北京智芯微电子科技有限公司 | OFDM system receiver sampling frequency offset compensation device and method |
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